1 /*
2 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef STM32MP2_DEF_H
8 #define STM32MP2_DEF_H
9
10 #include <common/tbbr/tbbr_img_def.h>
11 #ifndef __ASSEMBLER__
12 #include <drivers/st/bsec.h>
13 #endif
14 #include <drivers/st/stm32mp25_rcc.h>
15 #ifndef __ASSEMBLER__
16 #include <drivers/st/stm32mp2_clk.h>
17 #endif
18 #include <drivers/st/stm32mp2_pwr.h>
19 #include <dt-bindings/clock/stm32mp25-clks.h>
20 #include <dt-bindings/clock/stm32mp25-clksrc.h>
21 #include <dt-bindings/gpio/stm32-gpio.h>
22 #include <dt-bindings/reset/stm32mp25-resets.h>
23
24 #ifndef __ASSEMBLER__
25 #include <boot_api.h>
26 #include <stm32mp2_private.h>
27 #include <stm32mp_common.h>
28 #include <stm32mp_dt.h>
29 #include <stm32mp_shared_resources.h>
30 #endif
31
32 /*******************************************************************************
33 * CHIP ID
34 ******************************************************************************/
35 #define STM32MP2_CHIP_ID U(0x505)
36
37 #define STM32MP251A_PART_NB U(0x400B3E6D)
38 #define STM32MP251C_PART_NB U(0x000B306D)
39 #define STM32MP251D_PART_NB U(0xC00B3E6D)
40 #define STM32MP251F_PART_NB U(0x800B306D)
41 #define STM32MP253A_PART_NB U(0x400B3E0C)
42 #define STM32MP253C_PART_NB U(0x000B300C)
43 #define STM32MP253D_PART_NB U(0xC00B3E0C)
44 #define STM32MP253F_PART_NB U(0x800B300C)
45 #define STM32MP255A_PART_NB U(0x40082E00)
46 #define STM32MP255C_PART_NB U(0x00082000)
47 #define STM32MP255D_PART_NB U(0xC0082E00)
48 #define STM32MP255F_PART_NB U(0x80082000)
49 #define STM32MP257A_PART_NB U(0x40002E00)
50 #define STM32MP257C_PART_NB U(0x00002000)
51 #define STM32MP257D_PART_NB U(0xC0002E00)
52 #define STM32MP257F_PART_NB U(0x80002000)
53
54 #define STM32MP2_REV_A U(0x08)
55 #define STM32MP2_REV_B U(0x10)
56 #define STM32MP2_REV_X U(0x12)
57 #define STM32MP2_REV_Y U(0x11)
58 #define STM32MP2_REV_Z U(0x09)
59
60 /*******************************************************************************
61 * PACKAGE ID
62 ******************************************************************************/
63 #define STM32MP25_PKG_CUSTOM U(0)
64 #define STM32MP25_PKG_AL_VFBGA361 U(1)
65 #define STM32MP25_PKG_AK_VFBGA424 U(3)
66 #define STM32MP25_PKG_AI_TFBGA436 U(5)
67 #define STM32MP25_PKG_UNKNOWN U(7)
68
69 /*******************************************************************************
70 * STM32MP2 memory map related constants
71 ******************************************************************************/
72 #define STM32MP_SYSRAM_BASE U(0x0E000000)
73 #define STM32MP_SYSRAM_SIZE U(0x00040000)
74 #define SRAM1_BASE U(0x0E040000)
75 #define SRAM1_SIZE_FOR_TFA U(0x00010000)
76 #define RETRAM_BASE U(0x0E080000)
77 #define RETRAM_SIZE U(0x00020000)
78
79 #define STM32MP_SEC_SYSRAM_SIZE STM32MP_SYSRAM_SIZE
80
81 /* DDR configuration */
82 #define STM32MP_DDR_BASE U(0x80000000)
83 #define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */
84
85 /* DDR power initializations */
86 #ifndef __ASSEMBLER__
87 enum ddr_type {
88 STM32MP_DDR3,
89 STM32MP_DDR4,
90 STM32MP_LPDDR4
91 };
92 #endif
93
94 /* Section used inside TF binaries */
95 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
96 /* 512 Bytes reserved for header */
97 #define STM32MP_HEADER_SIZE U(0x00000200)
98 #define STM32MP_HEADER_BASE (STM32MP_SYSRAM_BASE + \
99 STM32MP_PARAM_LOAD_SIZE)
100
101 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */
102 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
103
104 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \
105 STM32MP_PARAM_LOAD_SIZE + \
106 STM32MP_HEADER_SIZE)
107
108 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \
109 (STM32MP_PARAM_LOAD_SIZE + \
110 STM32MP_HEADER_SIZE))
111
112 #define STM32MP_BL2_RO_SIZE U(0x00020000) /* 128 KB */
113 #define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */
114
115 /* Allocate remaining sysram to BL31 Binary only */
116 #define STM32MP_BL31_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
117 STM32MP_BL2_SIZE)
118
119 #define BL31_PROGBITS_LIMIT STM32MP_BL31_SIZE
120
121 #define STM32MP_BL2_BASE (STM32MP_SYSRAM_BASE + \
122 STM32MP_SYSRAM_SIZE - \
123 STM32MP_BL2_SIZE)
124
125 #define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE
126
127 #define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \
128 STM32MP_BL2_RO_SIZE)
129
130 #define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \
131 STM32MP_SYSRAM_SIZE - \
132 STM32MP_BL2_RW_BASE)
133
134 /* BL2 and BL32/sp_min require 4 tables */
135 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
136
137 /*
138 * MAX_MMAP_REGIONS is usually:
139 * BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup
140 */
141 #if defined(IMAGE_BL31)
142 #define MAX_MMAP_REGIONS 7
143 #else
144 #define MAX_MMAP_REGIONS 6
145 #endif
146
147 /* DTB initialization value */
148 #define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */
149
150 #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \
151 STM32MP_BL2_DTB_SIZE)
152
153 #if defined(IMAGE_BL2)
154 #define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE
155 #define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE
156 #endif
157
158 #if STM32MP_DDR_FIP_IO_STORAGE
159 #define STM32MP_DDR_FW_BASE SRAM1_BASE
160 #define STM32MP_DDR_FW_DMEM_OFFSET U(0x400)
161 #define STM32MP_DDR_FW_IMEM_OFFSET U(0x800)
162 #define STM32MP_DDR_FW_MAX_SIZE U(0x8800)
163 #endif
164
165 #define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE
166 #define STM32MP_FW_CONFIG_BASE STM32MP_SYSRAM_BASE
167
168 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000))
169 #define STM32MP_BL33_MAX_SIZE U(0x400000)
170 #define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \
171 STM32MP_BL33_MAX_SIZE)
172 #define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000)
173 #define STM32MP_SOC_FW_CONFIG_MAX_SIZE U(0x10000) /* 64kB for BL31 DT */
174
175 /*******************************************************************************
176 * STM32MP2 device/io map related constants (used for MMU)
177 ******************************************************************************/
178 #define STM32MP_DEVICE_BASE U(0x40000000)
179 #define STM32MP_DEVICE_SIZE U(0x40000000)
180
181 /*******************************************************************************
182 * STM32MP2 RCC
183 ******************************************************************************/
184 #define RCC_BASE U(0x44200000)
185
186 /*******************************************************************************
187 * STM32MP2 PWR
188 ******************************************************************************/
189 #define PWR_BASE U(0x44210000)
190
191 /*******************************************************************************
192 * STM32MP2 GPIO
193 ******************************************************************************/
194 #define GPIOA_BASE U(0x44240000)
195 #define GPIOB_BASE U(0x44250000)
196 #define GPIOC_BASE U(0x44260000)
197 #define GPIOD_BASE U(0x44270000)
198 #define GPIOE_BASE U(0x44280000)
199 #define GPIOF_BASE U(0x44290000)
200 #define GPIOG_BASE U(0x442A0000)
201 #define GPIOH_BASE U(0x442B0000)
202 #define GPIOI_BASE U(0x442C0000)
203 #define GPIOJ_BASE U(0x442D0000)
204 #define GPIOK_BASE U(0x442E0000)
205 #define GPIOZ_BASE U(0x46200000)
206 #define GPIO_BANK_OFFSET U(0x10000)
207
208 #define STM32MP_GPIOS_PIN_MAX_COUNT 16
209 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8
210
211 /*******************************************************************************
212 * STM32MP2 UART
213 ******************************************************************************/
214 #define USART1_BASE U(0x40330000)
215 #define USART2_BASE U(0x400E0000)
216 #define USART3_BASE U(0x400F0000)
217 #define UART4_BASE U(0x40100000)
218 #define UART5_BASE U(0x40110000)
219 #define USART6_BASE U(0x40220000)
220 #define UART7_BASE U(0x40370000)
221 #define UART8_BASE U(0x40380000)
222 #define UART9_BASE U(0x402C0000)
223 #define STM32MP_NB_OF_UART U(9)
224
225 /* For UART crash console */
226 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000
227 /* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */
228 #define STM32MP_DEBUG_USART_BASE USART2_BASE
229 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE
230 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR
231 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN
232 #define DEBUG_UART_TX_GPIO_PORT 4
233 #define DEBUG_UART_TX_GPIO_ALTERNATE 6
234 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR
235 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI
236 #define DEBUG_UART_TX_EN_REG RCC_USART2CFGR
237 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN
238 #define DEBUG_UART_RST_REG RCC_USART2CFGR
239 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST
240 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR
241 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR
242
243 /*******************************************************************************
244 * STM32MP2 SDMMC
245 ******************************************************************************/
246 #define STM32MP_SDMMC1_BASE U(0x48220000)
247 #define STM32MP_SDMMC2_BASE U(0x48230000)
248 #define STM32MP_SDMMC3_BASE U(0x48240000)
249
250 /*******************************************************************************
251 * STM32MP2 BSEC / OTP
252 ******************************************************************************/
253 /*
254 * 367 available OTPs, the other are masked
255 * - ECIES key: 368 to 375 (only readable by bootrom)
256 * - HWKEY: 376 to 383 (never reloadable or readable)
257 */
258 #define STM32MP2_OTP_MAX_ID U(0x16F)
259 #define STM32MP2_MID_OTP_START U(0x80)
260 #define STM32MP2_UPPER_OTP_START U(0x100)
261
262 /* OTP labels */
263 #define PART_NUMBER_OTP "part-number-otp"
264 #define REVISION_OTP "rev_otp"
265 #define PACKAGE_OTP "package-otp"
266 #define HCONF1_OTP "otp124"
267 #define NAND_OTP "otp16"
268 #define NAND2_OTP "otp20"
269 #define BOARD_ID_OTP "board-id"
270 #define UID_OTP "uid-otp"
271 #define LIFECYCLE2_OTP "otp18"
272 #define PKH_OTP "otp144"
273 #define ENCKEY_OTP "otp260"
274
275 /* OTP mask */
276 /* PACKAGE */
277 #define PACKAGE_OTP_PKG_MASK GENMASK_32(2, 0)
278 #define PACKAGE_OTP_PKG_SHIFT U(0)
279
280 /* IWDG OTP */
281 #define HCONF1_OTP_IWDG_HW_POS U(0)
282 #define HCONF1_OTP_IWDG_FZ_STOP_POS U(1)
283 #define HCONF1_OTP_IWDG_FZ_STANDBY_POS U(2)
284
285 /* NAND OTP */
286 /* NAND parameter storage flag */
287 #define NAND_PARAM_STORED_IN_OTP BIT_32(31)
288
289 /* NAND page size in bytes */
290 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
291 #define NAND_PAGE_SIZE_SHIFT U(29)
292 #define NAND_PAGE_SIZE_2K U(0)
293 #define NAND_PAGE_SIZE_4K U(1)
294 #define NAND_PAGE_SIZE_8K U(2)
295
296 /* NAND block size in pages */
297 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
298 #define NAND_BLOCK_SIZE_SHIFT U(27)
299 #define NAND_BLOCK_SIZE_64_PAGES U(0)
300 #define NAND_BLOCK_SIZE_128_PAGES U(1)
301 #define NAND_BLOCK_SIZE_256_PAGES U(2)
302
303 /* NAND number of block (in unit of 256 blocks) */
304 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
305 #define NAND_BLOCK_NB_SHIFT U(19)
306 #define NAND_BLOCK_NB_UNIT U(256)
307
308 /* NAND bus width in bits */
309 #define NAND_WIDTH_MASK BIT_32(18)
310 #define NAND_WIDTH_SHIFT U(18)
311
312 /* NAND number of ECC bits per 512 bytes */
313 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
314 #define NAND_ECC_BIT_NB_SHIFT U(15)
315 #define NAND_ECC_BIT_NB_UNSET U(0)
316 #define NAND_ECC_BIT_NB_1_BITS U(1)
317 #define NAND_ECC_BIT_NB_4_BITS U(2)
318 #define NAND_ECC_BIT_NB_8_BITS U(3)
319 #define NAND_ECC_ON_DIE U(4)
320
321 /* NAND number of planes */
322 #define NAND_PLANE_BIT_NB_MASK BIT_32(14)
323
324 /* NAND2 OTP */
325 #define NAND2_PAGE_SIZE_SHIFT U(16)
326
327 /* NAND2 config distribution */
328 #define NAND2_CONFIG_DISTRIB BIT_32(0)
329 #define NAND2_PNAND_NAND2_SNAND_NAND1 U(0)
330 #define NAND2_PNAND_NAND1_SNAND_NAND2 U(1)
331
332 /* MONOTONIC OTP */
333 #define MAX_MONOTONIC_VALUE U(32)
334
335 /* UID OTP */
336 #define UID_WORD_NB U(3)
337
338 /* Lifecycle OTP */
339 #define SECURE_BOOT_CLOSED_SECURE GENMASK_32(3, 0)
340
341 /*******************************************************************************
342 * STM32MP2 TAMP
343 ******************************************************************************/
344 #define PLAT_MAX_TAMP_INT U(5)
345 #define PLAT_MAX_TAMP_EXT U(3)
346 #define TAMP_BASE U(0x46010000)
347 #define TAMP_SMCR (TAMP_BASE + U(0x20))
348 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
349 #define TAMP_BKP_REG_CLK CK_BUS_RTC
350 #define TAMP_BKP_SEC_NUMBER U(10)
351 #define TAMP_COUNTR U(0x40)
352
353 #if !(defined(__LINKER__) || defined(__ASSEMBLER__))
tamp_bkpr(uint32_t idx)354 static inline uintptr_t tamp_bkpr(uint32_t idx)
355 {
356 return TAMP_BKP_REGISTER_BASE + (idx << 2);
357 }
358 #endif
359
360 /*******************************************************************************
361 * STM32MP2 DDRCTRL
362 ******************************************************************************/
363 #define DDRCTRL_BASE U(0x48040000)
364
365 /*******************************************************************************
366 * STM32MP2 DDRDBG
367 ******************************************************************************/
368 #define DDRDBG_BASE U(0x48050000)
369
370 /*******************************************************************************
371 * STM32MP2 DDRPHYC
372 ******************************************************************************/
373 #define DDRPHYC_BASE U(0x48C00000)
374
375 /*******************************************************************************
376 * Miscellaneous STM32MP1 peripherals base address
377 ******************************************************************************/
378 #define BSEC_BASE U(0x44000000)
379 #define DBGMCU_BASE U(0x4A010000)
380 #define HASH_BASE U(0x42010000)
381 #define RTC_BASE U(0x46000000)
382 #define STGEN_BASE U(0x48080000)
383 #define SYSCFG_BASE U(0x44230000)
384
385 /*******************************************************************************
386 * STM32MP RIF
387 ******************************************************************************/
388 #define RISAB3_BASE U(0x42110000)
389 #define RISAB5_BASE U(0x42130000)
390
391 /*******************************************************************************
392 * STM32MP CA35SSC
393 ******************************************************************************/
394 #define A35SSC_BASE U(0x48800000)
395
396 /*******************************************************************************
397 * REGULATORS
398 ******************************************************************************/
399 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
400 #define PLAT_NB_RDEVS U(19)
401 /* 2 FIXED */
402 #define PLAT_NB_FIXED_REGUS U(2)
403 /* No GPIO regu */
404 #define PLAT_NB_GPIO_REGUS U(0)
405
406 /*******************************************************************************
407 * Device Tree defines
408 ******************************************************************************/
409 #define DT_BSEC_COMPAT "st,stm32mp25-bsec"
410 #define DT_DDR_COMPAT "st,stm32mp2-ddr"
411 #define DT_PWR_COMPAT "st,stm32mp25-pwr"
412 #define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc"
413 #define DT_SDMMC2_COMPAT "st,stm32mp25-sdmmc2"
414 #define DT_UART_COMPAT "st,stm32h7-uart"
415
416 #endif /* STM32MP2_DEF_H */
417