| /external/oboe/samples/RhythmGame/third_party/glm/simd/ |
| D | integer.h | 17 glm_uvec4 Reg2; in glm_i128_interleave() local
71 glm_uvec4 Reg2; in glm_i128_interleave2() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 770 unsigned Reg2) { in EmitInstrRegReg()
790 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg()
801 unsigned Reg2, unsigned FPReg1, in EmitMovFPIntPair()
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| D | AArch64LowerHomogeneousPrologEpilog.cpp | 200 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitStore()
223 const TargetInstrInfo &TII, unsigned Reg1, unsigned Reg2, in emitLoad()
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| D | AArch64FrameLowering.cpp | 2447 static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateWindowsRegisterPairing()
2478 static bool invalidateRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateRegisterPairing()
2498 unsigned Reg2 = AArch64::NoRegister; member
2748 unsigned Reg2 = RPI.Reg2; in spillCalleeSavedRegisters() local
2854 unsigned Reg2 = RPI.Reg2; in restoreCalleeSavedRegisters() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MicroMipsSizeReduction.cpp | 378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr() local
479 Register Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP() local
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| D | MipsAsmPrinter.cpp | 876 unsigned Reg2) { in EmitInstrRegReg()
896 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg()
907 unsigned Reg2, unsigned FPReg1, in EmitMovFPIntPair()
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/ |
| D | MicroMipsSizeReduction.cpp | 378 static bool ConsecutiveRegisters(unsigned Reg1, unsigned Reg2) { in ConsecutiveRegisters()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr() local
479 Register Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP() local
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| D | MipsAsmPrinter.cpp | 875 unsigned Reg2) { in EmitInstrRegReg()
895 unsigned Reg2, unsigned Reg3) { in EmitInstrRegRegReg()
906 unsigned Reg2, unsigned FPReg1, in EmitMovFPIntPair()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 876 unsigned Reg2; member
975 unsigned Reg2 = RPI.Reg2; in spillCalleeSavedRegisters() local
1038 unsigned Reg2 = RPI.Reg2; in restoreCalleeSavedRegisters() local
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 145 unsigned Reg2, bool isKill2) { in addRegReg()
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 190 Register Reg2 = MI.getOperand(2).getReg(); in processBlock() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 190 Register Reg2 = MI.getOperand(2).getReg(); in processBlock() local
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXFMAMutate.cpp | 189 unsigned Reg2 = MI->getOperand(2).getReg(); in processBlock() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 166 unsigned Reg2, bool isKill2) { in addRegReg()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86InstrBuilder.h | 166 unsigned Reg2, bool isKill2) { in addRegReg()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 1867 static bool invalidateWindowsRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateWindowsRegisterPairing()
1890 static bool invalidateRegisterPairing(unsigned Reg1, unsigned Reg2, in invalidateRegisterPairing()
1907 unsigned Reg2 = AArch64::NoRegister; member
2132 unsigned Reg2 = RPI.Reg2; in spillCalleeSavedRegisters() local
2240 unsigned Reg2 = RPI.Reg2; in restoreCalleeSavedRegisters() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | GCNRegBankReassign.cpp | 403 unsigned Reg2, in getOperandGatherWeight()
541 unsigned Reg2 = OperandMasks[J].Reg; in collectCandidates() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/CSKY/MCTargetDesc/ |
| D | CSKYMCCodeEmitter.cpp | 280 unsigned Reg2 = in getRegisterSeqOpValue() local
|
| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 710 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
745 unsigned Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1386 StringRef Reg2(R2); in processInstruction() local
1401 StringRef Reg2(R2); in processInstruction() local
1417 StringRef Reg2(R2); in processInstruction() local
1749 StringRef Reg2(R2); in processInstruction() local
1893 StringRef Reg2(R2); in processInstruction() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 758 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
793 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 750 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
785 Register Reg2 = MI->getOperand(2).getReg(); in ReduceTo2Addr() local
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| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| D | HexagonAsmParser.cpp | 1607 StringRef Reg2(R2); in processInstruction() local
1622 StringRef Reg2(R2); in processInstruction() local
1638 StringRef Reg2(R2); in processInstruction() local
1978 StringRef Reg2(R2); in processInstruction() local
2132 StringRef Reg2(R2); in processInstruction() local
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AsmBackend.cpp | 454 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true); in generateCompactUnwindEncoding() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/AsmParser/ |
| D | SystemZAsmParser.cpp | 836 bool &HaveReg2, Register &Reg2, in parseAddress()
900 Register Reg1, Reg2; in parseAddress() local
1214 Register Reg1, Reg2; in parseOperand() local
|