| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 434 bool isSubRegister(unsigned RegA, unsigned RegB) const { in isSubRegister()
442 bool isSubRegisterEq(unsigned RegA, unsigned RegB) const { in isSubRegisterEq()
448 bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const { in isSuperRegisterEq()
454 bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const { in isSuperOrSubRegisterEq()
527 inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{ in isSuperRegister()
|
| /external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 560 bool isSubRegister(MCRegister RegA, MCRegister RegB) const { in isSubRegister()
568 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSubRegisterEq()
574 bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperRegisterEq()
580 bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperOrSubRegisterEq()
659 inline bool MCRegisterInfo::isSuperRegister(MCRegister RegA, MCRegister RegB) const{ in isSuperRegister()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 553 bool isSubRegister(MCRegister RegA, MCRegister RegB) const { in isSubRegister()
561 bool isSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSubRegisterEq()
567 bool isSuperRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperRegisterEq()
573 bool isSuperOrSubRegisterEq(MCRegister RegA, MCRegister RegB) const { in isSuperOrSubRegisterEq()
649 inline bool MCRegisterInfo::isSuperRegister(MCRegister RegA, MCRegister RegB) const{ in isSuperRegister()
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 436 static bool regsAreCompatible(Register RegA, Register RegB, in regsAreCompatible()
527 Register RegB, in isProfitableToCommute()
663 Register RegB) { in isProfitableToConv3Addr()
681 Register RegA, Register RegB, unsigned &Dist) { in convertInstTo3Addr()
1461 Register RegB = 0; in processTiedPairs() local
1643 Register RegB = TO.first; in processStatepoint() local
|
| D | ImplicitNullChecks.cpp | 291 Register RegB = MOB.getReg(); in canReorder() local
|
| D | TargetInstrInfo.cpp | 959 Register RegB = OpB.getReg(); in reassociateOps() local
|
| /external/llvm/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 534 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { in regsAreCompatible()
674 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){ in isProfitableToConv3Addr()
693 unsigned RegA, unsigned RegB, in convertInstTo3Addr()
1456 unsigned RegB = 0; in processTiedPairs() local
|
| D | TargetInstrInfo.cpp | 702 unsigned RegB = OpB.getReg(); in reassociateOps() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TwoAddressInstructionPass.cpp | 561 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { in regsAreCompatible()
712 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){ in isProfitableToConv3Addr()
731 unsigned RegA, unsigned RegB, in convertInstTo3Addr()
1515 unsigned RegB = 0; in processTiedPairs() local
|
| D | ImplicitNullChecks.cpp | 287 Register RegB = MOB.getReg(); in canReorder() local
|
| D | TargetInstrInfo.cpp | 810 Register RegB = OpB.getReg(); in reassociateOps() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.cpp | 627 auto IsSubReg = [&](MCRegister RegA, MCRegister RegB) { in isArgumentRegister()
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/SPIRV/ |
| D | SPIRVModuleAnalysis.cpp | 269 Register RegB = B->getOperand(i).getReg(); in findSameInstrInMS() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 421 bool regsOverlap(Register RegA, Register RegB) const { in regsOverlap()
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 521 Register RegB = Root.getOperand(AddOpIdx).getReg(); in getFMAPatterns() local
867 RegA21, RegB; in reassociateFMA() local
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1981 for (auto &RegB : UsesB) { in isDependent() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 2103 for (auto &RegB : UsesB) { in isDependent() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 2217 for (auto &RegB : UsesB) { in isDependent() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 5830 Register RegB = AddMI->getOperand(IdxOpd1).getReg(); in genSubAdd2SubSub() local
|