| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| D | R600ISelDAGToDAG.cpp | 104 unsigned RegClassID; in Select() local
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| D | AMDGPUISelDAGToDAG.cpp | 441 void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) { in SelectBuildVector()
568 unsigned RegClassID = in Select() local
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| /external/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 184 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64A57FPLoadBalancing.cpp | 506 unsigned RegClassID = G->getStart()->getDesc().OpInfo[0].RegClass; in scavengeRegister() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64A57FPLoadBalancing.cpp | 518 unsigned RegClassID = ChainBegin->getDesc().OpInfo[0].RegClass; in scavengeRegister() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| D | AArch64A57FPLoadBalancing.cpp | 518 unsigned RegClassID = ChainBegin->getDesc().operands()[0].RegClass; in scavengeRegister() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 77 static bool isMemOperand(const MCInst &MI, unsigned Op, unsigned RegClassID) { in isMemOperand()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 1294 unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, in GetSIDIForRegClass()
1330 int RegClassID = -1; in VerifyAndAdjustOperands() local
3807 bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID, in parseSEHRegisterNumber()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 681 void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) { in SelectBuildVector()
804 unsigned RegClassID = selectSGPRVectorRegClassID(NumVectorElts); in Select() local
2791 unsigned RegClassID; in Select() local
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 1026 unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, in GetSIDIForRegClass()
1062 int RegClassID = -1; in VerifyAndAdjustOperands() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 1629 unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, in GetSIDIForRegClass()
1665 int RegClassID = -1; in VerifyAndAdjustOperands() local
4845 bool X86AsmParser::parseSEHRegisterNumber(unsigned RegClassID, in parseSEHRegisterNumber()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 614 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand()
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| /external/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1559 unsigned RegClassID, in DecodeGPRSeqPairsClassRegisterClass()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 289 unsigned RegClassID; in Select() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1776 unsigned RegClassID, in DecodeGPRSeqPairsClassRegisterClass()
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 1105 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand()
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/Disassembler/ |
| D | AArch64Disassembler.cpp | 1895 DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID, in DecodeGPRSeqPairsClassRegisterClass()
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelDAGToDAG.cpp | 224 unsigned RegClassID; in createTuple() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/AsmParser/ |
| D | RISCVAsmParser.cpp | 1009 unsigned RegClassID; in convertVRToVRMx() local
|