Home
last modified time | relevance | path

Searched defs:RegClassInfo (Results 1 – 25 of 45) sorted by relevance

12

/external/llvm/lib/CodeGen/
DAllocationOrder.cpp32 const RegisterClassInfo &RegClassInfo, in AllocationOrder()
DCriticalAntiDepBreaker.h37 const RegisterClassInfo &RegClassInfo; variable
DRegAllocBase.h66 RegisterClassInfo RegClassInfo; variable
DAggressiveAntiDepBreaker.h117 const RegisterClassInfo &RegClassInfo; variable
DPostRASchedulerList.cpp82 RegisterClassInfo RegClassInfo; member in __anon5995e8400111::PostRAScheduler
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DAllocationOrder.cpp31 const RegisterClassInfo &RegClassInfo, in AllocationOrder()
DRegAllocBase.h69 RegisterClassInfo RegClassInfo; variable
DCriticalAntiDepBreaker.h41 const RegisterClassInfo &RegClassInfo; variable
DAggressiveAntiDepBreaker.h122 const RegisterClassInfo &RegClassInfo; variable
DBreakFalseDeps.cpp38 RegisterClassInfo RegClassInfo; member in llvm::BreakFalseDeps
DPostRASchedulerList.cpp82 RegisterClassInfo RegClassInfo; member in __anon78e259a20111::PostRAScheduler
/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/
DAllocationOrder.cpp30 const RegisterClassInfo &RegClassInfo, in create()
DCriticalAntiDepBreaker.h41 const RegisterClassInfo &RegClassInfo; variable
DRegAllocBase.h70 RegisterClassInfo RegClassInfo; variable
DAggressiveAntiDepBreaker.h122 const RegisterClassInfo &RegClassInfo; variable
DRegAllocPriorityAdvisor.h43 const RegisterClassInfo &RegClassInfo; variable
DRegAllocEvictionAdvisor.h144 const RegisterClassInfo &RegClassInfo; variable
DBreakFalseDeps.cpp40 RegisterClassInfo RegClassInfo; member in llvm::BreakFalseDeps
DPostRASchedulerList.cpp78 RegisterClassInfo RegClassInfo; member in __anon989621e80111::PostRAScheduler
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h232 struct RegClassInfo { struct
244 const RegClassInfo *const RCInfos; argument
DMachinePipeliner.h67 RegisterClassInfo RegClassInfo; variable
122 const RegisterClassInfo &RegClassInfo; variable
/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/CodeGen/
DTargetRegisterInfo.h240 struct RegClassInfo { struct
252 const RegClassInfo *const RCInfos; argument
DMachinePipeliner.h74 RegisterClassInfo RegClassInfo; variable
124 const RegisterClassInfo &RegClassInfo; variable
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIPreAllocateWWMRegs.cpp44 RegisterClassInfo RegClassInfo; member in __anon256cdc210111::SIPreAllocateWWMRegs
/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/
DSIPreAllocateWWMRegs.cpp41 RegisterClassInfo RegClassInfo; member in __anon460fd9a70111::SIPreAllocateWWMRegs

12