| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| D | AArch64MIPeepholeOpt.cpp | 123 static bool splitBitmaskImm(T Imm, unsigned RegSize, T &Imm1Enc, T &Imm2Enc) { in splitBitmaskImm()
176 T &Imm1) -> std::optional<OpcodePair> { in visitAND()
302 static bool splitAddSubImm(T Imm, unsigned RegSize, T &Imm0, T &Imm1) { in splitAddSubImm()
340 T &Imm1) -> std::optional<OpcodePair> { in visitADDSUB()
372 T &Imm1) -> std::optional<OpcodePair> { in visitADDSSUBS()
448 unsigned RegSize = sizeof(T) * 8; in splitTwoPartImm() local
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| D | AArch64FastISel.cpp | 1676 unsigned RegSize; in emitLogicalOp_ri() local
4066 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSL_ri() local
4169 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSR_ri() local
4285 unsigned RegSize = Is64Bit ? 64 : 32; in emitASR_ri() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/ |
| D | MipsFrameLowering.cpp | 127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize() local
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| D | MipsSEFrameLowering.cpp | 198 unsigned RegSize) { in expandLoadACC()
223 unsigned RegSize) { in expandStoreACC()
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| D | MipsCallLowering.cpp | 413 unsigned RegSize = 4; in lowerFormalArguments() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsFrameLowering.cpp | 127 unsigned RegSize = TRI.getSpillSize(*TRI.getMinimalPhysRegClass(*R)); in estimateStackSize() local
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| D | MipsSEFrameLowering.cpp | 198 unsigned RegSize) { in expandLoadACC()
223 unsigned RegSize) { in expandStoreACC()
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| D | MipsCallLowering.cpp | 505 unsigned RegSize = 4; in lowerFormalArguments() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 138 unsigned RegSize = TRI.getRegSizeInBits(*RC); in addMachineReg() local
291 unsigned RegSize = 0; in addMachineRegExpression() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| D | X86TileConfig.cpp | 179 unsigned RegSize = TRI->getRegSizeInBits(*MRI.getRegClass(R)); in INITIALIZE_PASS_DEPENDENCY() local
|
| /external/capstone/ |
| D | MCRegisterInfo.h | 36 uint16_t RegSize, Alignment; // Size & Alignment of register in bytes member
|
| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 222 unsigned RegSize = 0; in getInstrMappingImpl() local
372 unsigned RegSize = MRI.getSize(Reg); in getSizeInBits() local
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 133 unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8; in AddMachineRegPiece() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/AsmPrinter/ |
| D | DwarfExpression.cpp | 137 unsigned RegSize = TRI.getRegSizeInBits(*RC); in addMachineReg() local
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEFrameLowering.cpp | 179 unsigned RegSize) { in expandLoadACC()
204 unsigned RegSize) { in expandStoreACC()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 482 unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0; in getRegSizeInBits() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/CSKY/ |
| D | CSKYFrameLowering.cpp | 429 auto RegSize = TRI->getRegSizeInBits(Reg, MRI) / 8; in determineCalleeSaves() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/SystemZ/ |
| D | SystemZFrameLowering.cpp | 1024 unsigned RegSize = 8; in assignCalleeSavedSpillSlots() local
1404 const unsigned RegSize = MF.getDataLayout().getPointerSize(); in determineFrameLayout() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 512 unsigned RegSize = Ty.isValid() ? Ty.getSizeInBits() : 0; in getRegSizeInBits() local
|
| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 41 const uint16_t RegSize, Alignment; // Size & Alignment of register in bytes variable
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 1616 unsigned RegSize; in emitLogicalOp_ri() local
3946 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSL_ri() local
4053 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSR_ri() local
4174 unsigned RegSize = Is64Bit ? 64 : 32; in emitASR_ri() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 1703 unsigned RegSize; in emitLogicalOp_ri() local
4124 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSL_ri() local
4231 unsigned RegSize = Is64Bit ? 64 : 32; in emitLSR_ri() local
4352 unsigned RegSize = Is64Bit ? 64 : 32; in emitASR_ri() local
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 213 static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize, in processLogicalImmediate()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 233 unsigned RegSize, SpillSize, SpillAlignment; member
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 214 static inline bool processLogicalImmediate(uint64_t Imm, unsigned RegSize, in processLogicalImmediate()
|