• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /*
2  * Copyright (c) 2024, Rockchip, Inc. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef __CLOCK_H__
8 #define __CLOCK_H__
9 
10 /* scmi-clocks indices */
11 
12 #define SCMI_CLK_CPUL			0
13 #define SCMI_CLK_DSU			1
14 #define SCMI_CLK_CPUB01			2
15 #define SCMI_CLK_CPUB23			3
16 #define SCMI_CLK_DDR			4
17 #define SCMI_CLK_GPU			5
18 #define SCMI_CLK_NPU			6
19 #define SCMI_CLK_SBUS			7
20 #define SCMI_PCLK_SBUS			8
21 #define SCMI_CCLK_SD			9
22 #define SCMI_DCLK_SD			10
23 #define SCMI_ACLK_SECURE_NS		11
24 #define SCMI_HCLK_SECURE_NS		12
25 #define SCMI_TCLK_WDT			13
26 #define SCMI_KEYLADDER_CORE		14
27 #define SCMI_KEYLADDER_RNG		15
28 #define SCMI_ACLK_SECURE_S		16
29 #define SCMI_HCLK_SECURE_S		17
30 #define SCMI_PCLK_SECURE_S		18
31 #define SCMI_CRYPTO_RNG			19
32 #define SCMI_CRYPTO_CORE		20
33 #define SCMI_CRYPTO_PKA			21
34 #define SCMI_SPLL			22
35 #define SCMI_HCLK_SD			23
36 #define SCMI_CRYPTO_RNG_S		24
37 #define SCMI_CRYPTO_CORE_S		25
38 #define SCMI_CRYPTO_PKA_S		26
39 #define SCMI_A_CRYPTO_S			27
40 #define SCMI_H_CRYPTO_S			28
41 #define SCMI_P_CRYPTO_S			29
42 #define SCMI_A_KEYLADDER_S		30
43 #define SCMI_H_KEYLADDER_S		31
44 #define SCMI_P_KEYLADDER_S		32
45 #define SCMI_TRNG_S			33
46 #define SCMI_H_TRNG_S			34
47 #define SCMI_P_OTPC_S			35
48 #define SCMI_OTPC_S			36
49 #define SCMI_OTP_PHY			37
50 #define SCMI_OTPC_AUTO_RD		38
51 #define SCMI_OTPC_ARB			39
52 
53 /******** DSUCRU **************************************/
54 #define DSUCRU_CLKSEL_CON(n)		(0x0300 + (n) * 4)
55 
56 /********Name=DSUCRU_CLKSEL_CON04,Offset=0x310********/
57 #define PCLK_DSU_ROOT_SEL_SHIFT		5
58 #define PCLK_DSU_ROOT_SEL_MASK		0x3
59 #define PCLK_DSU_ROOT_SEL_GPLL		0x3
60 
61 /********Name=SECURE_SOFTRST_CON00,Offset=0xA00********/
62 #define SRST_A_SECURE_NS_BIU		10
63 #define SRST_H_SECURE_NS_BIU		11
64 #define SRST_A_SECURE_S_BIU		12
65 #define SRST_H_SECURE_S_BIU		13
66 #define SRST_P_SECURE_S_BIU		14
67 #define SRST_CRYPTO_CORE		15
68 /********Name=SECURE_SOFTRST_CON01,Offset=0xA04********/
69 #define SRST_CRYPTO_PKA			16
70 #define SRST_CRYPTO_RNG			17
71 #define SRST_A_CRYPTO			18
72 #define SRST_H_CRYPTO			19
73 #define SRST_KEYLADDER_CORE		25
74 #define SRST_KEYLADDER_RNG		26
75 #define SRST_A_KEYLADDER		27
76 #define SRST_H_KEYLADDER		28
77 #define SRST_P_OTPC_S			29
78 #define SRST_OTPC_S			30
79 #define SRST_WDT_S			31
80 /********Name=SECURE_SOFTRST_CON02,Offset=0xA08********/
81 #define SRST_T_WDT_S			32
82 #define SRST_H_BOOTROM			33
83 #define SRST_A_DCF			34
84 #define SRST_P_DCF			35
85 #define SRST_H_BOOTROM_NS		37
86 #define SRST_P_KEYLADDER		46
87 #define SRST_H_TRNG_S			47
88 /********Name=SECURE_SOFTRST_CON03,Offset=0xA0C********/
89 #define SRST_H_TRNG_NS			48
90 #define SRST_D_SDMMC_BUFFER		49
91 #define SRST_H_SDMMC			50
92 #define SRST_H_SDMMC_BUFFER		51
93 #define SRST_SDMMC			52
94 #define SRST_P_TRNG_CHK			53
95 #define SRST_TRNG_S			54
96 
97 #define SRST_INVALID			55
98 
99 void pvtplls_suspend(void);
100 void pvtplls_resume(void);
101 
102 void rockchip_clock_init(void);
103 
104 #endif
105