1 /* 2 * Copyright (c) 2022-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef EMI_MPU_PRIV_H 8 #define EMI_MPU_PRIV_H 9 10 #define ENABLE_EMI_MPU_SW_LOCK (0) 11 12 #define EMI_MPU_CTRL (EMI_MPU_BASE + 0x000) 13 #define EMI_MPU_DBG (EMI_MPU_BASE + 0x004) 14 #define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100) 15 #define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200) 16 #define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region * 4)) 17 #define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region * 4)) 18 #define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300) 19 #define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region * 4) + (dgroup * 0x100)) 20 #define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800) 21 #define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain * 4)) 22 #define EMI_RG_MASK_D0 (EMI_MPU_BASE + 0x900) 23 #define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain * 4)) 24 25 #define SUB_EMI_MPU_CTRL (SUB_EMI_MPU_BASE + 0x000) 26 #define SUB_EMI_MPU_DBG (SUB_EMI_MPU_BASE + 0x004) 27 #define SUB_EMI_MPU_SA0 (SUB_EMI_MPU_BASE + 0x100) 28 #define SUB_EMI_MPU_EA0 (SUB_EMI_MPU_BASE + 0x200) 29 #define SUB_EMI_MPU_SA(region) (SUB_EMI_MPU_SA0 + (region * 4)) 30 #define SUB_EMI_MPU_EA(region) (SUB_EMI_MPU_EA0 + (region * 4)) 31 #define SUB_EMI_MPU_APC0 (SUB_EMI_MPU_BASE + 0x300) 32 #define SUB_EMI_MPU_APC(region, dgroup) (SUB_EMI_MPU_APC0 + (region * 4) + (dgroup * 0x100)) 33 #define SUB_EMI_MPU_CTRL_D0 (SUB_EMI_MPU_BASE + 0x800) 34 #define SUB_EMI_MPU_CTRL_D(domain) (SUB_EMI_MPU_CTRL_D0 + (domain * 4)) 35 #define SUB_EMI_RG_MASK_D0 (SUB_EMI_MPU_BASE + 0x900) 36 #define SUB_EMI_RG_MASK_D(domain) (SUB_EMI_RG_MASK_D0 + (domain * 4)) 37 38 #define EMI_MPU_DOMAIN_NUM (16) 39 #define EMI_MPU_REGION_NUM (32) 40 #define EMI_MPU_ALIGN_BITS (16) 41 #define DRAM_START_ADDR (0x40000000ULL) 42 #define DRAM_OFFSET (DRAM_START_ADDR >> EMI_MPU_ALIGN_BITS) 43 #define DRAM_MAX_SIZE (0x200000000ULL) 44 #define BL32_REGION_BASE (0x43000000ULL) 45 #define BL32_REGION_SIZE (0x4600000ULL) 46 #define SCP_CORE0_REGION_BASE (0x50000000ULL) 47 #define SCP_CORE0_REGION_SIZE (0x800000ULL) 48 #define SCP_CORE1_REGION_BASE (0x70000000ULL) 49 #define SCP_CORE1_REGION_SIZE (0xa000000ULL) 50 #define DSP_PROTECT_REGION_BASE (0x60000000ULL) 51 #define DSP_PROTECT_REGION_SIZE (0x1100000ULL) 52 53 #define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8) 54 55 /* APU EMI MPU Setting */ 56 #define APUSYS_SEC_BUF_PA (0x55000000) 57 #define APUSYS_SEC_BUF_SZ (0x100000) 58 59 #define SVP_DRAM_REGION_COUNT (10) 60 61 enum region_ids { 62 BL31_EMI_REGION_ID = 0, 63 BL32_REGION_ID, 64 SCP_CORE0_REGION_ID, 65 SCP_CORE1_REGION_ID, 66 DSP_PROTECT_REGION_ID, 67 SVP_DRAM_REGION_ID_START = 5, 68 SVP_DRAM_REGION_ID_END = SVP_DRAM_REGION_ID_START + SVP_DRAM_REGION_COUNT - 1, 69 70 APUSYS_SEC_BUF_EMI_REGION_ID = 21, 71 72 ALL_DEFAULT_REGION_ID = 31, 73 }; 74 #endif 75