1 /* 2 * Copyright (c) 2023, Aspeed Technology Inc. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_REG_H 8 #define PLATFORM_REG_H 9 10 /* GIC */ 11 #define GICD_BASE U(0x12200000) 12 #define GICD_SIZE U(0x10000) 13 #define GICR_BASE U(0x12280000) 14 #define GICR_SIZE U(0x100000) 15 16 /* UART */ 17 #define UART_BASE U(0x14c33000) 18 #define UART12_BASE (UART_BASE + 0xb00) 19 20 /* CPU-die SCU */ 21 #define SCU_CPU_BASE U(0x12c02000) 22 #define SCU_CPU_HW_STRAP1 (SCU_CPU_BASE + 0x010) 23 #define SCU_CPU_HPLL (SCU_CPU_BASE + 0x300) 24 #define SCU_CPU_DPLL (SCU_CPU_BASE + 0x308) 25 #define SCU_CPU_MPLL (SCU_CPU_BASE + 0x310) 26 #define SCU_CPU_SMP_EP0 (SCU_CPU_BASE + 0x780) 27 #define SCU_CPU_SMP_EP1 (SCU_CPU_BASE + 0x788) 28 #define SCU_CPU_SMP_EP2 (SCU_CPU_BASE + 0x790) 29 #define SCU_CPU_SMP_EP3 (SCU_CPU_BASE + 0x798) 30 31 #endif /* PLATFORM_REG_H */ 32