1# SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_AMD_PICASSO 4 bool 5 select ACPI_SOC_NVS 6 select ADD_FSP_BINARIES if USE_AMD_BLOBS 7 select ARCH_X86 8 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH 9 select CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS if VBOOT_STARTS_BEFORE_BOOTBLOCK 10 select DRIVERS_USB_PCI_XHCI 11 select FSP_COMPRESS_FSP_M_LZMA 12 select FSP_COMPRESS_FSP_S_LZMA 13 select GENERIC_GPIO_LIB 14 select HAVE_ACPI_TABLES 15 select HAVE_CF9_RESET 16 select HAVE_EM100_SUPPORT 17 select HAVE_SMI_HANDLER 18 select IDT_IN_EVERY_STAGE 19 select PARALLEL_MP_AP_WORK 20 select PLATFORM_USES_FSP2_0 21 select PROVIDES_ROM_SHARING 22 select RESET_VECTOR_IN_RAM 23 select RTC 24 select SOC_AMD_COMMON 25 select SOC_AMD_COMMON_BLOCK_ACP_GEN1 26 select SOC_AMD_COMMON_BLOCK_ACPI 27 select SOC_AMD_COMMON_BLOCK_ACPIMMIO 28 select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS 29 select SOC_AMD_COMMON_BLOCK_ACPI_ALIB 30 select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE 31 select SOC_AMD_COMMON_BLOCK_ACPI_GPIO 32 select SOC_AMD_COMMON_BLOCK_ACPI_IVRS 33 select SOC_AMD_COMMON_BLOCK_ACPI_MADT 34 select SOC_AMD_COMMON_BLOCK_AOAC 35 select SOC_AMD_COMMON_BLOCK_APOB 36 select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS 37 select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H 38 select SOC_AMD_COMMON_BLOCK_DATA_FABRIC 39 select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN 40 select SOC_AMD_COMMON_BLOCK_EMMC 41 select SOC_AMD_COMMON_BLOCK_EMMC_SKIP_POWEROFF 42 select SOC_AMD_COMMON_BLOCK_GPP_CLK 43 select SOC_AMD_COMMON_BLOCK_GRAPHICS 44 select SOC_AMD_COMMON_BLOCK_HAS_ESPI 45 select SOC_AMD_COMMON_BLOCK_HDA 46 select SOC_AMD_COMMON_BLOCK_I2C 47 select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL 48 select SOC_AMD_COMMON_BLOCK_IOMMU 49 select SOC_AMD_COMMON_BLOCK_LPC 50 select SOC_AMD_COMMON_BLOCK_MCAX 51 select SOC_AMD_COMMON_BLOCK_NONCAR 52 select SOC_AMD_COMMON_BLOCK_PCI 53 select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER 54 select SOC_AMD_COMMON_BLOCK_PM 55 select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE 56 select SOC_AMD_COMMON_BLOCK_PSP_GEN2 57 select SOC_AMD_COMMON_BLOCK_RESET 58 select SOC_AMD_COMMON_BLOCK_SATA 59 select SOC_AMD_COMMON_BLOCK_SMBUS 60 select SOC_AMD_COMMON_BLOCK_SMI 61 select SOC_AMD_COMMON_BLOCK_SMM 62 select SOC_AMD_COMMON_BLOCK_SMU 63 select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY 64 select SOC_AMD_COMMON_BLOCK_SPI 65 select SOC_AMD_COMMON_BLOCK_SVI2 66 select SOC_AMD_COMMON_BLOCK_TSC 67 select SOC_AMD_COMMON_BLOCK_UART 68 select SOC_AMD_COMMON_BLOCK_UCODE 69 select SOC_AMD_COMMON_FSP_DMI_TABLES 70 select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ 71 select SOC_AMD_SUPPORTS_WARM_RESET 72 select SSE2 73 select UDK_2017_BINDING 74 select USE_DDR4 75 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 76 select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 77 select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE 78 select X86_AMD_FIXED_MTRRS 79 select X86_INIT_NEED_1_SIPI 80 select HAVE_X86_64_SUPPORT 81 help 82 AMD Picasso support 83 84if SOC_AMD_PICASSO 85 86config CHIPSET_DEVICETREE 87 string 88 default "soc/amd/picasso/chipset.cb" 89 90config FSP_M_FILE 91 string "FSP-M (memory init) binary path and filename" 92 depends on ADD_FSP_BINARIES 93 default "3rdparty/amd_blobs/picasso/PICASSO_M.fd" 94 help 95 The path and filename of the FSP-M binary for this platform. 96 97config FSP_S_FILE 98 string "FSP-S (silicon init) binary path and filename" 99 depends on ADD_FSP_BINARIES 100 default "3rdparty/amd_blobs/picasso/PICASSO_S.fd" 101 help 102 The path and filename of the FSP-S binary for this platform. 103 104config EARLY_RESERVED_DRAM_BASE 105 hex 106 default 0x2000000 107 help 108 This variable defines the base address of the DRAM which is reserved 109 for usage by coreboot in early stages (i.e. before ramstage is up). 110 This memory gets reserved in BIOS tables to ensure that the OS does 111 not use it, thus preventing corruption of OS memory in case of S3 112 resume. 113 114config EARLYRAM_BSP_STACK_SIZE 115 hex 116 default 0x1000 117 118config PSP_APOB_DRAM_ADDRESS 119 hex 120 default 0x2001000 121 help 122 Location in DRAM where the PSP will copy the AGESA PSP Output 123 Block. 124 125config PSP_APOB_DRAM_SIZE 126 hex 127 default 0x10000 128 129config PSP_SHAREDMEM_BASE 130 hex 131 default 0x2011000 if VBOOT 132 default 0x0 133 help 134 This variable defines the base address in DRAM memory where PSP copies 135 the vboot workbuf. This is used in the linker script to have a static 136 allocation for the buffer as well as for adding relevant entries in 137 the BIOS directory table for the PSP. 138 139config PSP_SHAREDMEM_SIZE 140 hex 141 default 0x8000 if VBOOT 142 default 0x0 143 help 144 Sets the maximum size for the PSP to pass the vboot workbuf and 145 any logs or timestamps back to coreboot. This will be copied 146 into main memory by the PSP and will be available when the x86 is 147 started. The workbuf's base depends on the address of the reset 148 vector. 149 150config PRE_X86_CBMEM_CONSOLE_SIZE 151 hex 152 default 0x1600 153 help 154 Size of the CBMEM console used in PSP verstage. 155 156config PRERAM_CBMEM_CONSOLE_SIZE 157 hex 158 default 0x1600 159 help 160 Increase this value if preram cbmem console is getting truncated 161 162config CBFS_MCACHE_SIZE 163 hex 164 default 0x2000 if VBOOT_STARTS_BEFORE_BOOTBLOCK 165 166config C_ENV_BOOTBLOCK_SIZE 167 hex 168 default 0x20000 169 help 170 Sets the size of the bootblock stage that should be loaded in DRAM. 171 This variable controls the DRAM allocation size in linker script 172 for bootblock stage. 173 174config ROMSTAGE_ADDR 175 hex 176 default 0x2050000 177 help 178 Sets the address in DRAM where romstage should be loaded. 179 180config ROMSTAGE_SIZE 181 hex 182 default 0x70000 183 help 184 Sets the size of DRAM allocation for romstage in linker script. 185 186config FSP_M_ADDR 187 hex 188 default 0x20C0000 189 help 190 Sets the address in DRAM where FSP-M should be loaded. cbfstool 191 performs relocation of FSP-M to this address. 192 193config FSP_M_SIZE 194 hex 195 default 0xC0000 196 help 197 Sets the size of DRAM allocation for FSP-M in linker script. 198 199config VERSTAGE_ADDR 200 hex 201 depends on VBOOT_SEPARATE_VERSTAGE 202 default 0x2180000 203 help 204 Sets the address in DRAM where verstage should be loaded if running 205 as a separate stage on x86. 206 207config VERSTAGE_SIZE 208 hex 209 depends on VBOOT_SEPARATE_VERSTAGE 210 default 0x80000 211 help 212 Sets the size of DRAM allocation for verstage in linker script if 213 running as a separate stage on x86. 214 215config ECAM_MMCONF_BASE_ADDRESS 216 default 0xF8000000 217 218config ECAM_MMCONF_BUS_NUMBER 219 default 64 220 221config VERSTAGE_ADDR 222 hex 223 default 0x4000000 224 225config MAX_CPUS 226 int 227 default 8 228 help 229 Maximum number of threads the platform can have. 230 231config VGA_BIOS_ID 232 string 233 default "1002,15d8" 234 help 235 The default VGA BIOS PCI vendor/device ID should be set to the 236 result of the map_oprom_vendev() function in graphics.c. 237 238config VGA_BIOS_FILE 239 string 240 default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" 241 242config VGA_BIOS_SECOND 243 def_bool y 244 245config VGA_BIOS_SECOND_ID 246 string 247 default "1002,15dd" 248 help 249 Some Dali and all Pollock APUs need a different VBIOS than some other 250 Dali and all Picasso APUs, but don't always have a different PCI 251 vendor/device IDs, so we need an alternate method to determine the 252 correct video BIOS. In map_oprom_vendev(), we look at the return 253 value of soc_is_raven2() and decide which rom to load. 254 255config VGA_BIOS_SECOND_FILE 256 string 257 default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin" 258 259config S3_VGA_ROM_RUN 260 bool 261 default n 262 263config SERIRQ_CONTINUOUS_MODE 264 bool 265 default n 266 help 267 Set this option to y for serial IRQ in continuous mode. 268 Otherwise it is in quiet mode. 269 270config CONSOLE_UART_BASE_ADDRESS 271 depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART 272 hex 273 default 0xfedc9000 if UART_FOR_CONSOLE = 0 274 default 0xfedca000 if UART_FOR_CONSOLE = 1 275 default 0xfedce000 if UART_FOR_CONSOLE = 2 276 default 0xfedcf000 if UART_FOR_CONSOLE = 3 277 278config SMM_TSEG_SIZE 279 hex 280 default 0x800000 if HAVE_SMI_HANDLER 281 default 0x0 282 283config SMM_RESERVED_SIZE 284 hex 285 default 0x180000 286 287config SMM_MODULE_STACK_SIZE 288 hex 289 default 0x800 290 291config ACPI_BERT 292 bool "Build ACPI BERT Table" 293 default y 294 depends on HAVE_ACPI_TABLES 295 help 296 Report Machine Check errors identified in POST to the OS in an 297 ACPI Boot Error Record Table. 298 299config ACPI_BERT_SIZE 300 hex 301 default 0x4000 if ACPI_BERT 302 default 0x0 303 help 304 Specify the amount of DRAM reserved for gathering the data used to 305 generate the ACPI table. 306 307config CHROMEOS 308 select ALWAYS_LOAD_OPROM 309 select ALWAYS_RUN_OPROM 310 311config RO_REGION_ONLY 312 string 313 depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A 314 default "apu/amdfw" 315 316config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ 317 int 318 default 150 319 320config DISABLE_SPI_FLASH_ROM_SHARING 321 def_bool n 322 help 323 Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin 324 which indicates a board level ROM transaction request. This 325 removes arbitration with board and assumes the chipset controls 326 the SPI flash bus entirely. 327 328config DISABLE_KEYBOARD_RESET_PIN 329 bool 330 help 331 Instruct the SoC to not use the state of GPIO_129 as keyboard reset 332 signal. When this pin is used as GPIO and the keyboard reset 333 functionality isn't disabled, configuring it as an output and driving 334 it as 0 will cause a reset. 335 336config FSP_TEMP_RAM_SIZE 337 hex 338 default 0x40000 339 help 340 The amount of coreboot-allocated heap and stack usage by the FSP. 341 342menu "PSP Configuration Options" 343 344config AMDFW_CONFIG_FILE 345 string 346 default "src/soc/amd/picasso/fw.cfg" 347 348config PSP_LOAD_MP2_FW 349 bool 350 default n 351 help 352 Include the MP2 firmwares and configuration into the PSP build. 353 354 If unsure, answer 'n' 355 356config PSP_LOAD_S0I3_FW 357 bool 358 default n 359 help 360 Select this item to include the S0i3 file into the PSP build. 361 362config HAVE_PSP_WHITELIST_FILE 363 bool "Include a debug whitelist file in PSP build" 364 default n 365 help 366 Support secured unlock prior to reset using a whitelisted 367 number? This feature requires a signed whitelist image and 368 bootloader from AMD. 369 370 If unsure, answer 'n' 371 372config PSP_WHITELIST_FILE 373 string "Debug whitelist file path" 374 depends on HAVE_PSP_WHITELIST_FILE 375 default "3rdparty/amd_blobs/picasso/PSP/wtl-rvn.sbin" 376 377config PSP_UNLOCK_SECURE_DEBUG 378 bool "Unlock secure debug" 379 default n 380 help 381 Select this item to enable secure debug options in PSP. 382 383config PSP_VERSTAGE_FILE 384 string "Specify the PSP_verstage file path" 385 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK 386 default "\$(obj)/psp_verstage.bin" 387 help 388 Add psp_verstage file to the build & PSP Directory Table 389 390config PSP_VERSTAGE_SIGNING_TOKEN 391 string "Specify the PSP_verstage Signature Token file path" 392 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK 393 default "" 394 help 395 Add psp_verstage signature token to the build & PSP Directory Table 396 397config PSP_SOFTFUSE_BITS 398 string "PSP Soft Fuse bits to enable" 399 default "28" 400 help 401 Space separated list of Soft Fuse bits to enable. 402 Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) 403 Bit 15: PSP post code destination: 0=LPC 1=eSPI 404 Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW) 405 406 See #55758 (NDA) for additional bit definitions. 407 408endmenu 409 410config VBOOT 411 select VBOOT_VBNV_CMOS 412 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH 413 414config VBOOT_STARTS_BEFORE_BOOTBLOCK 415 def_bool n 416 depends on VBOOT 417 select ARCH_VERSTAGE_ARMV7 418 help 419 Runs verstage on the PSP. Only available on 420 certain ChromeOS branded parts from AMD. 421 422config VBOOT_HASH_BLOCK_SIZE 423 hex 424 default 0x9000 425 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK 426 help 427 Because the bulk of the time in psp_verstage to hash the RO cbfs is 428 spent in the overhead of doing svc calls, increasing the hash block 429 size significantly cuts the verstage hashing time as seen below. 430 431 4k takes 180ms 432 16k takes 44ms 433 32k takes 33.7ms 434 36k takes 32.5ms 435 There's actually still room for an even bigger stack, but we've 436 reached a point of diminishing returns. 437 438config CMOS_RECOVERY_BYTE 439 hex 440 default 0x51 441 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK 442 help 443 If the workbuf is not passed from the PSP to coreboot, set the 444 recovery flag and reboot. The PSP will read this byte, mark the 445 recovery request in VBNV, and reset the system into recovery mode. 446 447 This is the byte before the default first byte used by VBNV 448 (0x26 + 0x0E - 1) 449 450if VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK 451 452config RWA_REGION_ONLY 453 string 454 default "apu/amdfw_a" 455 help 456 Add a space-delimited list of filenames that should only be in the 457 RW-A section. 458 459endif # VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK 460 461if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK 462 463config RWB_REGION_ONLY 464 string 465 default "apu/amdfw_b" 466 help 467 Add a space-delimited list of filenames that should only be in the 468 RW-B section. 469 470endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK 471 472endif # SOC_AMD_PICASSO 473