1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_INTEL_COMMON_SKYLAKE_BASE 4 bool 5 select ACPI_INTEL_HARDWARE_SLEEP_VALUES 6 select ACPI_NHLT 7 select ARCH_X86 8 select BOOT_DEVICE_SUPPORTS_WRITES 9 select CACHE_MRC_SETTINGS 10 select CPU_INTEL_COMMON 11 select CPU_INTEL_FIRMWARE_INTERFACE_TABLE 12 select CPU_SUPPORTS_PM_TIMER_EMULATION 13 select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2 14 select FSP_COMPRESS_FSP_S_LZ4 15 select FSP_M_XIP 16 select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 17 select GENERIC_GPIO_LIB 18 select HAVE_FSP_GOP 19 select HAVE_FSP_LOGO_SUPPORT 20 select HAVE_HYPERTHREADING 21 select HAVE_INTEL_FSP_REPO 22 select INTEL_CAR_NEM_ENHANCED 23 select HAVE_SMI_HANDLER 24 select INTEL_DESCRIPTOR_MODE_CAPABLE 25 select INTEL_GMA_ACPI 26 select INTEL_GMA_ADD_VBT if RUN_FSP_GOP 27 select MRC_SETTINGS_PROTECT 28 select PARALLEL_MP_AP_WORK 29 select PLATFORM_USES_FSP2_0 30 select PMC_GLOBAL_RESET_ENABLE_LOCK 31 select SA_ENABLE_DPR 32 select SOC_INTEL_COMMON 33 select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE 34 select SOC_INTEL_COMMON_BLOCK 35 select SOC_INTEL_COMMON_BLOCK_ACPI 36 select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC 37 select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO 38 select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT 39 select SOC_INTEL_COMMON_BLOCK_ACPI_PEP 40 select SOC_INTEL_COMMON_BLOCK_CAR 41 select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG 42 select SOC_INTEL_COMMON_BLOCK_CPU 43 select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT 44 select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE 45 select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT 46 select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL 47 select SOC_INTEL_COMMON_BLOCK_GSPI 48 select SOC_INTEL_COMMON_BLOCK_HDA 49 select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR 50 select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE 51 select SOC_INTEL_COMMON_BLOCK_SA 52 select SOC_INTEL_COMMON_BLOCK_SCS 53 select SOC_INTEL_COMMON_BLOCK_SGX 54 select SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY 55 select SOC_INTEL_COMMON_BLOCK_SMM 56 select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP 57 select SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV 58 select SOC_INTEL_COMMON_BLOCK_UART 59 select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG 60 select SOC_INTEL_COMMON_FSP_RESET 61 select SOC_INTEL_COMMON_PCH_CLIENT 62 select SOC_INTEL_COMMON_NHLT 63 select SOC_INTEL_COMMON_RESET 64 select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT 65 select SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION 66 select SSE2 67 select SUPPORT_CPU_UCODE_IN_CBFS 68 select TSC_MONOTONIC_TIMER 69 select TSC_SYNC_MFENCE 70 select UDELAY_TSC 71 select UDK_2017_BINDING 72 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 73 select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 74 select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE 75 76config SOC_INTEL_SKYLAKE 77 bool 78 select SOC_INTEL_COMMON_SKYLAKE_BASE 79 80config SOC_INTEL_KABYLAKE 81 bool 82 select SOC_INTEL_COMMON_SKYLAKE_BASE 83 84config SOC_INTEL_SKYLAKE_LGA1151_V2 85 bool 86 select PLATFORM_USES_FSP2_1 87 select SOC_INTEL_COMMON_SKYLAKE_BASE 88 select SKYLAKE_SOC_PCH_H 89 help 90 Selected by mainboards with a LGA1151 v2 socket and a Z370, H310C or B365 PCH 91 92if SOC_INTEL_COMMON_SKYLAKE_BASE 93 94config MAX_HECI_DEVICES 95 int 96 default 5 97 98config MAX_CPUS 99 int 100 default 16 if MAINBOARD_SUPPORTS_COFFEELAKE_CPU 101 default 8 102 103config ENABLE_SATA_TEST_MODE 104 bool "Enable SATA test mode" 105 default n 106 help 107 Enable SATA test mode in FSP-S. 108 109config CPU_INTEL_NUM_FIT_ENTRIES 110 int 111 default 10 112 113config VBOOT 114 select VBOOT_MUST_REQUEST_DISPLAY 115 select VBOOT_STARTS_IN_BOOTBLOCK 116 select VBOOT_VBNV_CMOS 117 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH 118 119config CBFS_SIZE 120 default 0x200000 121 122config DCACHE_RAM_BASE 123 hex 124 default 0xfef00000 125 126config DCACHE_RAM_SIZE 127 hex 128 default 0x40000 129 help 130 The size of the cache-as-ram region required during bootblock 131 and/or romstage. 132 133config DCACHE_BSP_STACK_SIZE 134 hex 135 default 0x20400 if FSP_USES_CB_STACK 136 default 0x4000 137 help 138 The amount of anticipated stack usage in CAR by bootblock and 139 other stages. 140 141config FSP_TEMP_RAM_SIZE 142 hex 143 depends on FSP_USES_CB_STACK 144 default 0x10000 145 help 146 The amount of anticipated heap usage in CAR by FSP. 147 Refer to Platform FSP integration guide document to know 148 the exact FSP requirement for Heap setup. 149 150config EXCLUDE_NATIVE_SD_INTERFACE 151 bool 152 default n 153 help 154 If you set this option to n, will not use native SD controller. 155 156config IED_REGION_SIZE 157 hex 158 default 0x400000 159 160config PCR_BASE_ADDRESS 161 hex 162 default 0xfd000000 163 help 164 This option allows you to select MMIO Base Address of sideband bus. 165 166config SMM_RESERVED_SIZE 167 hex 168 default 0x200000 169 170config SMM_TSEG_SIZE 171 hex 172 default 0x800000 173 174config VGA_BIOS_ID 175 string 176 default "8086,0406" 177 178config SKYLAKE_SOC_PCH_H 179 bool 180 default n 181 182config NHLT_DMIC_1CH 183 bool 184 default n 185 help 186 Include DSP firmware settings for 1 channel DMIC array. 187 188config NHLT_DMIC_2CH 189 bool 190 default n 191 help 192 Include DSP firmware settings for 2 channel DMIC array. 193 194config NHLT_DMIC_4CH 195 bool 196 default n 197 help 198 Include DSP firmware settings for 4 channel DMIC array. 199 200config NHLT_NAU88L25 201 bool 202 default n 203 help 204 Include DSP firmware settings for nau88l25 headset codec. 205 206config NHLT_MAX98357 207 bool 208 default n 209 help 210 Include DSP firmware settings for max98357 amplifier. 211 212config NHLT_MAX98373 213 bool 214 default n 215 help 216 Include DSP firmware settings for max98373 amplifier. 217 218config NHLT_SSM4567 219 bool 220 default n 221 help 222 Include DSP firmware settings for ssm4567 smart amplifier. 223 224config NHLT_RT5514 225 bool 226 default n 227 help 228 Include DSP firmware settings for rt5514 DSP. 229 230config NHLT_RT5663 231 bool 232 default n 233 help 234 Include DSP firmware settings for rt5663 headset codec. 235 236config NHLT_MAX98927 237 bool 238 default n 239 help 240 Include DSP firmware settings for max98927 amplifier. 241 242config NHLT_DA7219 243 bool 244 default n 245 help 246 Include DSP firmware settings for DA7219 headset codec. 247 248# Use KabylakeFsp for both Skylake and Kabylake as it supports both. 249# SkylakeFsp is FSP 1.1 and therefore incompatible. 250config FSP_HEADER_PATH 251 default "3rdparty/fsp/AmberLakeFspBinPkg/Include/" if SOC_INTEL_SKYLAKE_LGA1151_V2 252 default "3rdparty/fsp/KabylakeFspBinPkg/Include/" 253 254config FSP_FD_PATH 255 default "3rdparty/fsp/AmberLakeFspBinPkg/Fsp.fd" if SOC_INTEL_SKYLAKE_LGA1151_V2 256 default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" 257 258config MAX_ROOT_PORTS 259 int 260 default 24 261 262config NO_FADT_8042 263 bool 264 default n 265 help 266 Choose this option if you want to disable 8042 Keyboard 267 268config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ 269 int 270 default 120 271 272config CPU_XTAL_HZ 273 default 24000000 274 275config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ 276 int 277 default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ 278 279config SOC_INTEL_COMMON_BLOCK_GSPI_MAX 280 int 281 default 2 282 283config SOC_INTEL_I2C_DEV_MAX 284 int 285 default 6 286 287config CPU_BCLK_MHZ 288 int 289 default 100 290 291config CONSOLE_UART_BASE_ADDRESS 292 hex 293 default 0xfe030000 294 depends on INTEL_LPSS_UART_FOR_CONSOLE 295 296# Clock divider parameters for 115200 baud rate 297config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL 298 hex 299 default 0x30 300 301config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL 302 hex 303 default 0xc35 304 305config CHIPSET_DEVICETREE 306 string 307 default "soc/intel/skylake/chipset.cb" 308 309config IFD_CHIPSET 310 string 311 default "sklkbl" 312 313config INTEL_TXT_BIOSACM_ALIGNMENT 314 hex 315 default 0x40000 # 256KB 316 317config MAINBOARD_SUPPORTS_SKYLAKE_CPU 318 bool "Board can contain Skylake CPU" 319 default !SOC_INTEL_SKYLAKE_LGA1151_V2 320 321if SKYLAKE_SOC_PCH_H 322 323config MAINBOARD_SUPPORTS_KABYLAKE_CPU 324 bool "Board can contain Kaby Lake CPU" 325 default !SOC_INTEL_SKYLAKE_LGA1151_V2 && SOC_INTEL_KABYLAKE 326 327config MAINBOARD_SUPPORTS_COFFEELAKE_CPU 328 bool "Board can contain Coffee Lake CPU" 329 default y if SOC_INTEL_SKYLAKE_LGA1151_V2 330 331endif 332 333if !SKYLAKE_SOC_PCH_H 334 335config MAINBOARD_SUPPORTS_KABYLAKE_DUAL 336 bool "Board can contain Kaby Lake DUAL core" 337 default y 338 339config MAINBOARD_SUPPORTS_KABYLAKE_QUAD 340 bool "Board can contain Kaby Lake QUAD core" 341 default y 342 343endif 344 345endif 346