1 /*
2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef STM32MP1_DEF_H
8 #define STM32MP1_DEF_H
9
10 #include <common/tbbr/tbbr_img_def.h>
11 #include <drivers/st/stm32mp1_rcc.h>
12 #include <dt-bindings/clock/stm32mp1-clks.h>
13 #include <dt-bindings/gpio/stm32-gpio.h>
14 #include <dt-bindings/reset/stm32mp1-resets.h>
15 #include <lib/utils_def.h>
16 #include <lib/xlat_tables/xlat_tables_defs.h>
17
18 #ifndef __ASSEMBLER__
19 #include <drivers/st/bsec.h>
20 #include <drivers/st/stm32mp1_clk.h>
21
22 #include <boot_api.h>
23 #include <stm32mp_common.h>
24 #include <stm32mp_dt.h>
25 #include <stm32mp1_dbgmcu.h>
26 #include <stm32mp1_private.h>
27 #include <stm32mp1_shared_resources.h>
28 #endif
29
30 #include "stm32mp1_fip_def.h"
31
32 /*******************************************************************************
33 * CHIP ID
34 ******************************************************************************/
35 #if STM32MP13
36 #define STM32MP1_CHIP_ID U(0x501)
37
38 #define STM32MP135C_PART_NB U(0x05010000)
39 #define STM32MP135A_PART_NB U(0x05010001)
40 #define STM32MP133C_PART_NB U(0x050100C0)
41 #define STM32MP133A_PART_NB U(0x050100C1)
42 #define STM32MP131C_PART_NB U(0x050106C8)
43 #define STM32MP131A_PART_NB U(0x050106C9)
44 #define STM32MP135F_PART_NB U(0x05010800)
45 #define STM32MP135D_PART_NB U(0x05010801)
46 #define STM32MP133F_PART_NB U(0x050108C0)
47 #define STM32MP133D_PART_NB U(0x050108C1)
48 #define STM32MP131F_PART_NB U(0x05010EC8)
49 #define STM32MP131D_PART_NB U(0x05010EC9)
50 #endif
51 #if STM32MP15
52 #define STM32MP1_CHIP_ID U(0x500)
53
54 #define STM32MP157C_PART_NB U(0x05000000)
55 #define STM32MP157A_PART_NB U(0x05000001)
56 #define STM32MP153C_PART_NB U(0x05000024)
57 #define STM32MP153A_PART_NB U(0x05000025)
58 #define STM32MP151C_PART_NB U(0x0500002E)
59 #define STM32MP151A_PART_NB U(0x0500002F)
60 #define STM32MP157F_PART_NB U(0x05000080)
61 #define STM32MP157D_PART_NB U(0x05000081)
62 #define STM32MP153F_PART_NB U(0x050000A4)
63 #define STM32MP153D_PART_NB U(0x050000A5)
64 #define STM32MP151F_PART_NB U(0x050000AE)
65 #define STM32MP151D_PART_NB U(0x050000AF)
66 #endif
67
68 #define STM32MP1_REV_B U(0x2000)
69 #if STM32MP13
70 #define STM32MP1_REV_Y U(0x1003)
71 #define STM32MP1_REV_Z U(0x1001)
72 #endif
73 #if STM32MP15
74 #define STM32MP1_REV_Z U(0x2001)
75 #endif
76
77 /*******************************************************************************
78 * PACKAGE ID
79 ******************************************************************************/
80 #if STM32MP15
81 #define PKG_AA_LFBGA448 U(4)
82 #define PKG_AB_LFBGA354 U(3)
83 #define PKG_AC_TFBGA361 U(2)
84 #define PKG_AD_TFBGA257 U(1)
85 #endif
86
87 /*******************************************************************************
88 * STM32MP1 memory map related constants
89 ******************************************************************************/
90 #define STM32MP_ROM_BASE U(0x00000000)
91 #define STM32MP_ROM_SIZE U(0x00020000)
92 #define STM32MP_ROM_SIZE_2MB_ALIGNED U(0x00200000)
93
94 #if STM32MP13
95 #define STM32MP_SYSRAM_BASE U(0x2FFE0000)
96 #define STM32MP_SYSRAM_SIZE U(0x00020000)
97 #define SRAM1_BASE U(0x30000000)
98 #define SRAM1_SIZE U(0x00004000)
99 #define SRAM2_BASE U(0x30004000)
100 #define SRAM2_SIZE U(0x00002000)
101 #define SRAM3_BASE U(0x30006000)
102 #define SRAM3_SIZE U(0x00002000)
103 #define SRAMS_BASE SRAM1_BASE
104 #define SRAMS_SIZE_2MB_ALIGNED U(0x00200000)
105 #endif /* STM32MP13 */
106 #if STM32MP15
107 #define STM32MP_SYSRAM_BASE U(0x2FFC0000)
108 #define STM32MP_SYSRAM_SIZE U(0x00040000)
109 #endif /* STM32MP15 */
110
111 #define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE
112 #define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \
113 STM32MP_SYSRAM_SIZE - \
114 STM32MP_NS_SYSRAM_SIZE)
115
116 #define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE
117 #define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE
118
119 #define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE
120 #define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \
121 STM32MP_NS_SYSRAM_SIZE)
122
123 /* DDR configuration */
124 #define STM32MP_DDR_BASE U(0xC0000000)
125 #define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
126
127 /* DDR power initializations */
128 #ifndef __ASSEMBLER__
129 enum ddr_type {
130 STM32MP_DDR3,
131 STM32MP_LPDDR2,
132 STM32MP_LPDDR3
133 };
134 #endif
135
136 /* Section used inside TF binaries */
137 #if STM32MP13
138 /* 512 Octets reserved for header */
139 #define STM32MP_HEADER_RESERVED_SIZE U(0x200)
140
141 #define STM32MP_BINARY_BASE STM32MP_SEC_SYSRAM_BASE
142
143 #define STM32MP_BINARY_SIZE STM32MP_SEC_SYSRAM_SIZE
144 #endif
145 #if STM32MP15
146 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
147 /* 256 Octets reserved for header */
148 #define STM32MP_HEADER_SIZE U(0x00000100)
149 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */
150 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000)
151
152 #define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \
153 STM32MP_PARAM_LOAD_SIZE + \
154 STM32MP_HEADER_SIZE)
155
156 #define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
157 (STM32MP_PARAM_LOAD_SIZE + \
158 STM32MP_HEADER_SIZE))
159 #endif
160
161 /* BL2 and BL32/sp_min require finer granularity tables */
162 #if defined(IMAGE_BL2)
163 #define MAX_XLAT_TABLES U(2) /* 8 KB for mapping */
164 #endif
165
166 #if defined(IMAGE_BL32)
167 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
168 #endif
169
170 /*
171 * MAX_MMAP_REGIONS is usually:
172 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
173 */
174 #if defined(IMAGE_BL2)
175 #if STM32MP_USB_PROGRAMMER
176 #define MAX_MMAP_REGIONS 8
177 #else
178 #define MAX_MMAP_REGIONS 7
179 #endif
180 #endif
181
182 #if STM32MP13
183 #define STM32MP_BL33_BASE STM32MP_DDR_BASE
184 #endif
185 #if STM32MP15
186 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
187 #endif
188 #define STM32MP_BL33_MAX_SIZE U(0x400000)
189
190 /* Define location for the MTD scratch buffer */
191 #if STM32MP13
192 #define STM32MP_MTD_BUFFER (SRAM1_BASE + \
193 SRAM1_SIZE - \
194 PLATFORM_MTD_MAX_PAGE_SIZE)
195 #endif
196
197 /*******************************************************************************
198 * STM32MP1 device/io map related constants (used for MMU)
199 ******************************************************************************/
200 #define STM32MP1_DEVICE1_BASE U(0x40000000)
201 #define STM32MP1_DEVICE1_SIZE U(0x40000000)
202
203 #define STM32MP1_DEVICE2_BASE U(0x80000000)
204 #define STM32MP1_DEVICE2_SIZE U(0x40000000)
205
206 /*******************************************************************************
207 * STM32MP1 RCC
208 ******************************************************************************/
209 #define RCC_BASE U(0x50000000)
210
211 /*******************************************************************************
212 * STM32MP1 PWR
213 ******************************************************************************/
214 #define PWR_BASE U(0x50001000)
215
216 /*******************************************************************************
217 * STM32MP1 GPIO
218 ******************************************************************************/
219 #define GPIOA_BASE U(0x50002000)
220 #define GPIOB_BASE U(0x50003000)
221 #define GPIOC_BASE U(0x50004000)
222 #define GPIOD_BASE U(0x50005000)
223 #define GPIOE_BASE U(0x50006000)
224 #define GPIOF_BASE U(0x50007000)
225 #define GPIOG_BASE U(0x50008000)
226 #define GPIOH_BASE U(0x50009000)
227 #define GPIOI_BASE U(0x5000A000)
228 #if STM32MP15
229 #define GPIOJ_BASE U(0x5000B000)
230 #define GPIOK_BASE U(0x5000C000)
231 #define GPIOZ_BASE U(0x54004000)
232 #endif
233 #define GPIO_BANK_OFFSET U(0x1000)
234
235 #if STM32MP15
236 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8
237 #endif
238
239 /*******************************************************************************
240 * STM32MP1 UART
241 ******************************************************************************/
242 #if STM32MP13
243 #define USART1_BASE U(0x4C000000)
244 #define USART2_BASE U(0x4C001000)
245 #endif
246 #if STM32MP15
247 #define USART1_BASE U(0x5C000000)
248 #define USART2_BASE U(0x4000E000)
249 #endif
250 #define USART3_BASE U(0x4000F000)
251 #define UART4_BASE U(0x40010000)
252 #define UART5_BASE U(0x40011000)
253 #define USART6_BASE U(0x44003000)
254 #define UART7_BASE U(0x40018000)
255 #define UART8_BASE U(0x40019000)
256
257 /* For UART crash console */
258 #define STM32MP_DEBUG_USART_BASE UART4_BASE
259 #if STM32MP13
260 /* UART4 on HSI@64MHz, TX on GPIOF12 Alternate 8 (Disco board) */
261 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000
262 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOD_BASE
263 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_S_AHB4ENSETR
264 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_S_AHB4ENSETR_GPIODEN
265 #define DEBUG_UART_TX_GPIO_PORT 6
266 #define DEBUG_UART_TX_GPIO_ALTERNATE 8
267 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART4CKSELR
268 #define DEBUG_UART_TX_CLKSRC RCC_UART4CKSELR_HSI
269 #endif /* STM32MP13 */
270 #if STM32MP15
271 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */
272 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000
273 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE
274 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR
275 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN
276 #define DEBUG_UART_TX_GPIO_PORT 11
277 #define DEBUG_UART_TX_GPIO_ALTERNATE 6
278 #define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR
279 #define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI
280 #endif /* STM32MP15 */
281 #define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
282 #define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
283 #define DEBUG_UART_RST_REG RCC_APB1RSTSETR
284 #define DEBUG_UART_RST_BIT RCC_APB1RSTSETR_UART4RST
285
286 /*******************************************************************************
287 * STM32MP1 ETZPC
288 ******************************************************************************/
289 #define STM32MP1_ETZPC_BASE U(0x5C007000)
290
291 /* ETZPC TZMA IDs */
292 #define STM32MP1_ETZPC_TZMA_ROM U(0)
293 #define STM32MP1_ETZPC_TZMA_SYSRAM U(1)
294
295 #define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0)
296
297 /* ETZPC DECPROT IDs */
298 #define STM32MP1_ETZPC_STGENC_ID 0
299 #define STM32MP1_ETZPC_BKPSRAM_ID 1
300 #define STM32MP1_ETZPC_IWDG1_ID 2
301 #define STM32MP1_ETZPC_USART1_ID 3
302 #define STM32MP1_ETZPC_SPI6_ID 4
303 #define STM32MP1_ETZPC_I2C4_ID 5
304 #define STM32MP1_ETZPC_RNG1_ID 7
305 #define STM32MP1_ETZPC_HASH1_ID 8
306 #define STM32MP1_ETZPC_CRYP1_ID 9
307 #define STM32MP1_ETZPC_DDRCTRL_ID 10
308 #define STM32MP1_ETZPC_DDRPHYC_ID 11
309 #define STM32MP1_ETZPC_I2C6_ID 12
310 #define STM32MP1_ETZPC_SEC_ID_LIMIT 13
311
312 #define STM32MP1_ETZPC_TIM2_ID 16
313 #define STM32MP1_ETZPC_TIM3_ID 17
314 #define STM32MP1_ETZPC_TIM4_ID 18
315 #define STM32MP1_ETZPC_TIM5_ID 19
316 #define STM32MP1_ETZPC_TIM6_ID 20
317 #define STM32MP1_ETZPC_TIM7_ID 21
318 #define STM32MP1_ETZPC_TIM12_ID 22
319 #define STM32MP1_ETZPC_TIM13_ID 23
320 #define STM32MP1_ETZPC_TIM14_ID 24
321 #define STM32MP1_ETZPC_LPTIM1_ID 25
322 #define STM32MP1_ETZPC_WWDG1_ID 26
323 #define STM32MP1_ETZPC_SPI2_ID 27
324 #define STM32MP1_ETZPC_SPI3_ID 28
325 #define STM32MP1_ETZPC_SPDIFRX_ID 29
326 #define STM32MP1_ETZPC_USART2_ID 30
327 #define STM32MP1_ETZPC_USART3_ID 31
328 #define STM32MP1_ETZPC_UART4_ID 32
329 #define STM32MP1_ETZPC_UART5_ID 33
330 #define STM32MP1_ETZPC_I2C1_ID 34
331 #define STM32MP1_ETZPC_I2C2_ID 35
332 #define STM32MP1_ETZPC_I2C3_ID 36
333 #define STM32MP1_ETZPC_I2C5_ID 37
334 #define STM32MP1_ETZPC_CEC_ID 38
335 #define STM32MP1_ETZPC_DAC_ID 39
336 #define STM32MP1_ETZPC_UART7_ID 40
337 #define STM32MP1_ETZPC_UART8_ID 41
338 #define STM32MP1_ETZPC_MDIOS_ID 44
339 #define STM32MP1_ETZPC_TIM1_ID 48
340 #define STM32MP1_ETZPC_TIM8_ID 49
341 #define STM32MP1_ETZPC_USART6_ID 51
342 #define STM32MP1_ETZPC_SPI1_ID 52
343 #define STM32MP1_ETZPC_SPI4_ID 53
344 #define STM32MP1_ETZPC_TIM15_ID 54
345 #define STM32MP1_ETZPC_TIM16_ID 55
346 #define STM32MP1_ETZPC_TIM17_ID 56
347 #define STM32MP1_ETZPC_SPI5_ID 57
348 #define STM32MP1_ETZPC_SAI1_ID 58
349 #define STM32MP1_ETZPC_SAI2_ID 59
350 #define STM32MP1_ETZPC_SAI3_ID 60
351 #define STM32MP1_ETZPC_DFSDM_ID 61
352 #define STM32MP1_ETZPC_TT_FDCAN_ID 62
353 #define STM32MP1_ETZPC_LPTIM2_ID 64
354 #define STM32MP1_ETZPC_LPTIM3_ID 65
355 #define STM32MP1_ETZPC_LPTIM4_ID 66
356 #define STM32MP1_ETZPC_LPTIM5_ID 67
357 #define STM32MP1_ETZPC_SAI4_ID 68
358 #define STM32MP1_ETZPC_VREFBUF_ID 69
359 #define STM32MP1_ETZPC_DCMI_ID 70
360 #define STM32MP1_ETZPC_CRC2_ID 71
361 #define STM32MP1_ETZPC_ADC_ID 72
362 #define STM32MP1_ETZPC_HASH2_ID 73
363 #define STM32MP1_ETZPC_RNG2_ID 74
364 #define STM32MP1_ETZPC_CRYP2_ID 75
365 #define STM32MP1_ETZPC_SRAM1_ID 80
366 #define STM32MP1_ETZPC_SRAM2_ID 81
367 #define STM32MP1_ETZPC_SRAM3_ID 82
368 #define STM32MP1_ETZPC_SRAM4_ID 83
369 #define STM32MP1_ETZPC_RETRAM_ID 84
370 #define STM32MP1_ETZPC_OTG_ID 85
371 #define STM32MP1_ETZPC_SDMMC3_ID 86
372 #define STM32MP1_ETZPC_DLYBSD3_ID 87
373 #define STM32MP1_ETZPC_DMA1_ID 88
374 #define STM32MP1_ETZPC_DMA2_ID 89
375 #define STM32MP1_ETZPC_DMAMUX_ID 90
376 #define STM32MP1_ETZPC_FMC_ID 91
377 #define STM32MP1_ETZPC_QSPI_ID 92
378 #define STM32MP1_ETZPC_DLYBQ_ID 93
379 #define STM32MP1_ETZPC_ETH_ID 94
380 #define STM32MP1_ETZPC_RSV_ID 95
381
382 #define STM32MP_ETZPC_MAX_ID 96
383
384 /*******************************************************************************
385 * STM32MP1 TZC (TZ400)
386 ******************************************************************************/
387 #define STM32MP1_TZC_BASE U(0x5C006000)
388
389 #if STM32MP13
390 #define STM32MP1_FILTER_BIT_ALL TZC_400_REGION_ATTR_FILTER_BIT(0)
391 #endif
392 #if STM32MP15
393 #define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \
394 TZC_400_REGION_ATTR_FILTER_BIT(1))
395 #endif
396
397 /*******************************************************************************
398 * STM32MP1 SDMMC
399 ******************************************************************************/
400 #define STM32MP_SDMMC1_BASE U(0x58005000)
401 #define STM32MP_SDMMC2_BASE U(0x58007000)
402 #define STM32MP_SDMMC3_BASE U(0x48004000)
403
404 /*******************************************************************************
405 * STM32MP1 BSEC / OTP
406 ******************************************************************************/
407 #define STM32MP1_OTP_MAX_ID 0x5FU
408 #define STM32MP1_UPPER_OTP_START 0x20U
409
410 #define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U)
411
412 /* OTP labels */
413 #define CFG0_OTP "cfg0-otp"
414 #define PART_NUMBER_OTP "part-number-otp"
415 #if STM32MP15
416 #define PACKAGE_OTP "package-otp"
417 #endif
418 #define HW2_OTP "hw2-otp"
419 #if STM32MP13
420 #define NAND_OTP "cfg9-otp"
421 #define NAND2_OTP "cfg10-otp"
422 #endif
423 #if STM32MP15
424 #define NAND_OTP "nand-otp"
425 #endif
426 #define MONOTONIC_OTP "monotonic-otp"
427 #define UID_OTP "uid-otp"
428 #define PKH_OTP "pkh-otp"
429 #define ENCKEY_OTP "oem-enc-key"
430 #define BOARD_ID_OTP "board-id"
431
432 /* OTP mask */
433 /* CFG0 */
434 #if STM32MP13
435 #define CFG0_OTP_MODE_MASK GENMASK_32(9, 0)
436 #define CFG0_OTP_MODE_SHIFT 0
437 #define CFG0_OPEN_DEVICE 0x17U
438 #define CFG0_CLOSED_DEVICE 0x3FU
439 #define CFG0_CLOSED_DEVICE_NO_BOUNDARY_SCAN 0x17FU
440 #define CFG0_CLOSED_DEVICE_NO_JTAG 0x3FFU
441 #endif
442 #if STM32MP15
443 #define CFG0_CLOSED_DEVICE BIT(6)
444 #endif
445
446 /* PART NUMBER */
447 #if STM32MP13
448 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(11, 0)
449 #endif
450 #if STM32MP15
451 #define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0)
452 #endif
453 #define PART_NUMBER_OTP_PART_SHIFT 0
454
455 /* PACKAGE */
456 #if STM32MP15
457 #define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27)
458 #define PACKAGE_OTP_PKG_SHIFT 27
459 #endif
460
461 /* IWDG OTP */
462 #define HW2_OTP_IWDG_HW_POS U(3)
463 #define HW2_OTP_IWDG_FZ_STOP_POS U(5)
464 #define HW2_OTP_IWDG_FZ_STANDBY_POS U(7)
465
466 /* HW2 OTP */
467 #define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13)
468
469 /* NAND OTP */
470 /* NAND parameter storage flag */
471 #define NAND_PARAM_STORED_IN_OTP BIT(31)
472
473 /* NAND page size in bytes */
474 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
475 #define NAND_PAGE_SIZE_SHIFT 29
476 #define NAND_PAGE_SIZE_2K U(0)
477 #define NAND_PAGE_SIZE_4K U(1)
478 #define NAND_PAGE_SIZE_8K U(2)
479
480 /* NAND block size in pages */
481 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
482 #define NAND_BLOCK_SIZE_SHIFT 27
483 #define NAND_BLOCK_SIZE_64_PAGES U(0)
484 #define NAND_BLOCK_SIZE_128_PAGES U(1)
485 #define NAND_BLOCK_SIZE_256_PAGES U(2)
486
487 /* NAND number of block (in unit of 256 blocks) */
488 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
489 #define NAND_BLOCK_NB_SHIFT 19
490 #define NAND_BLOCK_NB_UNIT U(256)
491
492 /* NAND bus width in bits */
493 #define NAND_WIDTH_MASK BIT(18)
494 #define NAND_WIDTH_SHIFT 18
495
496 /* NAND number of ECC bits per 512 bytes */
497 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
498 #define NAND_ECC_BIT_NB_SHIFT 15
499 #define NAND_ECC_BIT_NB_UNSET U(0)
500 #define NAND_ECC_BIT_NB_1_BITS U(1)
501 #define NAND_ECC_BIT_NB_4_BITS U(2)
502 #define NAND_ECC_BIT_NB_8_BITS U(3)
503 #define NAND_ECC_ON_DIE U(4)
504
505 /* NAND number of planes */
506 #define NAND_PLANE_BIT_NB_MASK BIT(14)
507
508 /* NAND2 OTP */
509 #define NAND2_PAGE_SIZE_SHIFT 16
510
511 /* NAND2 config distribution */
512 #define NAND2_CONFIG_DISTRIB BIT(0)
513 #define NAND2_PNAND_NAND2_SNAND_NAND1 U(0)
514 #define NAND2_PNAND_NAND1_SNAND_NAND2 U(1)
515
516 /* MONOTONIC OTP */
517 #define MAX_MONOTONIC_VALUE 32
518
519 /* UID OTP */
520 #define UID_WORD_NB U(3)
521
522 /*******************************************************************************
523 * STM32MP1 TAMP
524 ******************************************************************************/
525 #define TAMP_BASE U(0x5C00A000)
526 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
527 #define TAMP_BKP_REG_CLK RTCAPB
528 #define TAMP_COUNTR U(0x40)
529
530 #if !(defined(__LINKER__) || defined(__ASSEMBLER__))
tamp_bkpr(uint32_t idx)531 static inline uintptr_t tamp_bkpr(uint32_t idx)
532 {
533 return TAMP_BKP_REGISTER_BASE + (idx << 2);
534 }
535 #endif
536
537 /*******************************************************************************
538 * STM32MP1 USB
539 ******************************************************************************/
540 #define USB_OTG_BASE U(0x49000000)
541
542 /*******************************************************************************
543 * STM32MP1 DDRCTRL
544 ******************************************************************************/
545 #define DDRCTRL_BASE U(0x5A003000)
546
547 /*******************************************************************************
548 * STM32MP1 DDRPHYC
549 ******************************************************************************/
550 #define DDRPHYC_BASE U(0x5A004000)
551
552 /*******************************************************************************
553 * STM32MP1 IWDG
554 ******************************************************************************/
555 #define IWDG_MAX_INSTANCE U(2)
556 #define IWDG1_INST U(0)
557 #define IWDG2_INST U(1)
558
559 #define IWDG1_BASE U(0x5C003000)
560 #define IWDG2_BASE U(0x5A002000)
561
562 /*******************************************************************************
563 * Miscellaneous STM32MP1 peripherals base address
564 ******************************************************************************/
565 #define BSEC_BASE U(0x5C005000)
566 #if STM32MP13
567 #define CRYP_BASE U(0x54002000)
568 #endif
569 #if STM32MP15
570 #define CRYP1_BASE U(0x54001000)
571 #endif
572 #define DBGMCU_BASE U(0x50081000)
573 #if STM32MP13
574 #define HASH_BASE U(0x54003000)
575 #endif
576 #if STM32MP15
577 #define HASH1_BASE U(0x54002000)
578 #endif
579 #if STM32MP13
580 #define I2C3_BASE U(0x4C004000)
581 #define I2C4_BASE U(0x4C005000)
582 #define I2C5_BASE U(0x4C006000)
583 #endif
584 #if STM32MP15
585 #define I2C4_BASE U(0x5C002000)
586 #define I2C6_BASE U(0x5c009000)
587 #endif
588 #if STM32MP13
589 #define RNG_BASE U(0x54004000)
590 #endif
591 #if STM32MP15
592 #define RNG1_BASE U(0x54003000)
593 #endif
594 #define RTC_BASE U(0x5c004000)
595 #if STM32MP13
596 #define SPI4_BASE U(0x4C002000)
597 #define SPI5_BASE U(0x4C003000)
598 #endif
599 #if STM32MP15
600 #define SPI6_BASE U(0x5c001000)
601 #endif
602 #define STGEN_BASE U(0x5c008000)
603 #define SYSCFG_BASE U(0x50020000)
604
605 /*******************************************************************************
606 * STM32MP13 SAES
607 ******************************************************************************/
608 #define SAES_BASE U(0x54005000)
609
610 /*******************************************************************************
611 * STM32MP13 PKA
612 ******************************************************************************/
613 #define PKA_BASE U(0x54006000)
614
615 /*******************************************************************************
616 * REGULATORS
617 ******************************************************************************/
618 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */
619 #define PLAT_NB_RDEVS U(19)
620 /* 2 FIXED */
621 #define PLAT_NB_FIXED_REGUS U(2)
622
623 /*******************************************************************************
624 * STM32MP1 CLOCKS
625 ******************************************************************************/
626 #define PLL1_NOMINAL_FREQ_IN_KHZ U(650000) /* 650MHz */
627
628 /*******************************************************************************
629 * Device Tree defines
630 ******************************************************************************/
631 #if STM32MP13
632 #define DT_BSEC_COMPAT "st,stm32mp13-bsec"
633 #define DT_DDR_COMPAT "st,stm32mp13-ddr"
634 #endif
635 #if STM32MP15
636 #define DT_BSEC_COMPAT "st,stm32mp15-bsec"
637 #define DT_DDR_COMPAT "st,stm32mp1-ddr"
638 #endif
639 #define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
640 #define DT_PWR_COMPAT "st,stm32mp1,pwr-reg"
641 #if STM32MP13
642 #define DT_RCC_CLK_COMPAT "st,stm32mp13-rcc"
643 #define DT_RCC_SEC_CLK_COMPAT "st,stm32mp13-rcc-secure"
644 #endif
645 #if STM32MP15
646 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
647 #define DT_RCC_SEC_CLK_COMPAT "st,stm32mp1-rcc-secure"
648 #endif
649 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2"
650 #define DT_UART_COMPAT "st,stm32h7-uart"
651
652 #endif /* STM32MP1_DEF_H */
653