1 /* 2 * Copyright (C) 2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STPMIC2_H 8 #define STPMIC2_H 9 10 #include <drivers/st/stm32_i2c.h> 11 #include <lib/utils_def.h> 12 13 enum { 14 STPMIC2_BUCK1 = 0, 15 STPMIC2_BUCK2, 16 STPMIC2_BUCK3, 17 STPMIC2_BUCK4, 18 STPMIC2_BUCK5, 19 STPMIC2_BUCK6, 20 STPMIC2_BUCK7, 21 STPMIC2_REFDDR, 22 STPMIC2_LDO1, 23 STPMIC2_LDO2, 24 STPMIC2_LDO3, 25 STPMIC2_LDO4, 26 STPMIC2_LDO5, 27 STPMIC2_LDO6, 28 STPMIC2_LDO7, 29 STPMIC2_LDO8, 30 STPMIC2_NB_REG 31 }; 32 33 /* Status Registers */ 34 #define PRODUCT_ID 0x00 35 #define VERSION_SR 0x01 36 #define TURN_ON_SR 0x02 37 #define TURN_OFF_SR 0x03 38 #define RESTART_SR 0x04 39 #define OCP_SR1 0x05 40 #define OCP_SR2 0x06 41 #define EN_SR1 0x07 42 #define EN_SR2 0x08 43 #define FS_CNT_SR1 0x09 44 #define FS_CNT_SR2 0x0A 45 #define FS_CNT_SR3 0x0B 46 #define MODE_SR 0x0C 47 /* Control Registers */ 48 #define MAIN_CR 0x10 49 #define VINLOW_CR 0x11 50 #define PKEY_LKP_CR 0x12 51 #define WDG_CR 0x13 52 #define WDG_TMR_CR 0x14 53 #define WDG_TMR_SR 0x15 54 #define FS_OCP_CR1 0x16 55 #define FS_OCP_CR2 0x17 56 #define PADS_PULL_CR 0x18 57 #define BUCKS_PD_CR1 0x19 58 #define BUCKS_PD_CR2 0x1A 59 #define LDOS_PD_CR1 0x1B 60 #define LDOS_PD_CR2 0x1C 61 #define BUCKS_MRST_CR 0x1D 62 #define LDOS_MRST_CR 0x1E 63 /* Buck CR */ 64 #define BUCK1_MAIN_CR1 0x20 65 #define BUCK1_MAIN_CR2 0x21 66 #define BUCK1_ALT_CR1 0x22 67 #define BUCK1_ALT_CR2 0x23 68 #define BUCK1_PWRCTRL_CR 0x24 69 #define BUCK2_MAIN_CR1 0x25 70 #define BUCK2_MAIN_CR2 0x26 71 #define BUCK2_ALT_CR1 0x27 72 #define BUCK2_ALT_CR2 0x28 73 #define BUCK2_PWRCTRL_CR 0x29 74 #define BUCK3_MAIN_CR1 0x2A 75 #define BUCK3_MAIN_CR2 0x2B 76 #define BUCK3_ALT_CR1 0x2C 77 #define BUCK3_ALT_CR2 0x2D 78 #define BUCK3_PWRCTRL_CR 0x2E 79 #define BUCK4_MAIN_CR1 0x2F 80 #define BUCK4_MAIN_CR2 0x30 81 #define BUCK4_ALT_CR1 0x31 82 #define BUCK4_ALT_CR2 0x32 83 #define BUCK4_PWRCTRL_CR 0x33 84 #define BUCK5_MAIN_CR1 0x34 85 #define BUCK5_MAIN_CR2 0x35 86 #define BUCK5_ALT_CR1 0x36 87 #define BUCK5_ALT_CR2 0x37 88 #define BUCK5_PWRCTRL_CR 0x38 89 #define BUCK6_MAIN_CR1 0x39 90 #define BUCK6_MAIN_CR2 0x3A 91 #define BUCK6_ALT_CR1 0x3B 92 #define BUCK6_ALT_CR2 0x3C 93 #define BUCK6_PWRCTRL_CR 0x3D 94 #define BUCK7_MAIN_CR1 0x3E 95 #define BUCK7_MAIN_CR2 0x3F 96 #define BUCK7_ALT_CR1 0x40 97 #define BUCK7_ALT_CR2 0x41 98 #define BUCK7_PWRCTRL_CR 0x42 99 /* LDO CR */ 100 #define LDO1_MAIN_CR 0x4C 101 #define LDO1_ALT_CR 0x4D 102 #define LDO1_PWRCTRL_CR 0x4E 103 #define LDO2_MAIN_CR 0x4F 104 #define LDO2_ALT_CR 0x50 105 #define LDO2_PWRCTRL_CR 0x51 106 #define LDO3_MAIN_CR 0x52 107 #define LDO3_ALT_CR 0x53 108 #define LDO3_PWRCTRL_CR 0x54 109 #define LDO4_MAIN_CR 0x55 110 #define LDO4_ALT_CR 0x56 111 #define LDO4_PWRCTRL_CR 0x57 112 #define LDO5_MAIN_CR 0x58 113 #define LDO5_ALT_CR 0x59 114 #define LDO5_PWRCTRL_CR 0x5A 115 #define LDO6_MAIN_CR 0x5B 116 #define LDO6_ALT_CR 0x5C 117 #define LDO6_PWRCTRL_CR 0x5D 118 #define LDO7_MAIN_CR 0x5E 119 #define LDO7_ALT_CR 0x5F 120 #define LDO7_PWRCTRL_CR 0x60 121 #define LDO8_MAIN_CR 0x61 122 #define LDO8_ALT_CR 0x62 123 #define LDO8_PWRCTRL_CR 0x63 124 #define REFDDR_MAIN_CR 0x64 125 #define REFDDR_ALT_CR 0x65 126 #define REFDDR_PWRCTRL_CR 0x66 127 /* INTERRUPT CR */ 128 #define INT_PENDING_R1 0x70 129 #define INT_PENDING_R2 0x71 130 #define INT_PENDING_R3 0x72 131 #define INT_PENDING_R4 0x73 132 #define INT_CLEAR_R1 0x74 133 #define INT_CLEAR_R2 0x75 134 #define INT_CLEAR_R3 0x76 135 #define INT_CLEAR_R4 0x77 136 #define INT_MASK_R1 0x78 137 #define INT_MASK_R2 0x79 138 #define INT_MASK_R3 0x7A 139 #define INT_MASK_R4 0x7B 140 #define INT_SRC_R1 0x7C 141 #define INT_SRC_R2 0x7D 142 #define INT_SRC_R3 0x7E 143 #define INT_SRC_R4 0x7F 144 #define INT_DBG_LATCH_R1 0x80 145 #define INT_DBG_LATCH_R2 0x81 146 #define INT_DBG_LATCH_R3 0x82 147 #define INT_DBG_LATCH_R4 0x83 148 149 /* BUCKS_MRST_CR bits definition */ 150 #define BUCK1_MRST BIT(0) 151 #define BUCK2_MRST BIT(1) 152 #define BUCK3_MRST BIT(2) 153 #define BUCK4_MRST BIT(3) 154 #define BUCK5_MRST BIT(4) 155 #define BUCK6_MRST BIT(5) 156 #define BUCK7_MRST BIT(6) 157 #define REFDDR_MRST BIT(7) 158 159 /* LDOS_MRST_CR bits definition */ 160 #define LDO1_MRST BIT(0) 161 #define LDO2_MRST BIT(1) 162 #define LDO3_MRST BIT(2) 163 #define LDO4_MRST BIT(3) 164 #define LDO5_MRST BIT(4) 165 #define LDO6_MRST BIT(5) 166 #define LDO7_MRST BIT(6) 167 #define LDO8_MRST BIT(7) 168 169 /* LDOx_MAIN_CR */ 170 #define LDO_VOLT_SHIFT 1 171 #define LDO_BYPASS BIT(6) 172 #define LDO1_INPUT_SRC BIT(7) 173 #define LDO3_SNK_SRC BIT(7) 174 #define LDO4_INPUT_SRC_SHIFT 6 175 #define LDO4_INPUT_SRC_MASK GENMASK_32(7, 6) 176 177 /* PWRCTRL register bit definition */ 178 #define PWRCTRL_EN BIT(0) 179 #define PWRCTRL_RS BIT(1) 180 #define PWRCTRL_SEL_SHIFT 2 181 #define PWRCTRL_SEL_MASK GENMASK_32(3, 2) 182 183 /* BUCKx_MAIN_CR2 */ 184 #define PREG_MODE_SHIFT 1 185 #define PREG_MODE_MASK GENMASK_32(2, 1) 186 187 /* BUCKS_PD_CR1 */ 188 #define BUCK1_PD_MASK GENMASK_32(1, 0) 189 #define BUCK2_PD_MASK GENMASK_32(3, 2) 190 #define BUCK3_PD_MASK GENMASK_32(5, 4) 191 #define BUCK4_PD_MASK GENMASK_32(7, 6) 192 193 #define BUCK1_PD_FAST BIT(1) 194 #define BUCK2_PD_FAST BIT(3) 195 #define BUCK3_PD_FAST BIT(5) 196 #define BUCK4_PD_FAST BIT(7) 197 198 /* BUCKS_PD_CR2 */ 199 #define BUCK5_PD_MASK GENMASK_32(1, 0) 200 #define BUCK6_PD_MASK GENMASK_32(3, 2) 201 #define BUCK7_PD_MASK GENMASK_32(5, 4) 202 203 #define BUCK5_PD_FAST BIT(1) 204 #define BUCK6_PD_FAST BIT(3) 205 #define BUCK7_PD_FAST BIT(5) 206 207 /* LDOS_PD_CR1 */ 208 #define LDO1_PD BIT(0) 209 #define LDO2_PD BIT(1) 210 #define LDO3_PD BIT(2) 211 #define LDO4_PD BIT(3) 212 #define LDO5_PD BIT(4) 213 #define LDO6_PD BIT(5) 214 #define LDO7_PD BIT(6) 215 #define LDO8_PD BIT(7) 216 217 /* LDOS_PD_CR2 */ 218 #define REFDDR_PD BIT(0) 219 220 /* FS_OCP_CR1 */ 221 #define FS_OCP_BUCK1 BIT(0) 222 #define FS_OCP_BUCK2 BIT(1) 223 #define FS_OCP_BUCK3 BIT(2) 224 #define FS_OCP_BUCK4 BIT(3) 225 #define FS_OCP_BUCK5 BIT(4) 226 #define FS_OCP_BUCK6 BIT(5) 227 #define FS_OCP_BUCK7 BIT(6) 228 #define FS_OCP_REFDDR BIT(7) 229 230 /* FS_OCP_CR2 */ 231 #define FS_OCP_LDO1 BIT(0) 232 #define FS_OCP_LDO2 BIT(1) 233 #define FS_OCP_LDO3 BIT(2) 234 #define FS_OCP_LDO4 BIT(3) 235 #define FS_OCP_LDO5 BIT(4) 236 #define FS_OCP_LDO6 BIT(5) 237 #define FS_OCP_LDO7 BIT(6) 238 #define FS_OCP_LDO8 BIT(7) 239 240 /* IRQ definitions */ 241 #define IT_PONKEY_F 0 242 #define IT_PONKEY_R 1 243 #define IT_BUCK1_OCP 16 244 #define IT_BUCK2_OCP 17 245 #define IT_BUCK3_OCP 18 246 #define IT_BUCK4_OCP 19 247 #define IT_BUCK5_OCP 20 248 #define IT_BUCK6_OCP 21 249 #define IT_BUCK7_OCP 22 250 #define IT_REFDDR_OCP 23 251 #define IT_LDO1_OCP 24 252 #define IT_LDO2_OCP 25 253 #define IT_LDO3_OCP 26 254 #define IT_LDO4_OCP 27 255 #define IT_LDO5_OCP 28 256 #define IT_LDO6_OCP 29 257 #define IT_LDO7_OCP 30 258 #define IT_LDO8_OCP 31 259 260 enum stpmic2_prop_id { 261 STPMIC2_MASK_RESET = 0, 262 STPMIC2_PULL_DOWN, 263 STPMIC2_BYPASS, /* arg: 1=set 0=reset */ 264 STPMIC2_SINK_SOURCE, 265 STPMIC2_OCP, 266 }; 267 268 struct pmic_handle_s { 269 struct i2c_handle_s *i2c_handle; 270 uint32_t i2c_addr; 271 unsigned int pmic_status; 272 }; 273 274 int stpmic2_register_read(struct pmic_handle_s *pmic, 275 uint8_t register_id, uint8_t *value); 276 int stpmic2_register_write(struct pmic_handle_s *pmic, 277 uint8_t register_id, uint8_t value); 278 int stpmic2_register_update(struct pmic_handle_s *pmic, 279 uint8_t register_id, uint8_t value, uint8_t mask); 280 281 int stpmic2_regulator_set_state(struct pmic_handle_s *pmic, 282 uint8_t id, bool enable); 283 int stpmic2_regulator_get_state(struct pmic_handle_s *pmic, 284 uint8_t id, bool *enabled); 285 286 int stpmic2_regulator_levels_mv(struct pmic_handle_s *pmic, 287 uint8_t id, const uint16_t **levels, 288 size_t *levels_count); 289 int stpmic2_regulator_get_voltage(struct pmic_handle_s *pmic, 290 uint8_t id, uint16_t *val); 291 int stpmic2_regulator_set_voltage(struct pmic_handle_s *pmic, 292 uint8_t id, uint16_t millivolts); 293 294 #if EVENT_LOG_LEVEL == LOG_LEVEL_VERBOSE 295 void stpmic2_dump_regulators(struct pmic_handle_s *pmic); 296 #endif 297 298 int stpmic2_get_version(struct pmic_handle_s *pmic, uint8_t *val); 299 int stpmic2_get_product_id(struct pmic_handle_s *pmic, uint8_t *val); 300 301 int stpmic2_regulator_get_prop(struct pmic_handle_s *pmic, uint8_t id, 302 enum stpmic2_prop_id prop); 303 304 int stpmic2_regulator_set_prop(struct pmic_handle_s *pmic, uint8_t id, 305 enum stpmic2_prop_id prop, uint32_t arg); 306 307 #endif /*STPMIC2_H*/ 308