1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 3 #ifndef __EMI_HW_H__ 4 #define __EMI_HW_H__ 5 6 /* from EMI golden setting */ 7 //#define EMI_MP_SETTING 8 #define REAL_CHIP_EMI_GOLDEN_SETTING 9 #define INFRA_DRAMC_REG_CONFIG (0x100010b4) 10 #define INFRACFG_AO_MEM_BASE (0x10002000) 11 #define SUB_INFRACFG_AO_MEM_BASE (0x1030E000) 12 #define MCUSYS_PAR_WRAP_BASE (0x0C530000) 13 14 #define EMI_BASE (0x10219000) 15 #define SUB_EMI_BASE (0x1021D000) 16 #define EMI_MPU_BASE (0x10226000) 17 #define SUB_EMI_MPU_BASE (0x10225000) 18 #define CHN0_EMI_BASE (0x10235000) 19 #define CHN1_EMI_BASE (0x10245000) 20 21 #define EMI_CONA (EMI_BASE+0x000) 22 #define EMI_CONB (EMI_BASE+0x008) 23 #define EMI_CONC (EMI_BASE+0x010) 24 #define EMI_COND (EMI_BASE+0x018) 25 #define EMI_CONE (EMI_BASE+0x020) 26 #define EMI_CONF (EMI_BASE+0x028) 27 #define EMI_CONG (EMI_BASE+0x030) 28 #define EMI_CONH (EMI_BASE+0x038) 29 #define EMI_CONH_2ND (EMI_BASE+0x03C) 30 #define EMI_CONI (EMI_BASE+0x040) 31 #define EMI_CONJ (EMI_BASE+0x048) 32 #define EMI_CONK (EMI_BASE+0x050) 33 #define EMI_CONM (EMI_BASE+0x060) 34 #define EMI_CONN (EMI_BASE+0x068) 35 #define EMI_CONO (EMI_BASE+0x070) 36 #define EMI_MDCT (EMI_BASE+0x078) 37 #define EMI_MDCT_2ND (EMI_BASE+0x07C) 38 #define EMI_IOCL (EMI_BASE+0x0D0) 39 #define EMI_IOCL_2ND (EMI_BASE+0x0D4) 40 #define EMI_IOCM (EMI_BASE+0x0D8) 41 #define EMI_IOCM_2ND (EMI_BASE+0x0DC) 42 #define EMI_TESTB (EMI_BASE+0x0E8) 43 #define EMI_TESTC (EMI_BASE+0x0F0) 44 #define EMI_TESTD (EMI_BASE+0x0F8) 45 #define EMI_ARBA (EMI_BASE+0x100) 46 #define EMI_ARBB (EMI_BASE+0x108) 47 #define EMI_ARBC (EMI_BASE+0x110) 48 #define EMI_ARBD (EMI_BASE+0x118) 49 #define EMI_ARBE (EMI_BASE+0x120) 50 #define EMI_ARBF (EMI_BASE+0x128) 51 #define EMI_ARBG (EMI_BASE+0x130) 52 #define EMI_ARBH (EMI_BASE+0x138) 53 #define EMI_ARBI (EMI_BASE+0x140) 54 #define EMI_ARBI_2ND (EMI_BASE+0x144) 55 #define EMI_ARBJ_2ND (EMI_BASE+0x14C) 56 #define EMI_ARBK (EMI_BASE+0x150) 57 #define EMI_ARBK_2ND (EMI_BASE+0x154) 58 #define EMI_SLCT (EMI_BASE+0x158) 59 #define EMI_MPUD0_ST (EMI_BASE+0x160) 60 #define EMI_MPUD1_ST (EMI_BASE+0x164) 61 #define EMI_MPUD2_ST (EMI_BASE+0x168) 62 #define EMI_MPUD3_ST (EMI_BASE+0x16C) 63 #define EMI_MPUD4_ST (EMI_BASE+0x170) 64 #define EMI_MPUD5_ST (EMI_BASE+0x174) 65 #define EMI_MPUD6_ST (EMI_BASE+0x178) 66 #define EMI_MPUD7_ST (EMI_BASE+0x17C) 67 #define EMI_MPUD8_ST (EMI_BASE+0x180) 68 #define EMI_MPUD9_ST (EMI_BASE+0x184) 69 #define EMI_MPUD10_ST (EMI_BASE+0x188) 70 #define EMI_MPUD11_ST (EMI_BASE+0x18C) 71 #define EMI_MPUD12_ST (EMI_BASE+0x190) 72 #define EMI_MPUD13_ST (EMI_BASE+0x194) 73 #define EMI_MPUD14_ST (EMI_BASE+0x198) 74 #define EMI_MPUD15_ST (EMI_BASE+0x19C) 75 #define EMI_MPUD16_ST (EMI_BASE+0x1A0) 76 #define EMI_MPUD17_ST (EMI_BASE+0x1A4) 77 #define EMI_MPUD18_ST (EMI_BASE+0x1A8) 78 #define EMI_MPUD19_ST (EMI_BASE+0x1AC) 79 #define EMI_MPUD20_ST (EMI_BASE+0x1B0) 80 #define EMI_MPUD21_ST (EMI_BASE+0x1B4) 81 #define EMI_MPUD22_ST (EMI_BASE+0x1B8) 82 #define EMI_MPUD23_ST (EMI_BASE+0x1BC) 83 #define EMI_MPUD24_ST (EMI_BASE+0x1C0) 84 #define EMI_MPUD25_ST (EMI_BASE+0x1C4) 85 #define EMI_MPUD26_ST (EMI_BASE+0x1C8) 86 #define EMI_MPUD27_ST (EMI_BASE+0x1CC) 87 #define EMI_MPUD28_ST (EMI_BASE+0x1D0) 88 #define EMI_MPUD29_ST (EMI_BASE+0x1D4) 89 #define EMI_MPUD30_ST (EMI_BASE+0x1D8) 90 #define EMI_MPUD31_ST (EMI_BASE+0x1DC) 91 #define EMI_MPUS (EMI_BASE+0x1F0) 92 #define EMI_MPUT (EMI_BASE+0x1F8) 93 #define EMI_MPUT_2ND (EMI_BASE+0x1FC) 94 #define EMI_D0_ST2 (EMI_BASE+0x200) 95 #define EMI_D1_ST2 (EMI_BASE+0x204) 96 #define EMI_D2_ST2 (EMI_BASE+0x208) 97 #define EMI_D3_ST2 (EMI_BASE+0x20C) 98 #define EMI_D4_ST2 (EMI_BASE+0x210) 99 #define EMI_D5_ST2 (EMI_BASE+0x214) 100 #define EMI_D6_ST2 (EMI_BASE+0x218) 101 #define EMI_D7_ST2 (EMI_BASE+0x21C) 102 #define EMI_D8_ST2 (EMI_BASE+0x220) 103 #define EMI_D9_ST2 (EMI_BASE+0x224) 104 #define EMI_D10_ST2 (EMI_BASE+0x228) 105 #define EMI_D11_ST2 (EMI_BASE+0x22C) 106 #define EMI_D12_ST2 (EMI_BASE+0x230) 107 #define EMI_D13_ST2 (EMI_BASE+0x234) 108 #define EMI_D14_ST2 (EMI_BASE+0x238) 109 #define EMI_D15_ST2 (EMI_BASE+0x23C) 110 #define EMI_D16_ST2 (EMI_BASE+0x240) 111 #define EMI_D17_ST2 (EMI_BASE+0x244) 112 #define EMI_D18_ST2 (EMI_BASE+0x248) 113 #define EMI_D19_ST2 (EMI_BASE+0x24C) 114 #define EMI_D20_ST2 (EMI_BASE+0x250) 115 #define EMI_D21_ST2 (EMI_BASE+0x254) 116 #define EMI_D22_ST2 (EMI_BASE+0x258) 117 #define EMI_D23_ST2 (EMI_BASE+0x25C) 118 #define EMI_D24_ST2 (EMI_BASE+0x260) 119 #define EMI_D25_ST2 (EMI_BASE+0x264) 120 #define EMI_D26_ST2 (EMI_BASE+0x268) 121 #define EMI_D27_ST2 (EMI_BASE+0x26C) 122 #define EMI_D28_ST2 (EMI_BASE+0x270) 123 #define EMI_D29_ST2 (EMI_BASE+0x274) 124 #define EMI_D30_ST2 (EMI_BASE+0x278) 125 #define EMI_D31_ST2 (EMI_BASE+0x27C) 126 #define EMI_BMEN (EMI_BASE+0x400) 127 #define EMI_BSTP (EMI_BASE+0x404) 128 #define EMI_BCNT (EMI_BASE+0x408) 129 #define EMI_TACT (EMI_BASE+0x410) 130 #define EMI_TSCT (EMI_BASE+0x418) 131 #define EMI_WACT (EMI_BASE+0x420) 132 #define EMI_WSCT (EMI_BASE+0x428) 133 #define EMI_BACT (EMI_BASE+0x430) 134 #define EMI_BSCT (EMI_BASE+0x438) 135 #define EMI_MSEL (EMI_BASE+0x440) 136 #define EMI_TSCT2 (EMI_BASE+0x448) 137 #define EMI_TSCT3 (EMI_BASE+0x450) 138 #define EMI_WSCT2 (EMI_BASE+0x458) 139 #define EMI_WSCT3 (EMI_BASE+0x460) 140 #define EMI_WSCT4 (EMI_BASE+0x464) 141 #define EMI_MSEL2 (EMI_BASE+0x468) 142 #define EMI_MSEL3 (EMI_BASE+0x470) 143 #define EMI_MSEL4 (EMI_BASE+0x478) 144 #define EMI_MSEL5 (EMI_BASE+0x480) 145 #define EMI_MSEL6 (EMI_BASE+0x488) 146 #define EMI_MSEL7 (EMI_BASE+0x490) 147 #define EMI_MSEL8 (EMI_BASE+0x498) 148 #define EMI_MSEL9 (EMI_BASE+0x4A0) 149 #define EMI_MSEL10 (EMI_BASE+0x4A8) 150 #define EMI_BMID0 (EMI_BASE+0x4B0) 151 #define EMI_BMID1 (EMI_BASE+0x4B4) 152 #define EMI_BMID2 (EMI_BASE+0x4B8) 153 #define EMI_BMID3 (EMI_BASE+0x4BC) 154 #define EMI_BMID4 (EMI_BASE+0x4C0) 155 #define EMI_BMID5 (EMI_BASE+0x4C4) 156 #define EMI_BMID6 (EMI_BASE+0x4C8) 157 #define EMI_BMID7 (EMI_BASE+0x4CC) 158 #define EMI_BMID8 (EMI_BASE+0x4D0) 159 #define EMI_BMID9 (EMI_BASE+0x4D4) 160 #define EMI_BMID10 (EMI_BASE+0x4D8) 161 #define EMI_BMEN1 (EMI_BASE+0x4E0) 162 #define EMI_BMEN2 (EMI_BASE+0x4E8) 163 #define EMI_BMRW0 (EMI_BASE+0x4F8) 164 #define EMI_BMRW1 (EMI_BASE+0x4FC) 165 #define EMI_TTYPE1 (EMI_BASE+0x500) 166 #define EMI_TTYPE2 (EMI_BASE+0x508) 167 #define EMI_TTYPE3 (EMI_BASE+0x510) 168 #define EMI_TTYPE4 (EMI_BASE+0x518) 169 #define EMI_TTYPE5 (EMI_BASE+0x520) 170 #define EMI_TTYPE6 (EMI_BASE+0x528) 171 #define EMI_TTYPE7 (EMI_BASE+0x530) 172 #define EMI_TTYPE8 (EMI_BASE+0x538) 173 #define EMI_TTYPE9 (EMI_BASE+0x540) 174 #define EMI_TTYPE10 (EMI_BASE+0x548) 175 #define EMI_TTYPE11 (EMI_BASE+0x550) 176 #define EMI_TTYPE12 (EMI_BASE+0x558) 177 #define EMI_TTYPE13 (EMI_BASE+0x560) 178 #define EMI_TTYPE14 (EMI_BASE+0x568) 179 #define EMI_TTYPE15 (EMI_BASE+0x570) 180 #define EMI_TTYPE16 (EMI_BASE+0x578) 181 #define EMI_TTYPE17 (EMI_BASE+0x580) 182 #define EMI_TTYPE18 (EMI_BASE+0x588) 183 #define EMI_TTYPE19 (EMI_BASE+0x590) 184 #define EMI_TTYPE20 (EMI_BASE+0x598) 185 #define EMI_TTYPE21 (EMI_BASE+0x5A0) 186 #define EMI_BWCT0 (EMI_BASE+0x5B0) 187 #define EMI_BWCT1 (EMI_BASE+0x5B4) 188 #define EMI_BWCT2 (EMI_BASE+0x5B8) 189 #define EMI_BWCT3 (EMI_BASE+0x5BC) 190 #define EMI_BWCT4 (EMI_BASE+0x5C0) 191 #define EMI_BWST0 (EMI_BASE+0x5C4) 192 #define EMI_BWST1 (EMI_BASE+0x5C8) 193 #define EMI_EX_CON (EMI_BASE+0x5D0) 194 #define EMI_EX_ST0 (EMI_BASE+0x5D4) 195 #define EMI_EX_ST1 (EMI_BASE+0x5D8) 196 #define EMI_EX_ST2 (EMI_BASE+0x5DC) 197 #define EMI_WP_ADR (EMI_BASE+0x5E0) 198 #define EMI_WP_ADR_2ND (EMI_BASE+0x5E4) 199 #define EMI_WP_CTRL (EMI_BASE+0x5E8) 200 #define EMI_CHKER (EMI_BASE+0x5F0) 201 #define EMI_CHKER_TYPE (EMI_BASE+0x5F4) 202 #define EMI_CHKER_ADR (EMI_BASE+0x5F8) 203 #define EMI_CHKER_ADR_2ND (EMI_BASE+0x5FC) 204 #define EMI_BWCT0_2ND (EMI_BASE+0x6A0) 205 #define EMI_LTCT0_2ND (EMI_BASE+0x750) 206 #define EMI_LTCT1_2ND (EMI_BASE+0x754) 207 #define EMI_LTCT2_2ND (EMI_BASE+0x758) 208 #define EMI_LTCT3_2ND (EMI_BASE+0x75C) 209 #define EMI_BWCT0_3RD (EMI_BASE+0x770) 210 #define EMI_BWCT0_4TH (EMI_BASE+0x780) 211 #define EMI_BWCT0_5TH (EMI_BASE+0x7B0) 212 #define EMI_BWCT0_6TH (EMI_BASE+0x7C8) 213 #define EMI_SNST (EMI_BASE+0x7F8) 214 #define EMI_SLVA (EMI_BASE+0x800) 215 #define EMI_AXI_BIST_ADR0 (EMI_BASE+0x98c) 216 #define EMI_AXI_BIST_ADR1 (EMI_BASE+0x990) 217 #define EMI_AXI_BIST_ADR2 (EMI_BASE+0x994) 218 219 #define EMI_MPU_CTRL (EMI_MPU_BASE+0x000) 220 #define EMI_MPU_DBG (EMI_MPU_BASE+0x004) 221 #define EMI_MPU_SA0 (EMI_MPU_BASE+0x100) 222 #define EMI_MPU_EA0 (EMI_MPU_BASE+0x200) 223 #define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region*4)) 224 #define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region*4)) 225 #define EMI_MPU_APC0 (EMI_MPU_BASE+0x300) 226 #define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region*4) + ((dgroup)*0x100)) 227 #define EMI_MPU_CTRL_D0 (EMI_MPU_BASE+0x800) 228 #define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain*4)) 229 #define EMI_RG_MASK_D0 (EMI_MPU_BASE+0x900) 230 #define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain*4)) 231 232 #define SUB_EMI_MPU_CTRL (SUB_EMI_MPU_BASE+0x000) 233 #define SUB_EMI_MPU_DBG (SUB_EMI_MPU_BASE+0x004) 234 #define SUB_EMI_MPU_SA0 (SUB_EMI_MPU_BASE+0x100) 235 #define SUB_EMI_MPU_EA0 (SUB_EMI_MPU_BASE+0x200) 236 #define SUB_EMI_MPU_SA(region) (SUB_EMI_MPU_SA0 + (region*4)) 237 #define SUB_EMI_MPU_EA(region) (SUB_EMI_MPU_EA0 + (region*4)) 238 #define SUB_EMI_MPU_APC0 (SUB_EMI_MPU_BASE+0x300) 239 #define SUB_EMI_MPU_APC(region, dgroup) (SUB_EMI_MPU_APC0 + (region*4) + ((dgroup)*0x100)) 240 #define SUB_EMI_MPU_CTRL_D0 (SUB_EMI_MPU_BASE+0x800) 241 #define SUB_EMI_MPU_CTRL_D(domain) (SUB_EMI_MPU_CTRL_D0 + (domain*4)) 242 #define SUB_EMI_RG_MASK_D0 (SUB_EMI_MPU_BASE+0x900) 243 #define SUB_EMI_RG_MASK_D(domain) (SUB_EMI_RG_MASK_D0 + (domain*4)) 244 245 #define CHN_EMI_CONA(base) (base + 0x000) 246 #define CHN_EMI_CONC(base) (base + 0x010) 247 248 #endif // __EMI_HW_H__ 249