1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
2 /*
3 * Copyright (c) 2007-2020 Broadcom. All Rights Reserved. The term
4 * "Broadcom" refers to Broadcom Inc. and/or its subsidiaries.
5 *
6 * Permission is hereby granted, free of charge, to any person
7 * obtaining a copy of this software and associated documentation
8 * files (the "Software"), to deal in the Software without
9 * restriction, including without limitation the rights to use, copy,
10 * modify, merge, publish, distribute, sublicense, and/or sell copies
11 * of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be
15 * included in all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
21 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
22 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
23 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * SOFTWARE.
25 *
26 */
27
28 /*
29 * svga3d_shaderdefs.h --
30 *
31 * SVGA3D byte code format and limit definitions.
32 */
33
34 #ifndef __SVGA3D_SHADER_DEFS__
35 #define __SVGA3D_SHADER_DEFS__
36
37 #include "svga3d_types.h"
38
39 #if defined __cplusplus
40 extern "C" {
41 #endif
42
43 #define SVGA3D_INPUTREG_MAX 16
44 #define SVGA3D_OUTPUTREG_MAX 12
45 #define SVGA3D_VERTEX_SAMPLERREG_MAX 4
46 #define SVGA3D_PIXEL_SAMPLERREG_MAX 16
47 #define SVGA3D_SAMPLERREG_MAX \
48 (SVGA3D_PIXEL_SAMPLERREG_MAX + SVGA3D_VERTEX_SAMPLERREG_MAX)
49 #define SVGA3D_TEMPREG_MAX 32
50 #define SVGA3D_ADDRREG_MAX 1
51 #define SVGA3D_PREDREG_MAX 1
52
53 #define SVGA3D_MAX_SRC_REGS 4
54 #define SVGA3D_MAX_NESTING_LEVEL 32
55
56 #define SVGA3D_VS_TYPE 0xFFFE
57 #define SVGA3D_PS_TYPE 0xFFFF
58
59 typedef struct {
60 union {
61 struct {
62 uint32 minor : 8;
63 uint32 major : 8;
64 uint32 type : 16;
65 };
66
67 uint32 value;
68 };
69 } SVGA3dShaderVersion;
70
71 #define SVGA3D_VS_10 ((uint32)((SVGA3D_VS_TYPE << 16) | 1 << 8))
72 #define SVGA3D_VS_11 ((uint32)(SVGA3D_VS_10 | 1))
73 #define SVGA3D_VS_20 ((uint32)((SVGA3D_VS_TYPE << 16) | 2 << 8))
74 #define SVGA3D_VS_21 ((uint32)(SVGA3D_VS_20 | 1))
75 #define SVGA3D_VS_30 ((uint32)((SVGA3D_VS_TYPE << 16) | 3 << 8))
76
77 #define SVGA3D_PS_10 ((uint32)((SVGA3D_PS_TYPE << 16) | 1 << 8))
78 #define SVGA3D_PS_11 ((uint32)(SVGA3D_PS_10 | 1))
79 #define SVGA3D_PS_12 ((uint32)(SVGA3D_PS_10 | 2))
80 #define SVGA3D_PS_13 ((uint32)(SVGA3D_PS_10 | 3))
81 #define SVGA3D_PS_14 ((uint32)(SVGA3D_PS_10 | 4))
82 #define SVGA3D_PS_20 ((uint32)((SVGA3D_PS_TYPE << 16) | 2 << 8))
83 #define SVGA3D_PS_21 ((uint32)(SVGA3D_PS_20 | 1))
84 #define SVGA3D_PS_30 ((uint32)((SVGA3D_PS_TYPE << 16) | 3 << 8))
85
86 typedef enum {
87 SVGA3DPSVERSION_NONE = 0,
88 SVGA3DPSVERSION_ENABLED = 1,
89 SVGA3DPSVERSION_11 = 3,
90 SVGA3DPSVERSION_12 = 5,
91 SVGA3DPSVERSION_13 = 7,
92 SVGA3DPSVERSION_14 = 9,
93 SVGA3DPSVERSION_20 = 11,
94 SVGA3DPSVERSION_30 = 13,
95 SVGA3DPSVERSION_40 = 15,
96 SVGA3DPSVERSION_MAX
97 } SVGA3dPixelShaderVersion;
98
99 typedef enum {
100 SVGA3DVSVERSION_NONE = 0,
101 SVGA3DVSVERSION_ENABLED = 1,
102 SVGA3DVSVERSION_11 = 3,
103 SVGA3DVSVERSION_20 = 5,
104 SVGA3DVSVERSION_30 = 7,
105 SVGA3DVSVERSION_40 = 9,
106 SVGA3DVSVERSION_MAX
107 } SVGA3dVertexShaderVersion;
108
109 typedef enum {
110 SVGA3DOP_NOP = 0,
111 SVGA3DOP_MOV = 1,
112 SVGA3DOP_ADD = 2,
113 SVGA3DOP_SUB = 3,
114 SVGA3DOP_MAD = 4,
115 SVGA3DOP_MUL = 5,
116 SVGA3DOP_RCP = 6,
117 SVGA3DOP_RSQ = 7,
118 SVGA3DOP_DP3 = 8,
119 SVGA3DOP_DP4 = 9,
120 SVGA3DOP_MIN = 10,
121 SVGA3DOP_MAX = 11,
122 SVGA3DOP_SLT = 12,
123 SVGA3DOP_SGE = 13,
124 SVGA3DOP_EXP = 14,
125 SVGA3DOP_LOG = 15,
126 SVGA3DOP_LIT = 16,
127 SVGA3DOP_DST = 17,
128 SVGA3DOP_LRP = 18,
129 SVGA3DOP_FRC = 19,
130 SVGA3DOP_M4x4 = 20,
131 SVGA3DOP_M4x3 = 21,
132 SVGA3DOP_M3x4 = 22,
133 SVGA3DOP_M3x3 = 23,
134 SVGA3DOP_M3x2 = 24,
135 SVGA3DOP_CALL = 25,
136 SVGA3DOP_CALLNZ = 26,
137 SVGA3DOP_LOOP = 27,
138 SVGA3DOP_RET = 28,
139 SVGA3DOP_ENDLOOP = 29,
140 SVGA3DOP_LABEL = 30,
141 SVGA3DOP_DCL = 31,
142 SVGA3DOP_POW = 32,
143 SVGA3DOP_CRS = 33,
144 SVGA3DOP_SGN = 34,
145 SVGA3DOP_ABS = 35,
146 SVGA3DOP_NRM = 36,
147 SVGA3DOP_SINCOS = 37,
148 SVGA3DOP_REP = 38,
149 SVGA3DOP_ENDREP = 39,
150 SVGA3DOP_IF = 40,
151 SVGA3DOP_IFC = 41,
152 SVGA3DOP_ELSE = 42,
153 SVGA3DOP_ENDIF = 43,
154 SVGA3DOP_BREAK = 44,
155 SVGA3DOP_BREAKC = 45,
156 SVGA3DOP_MOVA = 46,
157 SVGA3DOP_DEFB = 47,
158 SVGA3DOP_DEFI = 48,
159
160 SVGA3DOP_TEXCOORD = 64,
161 SVGA3DOP_TEXKILL = 65,
162 SVGA3DOP_TEX = 66,
163 SVGA3DOP_TEXBEM = 67,
164 SVGA3DOP_TEXBEML = 68,
165 SVGA3DOP_TEXREG2AR = 69,
166 SVGA3DOP_TEXREG2GB = 70,
167 SVGA3DOP_TEXM3x2PAD = 71,
168 SVGA3DOP_TEXM3x2TEX = 72,
169 SVGA3DOP_TEXM3x3PAD = 73,
170 SVGA3DOP_TEXM3x3TEX = 74,
171 SVGA3DOP_RESERVED0 = 75,
172 SVGA3DOP_TEXM3x3SPEC = 76,
173 SVGA3DOP_TEXM3x3VSPEC = 77,
174 SVGA3DOP_EXPP = 78,
175 SVGA3DOP_LOGP = 79,
176 SVGA3DOP_CND = 80,
177 SVGA3DOP_DEF = 81,
178 SVGA3DOP_TEXREG2RGB = 82,
179 SVGA3DOP_TEXDP3TEX = 83,
180 SVGA3DOP_TEXM3x2DEPTH = 84,
181 SVGA3DOP_TEXDP3 = 85,
182 SVGA3DOP_TEXM3x3 = 86,
183 SVGA3DOP_TEXDEPTH = 87,
184 SVGA3DOP_CMP = 88,
185 SVGA3DOP_BEM = 89,
186 SVGA3DOP_DP2ADD = 90,
187 SVGA3DOP_DSX = 91,
188 SVGA3DOP_DSY = 92,
189 SVGA3DOP_TEXLDD = 93,
190 SVGA3DOP_SETP = 94,
191 SVGA3DOP_TEXLDL = 95,
192 SVGA3DOP_BREAKP = 96,
193 SVGA3DOP_LAST_INST,
194 SVGA3DOP_PHASE = 0xFFFD,
195 SVGA3DOP_COMMENT = 0xFFFE,
196 SVGA3DOP_END = 0xFFFF,
197 } SVGA3dShaderOpCodeType;
198
199 typedef enum {
200 SVGA3DOPCONT_NONE,
201 SVGA3DOPCONT_PROJECT,
202 SVGA3DOPCONT_BIAS,
203 } SVGA3dShaderOpCodeControlFnType;
204
205 typedef enum {
206 SVGA3DOPCOMP_RESERVED0 = 0,
207 SVGA3DOPCOMP_GT,
208 SVGA3DOPCOMP_EQ,
209 SVGA3DOPCOMP_GE,
210 SVGA3DOPCOMP_LT,
211 SVGA3DOPCOMP_NE,
212 SVGA3DOPCOMP_LE,
213 SVGA3DOPCOMP_RESERVED1
214 } SVGA3dShaderOpCodeCompFnType;
215
216 typedef enum {
217 SVGA3DREG_TEMP = 0,
218 SVGA3DREG_INPUT,
219 SVGA3DREG_CONST,
220 SVGA3DREG_ADDR,
221 SVGA3DREG_TEXTURE = 3,
222 SVGA3DREG_RASTOUT,
223 SVGA3DREG_ATTROUT,
224 SVGA3DREG_TEXCRDOUT,
225 SVGA3DREG_OUTPUT = 6,
226 SVGA3DREG_CONSTINT,
227 SVGA3DREG_COLOROUT,
228 SVGA3DREG_DEPTHOUT,
229 SVGA3DREG_SAMPLER,
230 SVGA3DREG_CONST2,
231 SVGA3DREG_CONST3,
232 SVGA3DREG_CONST4,
233 SVGA3DREG_CONSTBOOL,
234 SVGA3DREG_LOOP,
235 SVGA3DREG_TEMPFLOAT16,
236 SVGA3DREG_MISCTYPE,
237 SVGA3DREG_LABEL,
238 SVGA3DREG_PREDICATE,
239 } SVGA3dShaderRegType;
240
241 typedef enum {
242 SVGA3DRASTOUT_POSITION = 0,
243 SVGA3DRASTOUT_FOG,
244 SVGA3DRASTOUT_PSIZE
245 } SVGA3dShaderRastOutRegType;
246
247 typedef enum {
248 SVGA3DMISCREG_POSITION = 0,
249 SVGA3DMISCREG_FACE
250 } SVGA3DShaderMiscRegType;
251
252 typedef enum {
253 SVGA3DSAMP_UNKNOWN = 0,
254 SVGA3DSAMP_2D = 2,
255 SVGA3DSAMP_CUBE,
256 SVGA3DSAMP_VOLUME,
257 SVGA3DSAMP_2D_SHADOW,
258 SVGA3DSAMP_MAX,
259 } SVGA3dShaderSamplerType;
260
261 #define SVGA3DWRITEMASK_0 1
262 #define SVGA3DWRITEMASK_1 2
263 #define SVGA3DWRITEMASK_2 4
264 #define SVGA3DWRITEMASK_3 8
265 #define SVGA3DWRITEMASK_ALL 15
266
267 #define SVGA3DDSTMOD_NONE 0
268 #define SVGA3DDSTMOD_SATURATE 1
269 #define SVGA3DDSTMOD_PARTIALPRECISION 2
270
271 #define SVGA3DDSTMOD_MSAMPCENTROID 4
272
273 typedef enum {
274 SVGA3DDSTSHFSCALE_X1 = 0,
275 SVGA3DDSTSHFSCALE_X2 = 1,
276 SVGA3DDSTSHFSCALE_X4 = 2,
277 SVGA3DDSTSHFSCALE_X8 = 3,
278 SVGA3DDSTSHFSCALE_D8 = 13,
279 SVGA3DDSTSHFSCALE_D4 = 14,
280 SVGA3DDSTSHFSCALE_D2 = 15
281 } SVGA3dShaderDstShfScaleType;
282
283 #define SVGA3DSWIZZLE_REPLICATEX 0x00
284 #define SVGA3DSWIZZLE_REPLICATEY 0x55
285 #define SVGA3DSWIZZLE_REPLICATEZ 0xAA
286 #define SVGA3DSWIZZLE_REPLICATEW 0xFF
287 #define SVGA3DSWIZZLE_NONE 0xE4
288 #define SVGA3DSWIZZLE_YZXW 0xC9
289 #define SVGA3DSWIZZLE_ZXYW 0xD2
290 #define SVGA3DSWIZZLE_WXYZ 0x1B
291
292 typedef enum {
293 SVGA3DSRCMOD_NONE = 0,
294 SVGA3DSRCMOD_NEG,
295 SVGA3DSRCMOD_BIAS,
296 SVGA3DSRCMOD_BIASNEG,
297 SVGA3DSRCMOD_SIGN,
298 SVGA3DSRCMOD_SIGNNEG,
299 SVGA3DSRCMOD_COMP,
300 SVGA3DSRCMOD_X2,
301 SVGA3DSRCMOD_X2NEG,
302 SVGA3DSRCMOD_DZ,
303 SVGA3DSRCMOD_DW,
304 SVGA3DSRCMOD_ABS,
305 SVGA3DSRCMOD_ABSNEG,
306 SVGA3DSRCMOD_NOT,
307 } SVGA3dShaderSrcModType;
308
309 typedef struct {
310 union {
311 struct {
312 uint32 comment_op : 16;
313 uint32 comment_size : 16;
314 };
315
316 struct {
317 uint32 op : 16;
318 uint32 control : 3;
319 uint32 reserved2 : 5;
320 uint32 size : 4;
321 uint32 predicated : 1;
322 uint32 reserved1 : 1;
323 uint32 coissue : 1;
324 uint32 reserved0 : 1;
325 };
326
327 uint32 value;
328 };
329 } SVGA3dShaderInstToken;
330
331 typedef struct {
332 union {
333 struct {
334 uint32 num : 11;
335 uint32 type_upper : 2;
336 uint32 relAddr : 1;
337 uint32 reserved1 : 2;
338 uint32 mask : 4;
339 uint32 dstMod : 4;
340 uint32 shfScale : 4;
341 uint32 type_lower : 3;
342 uint32 reserved0 : 1;
343 };
344
345 uint32 value;
346 };
347 } SVGA3dShaderDestToken;
348
349 typedef struct {
350 union {
351 struct {
352 uint32 num : 11;
353 uint32 type_upper : 2;
354 uint32 relAddr : 1;
355 uint32 reserved1 : 2;
356 uint32 swizzle : 8;
357 uint32 srcMod : 4;
358 uint32 type_lower : 3;
359 uint32 reserved0 : 1;
360 };
361
362 uint32 value;
363 };
364 } SVGA3dShaderSrcToken;
365
366 typedef struct {
367 union {
368 struct {
369 union {
370 struct {
371 uint32 usage : 5;
372 uint32 reserved1 : 11;
373 uint32 index : 4;
374 uint32 reserved0 : 12;
375 };
376
377 struct {
378 uint32 reserved3 : 27;
379 uint32 type : 4;
380 uint32 reserved2 : 1;
381 };
382 };
383
384 SVGA3dShaderDestToken dst;
385 };
386
387 uint32 values[2];
388 };
389 } SVGA3DOpDclArgs;
390
391 typedef struct {
392 union {
393 struct {
394 SVGA3dShaderDestToken dst;
395
396 union {
397 float constValues[4];
398 int constIValues[4];
399 Bool constBValue;
400 };
401 };
402
403 uint32 values[5];
404 };
405 } SVGA3DOpDefArgs;
406
407 typedef union {
408 uint32 value;
409 SVGA3dShaderInstToken inst;
410 SVGA3dShaderDestToken dest;
411 SVGA3dShaderSrcToken src;
412 } SVGA3dShaderToken;
413
414 typedef struct {
415 SVGA3dShaderVersion version;
416
417 } SVGA3dShaderProgram;
418
419 static const uint32 SVGA3D_INPUT_REG_POSITION_VS11 = 0;
420 static const uint32 SVGA3D_INPUT_REG_PSIZE_VS11 = 1;
421 static const uint32 SVGA3D_INPUT_REG_FOG_VS11 = 3;
422 static const uint32 SVGA3D_INPUT_REG_FOG_MASK_VS11 = SVGA3DWRITEMASK_3;
423 static const uint32 SVGA3D_INPUT_REG_COLOR_BASE_VS11 = 2;
424 static const uint32 SVGA3D_INPUT_REG_TEXCOORD_BASE_VS11 = 4;
425
426 static const uint32 SVGA3D_INPUT_REG_COLOR_BASE_PS11 = 0;
427 static const uint32 SVGA3D_INPUT_REG_TEXCOORD_BASE_PS11 = 2;
428 static const uint32 SVGA3D_OUTPUT_REG_DEPTH_PS11 = 0;
429 static const uint32 SVGA3D_OUTPUT_REG_COLOR_PS11 = 1;
430
431 static const uint32 SVGA3D_INPUT_REG_COLOR_BASE_PS20 = 0;
432 static const uint32 SVGA3D_INPUT_REG_COLOR_NUM_PS20 = 2;
433 static const uint32 SVGA3D_INPUT_REG_TEXCOORD_BASE_PS20 = 2;
434 static const uint32 SVGA3D_INPUT_REG_TEXCOORD_NUM_PS20 = 8;
435 static const uint32 SVGA3D_OUTPUT_REG_COLOR_BASE_PS20 = 1;
436 static const uint32 SVGA3D_OUTPUT_REG_COLOR_NUM_PS20 = 4;
437 static const uint32 SVGA3D_OUTPUT_REG_DEPTH_BASE_PS20 = 0;
438 static const uint32 SVGA3D_OUTPUT_REG_DEPTH_NUM_PS20 = 1;
439
440 static INLINE SVGA3dShaderRegType
SVGA3dShaderGetRegType(uint32 token)441 SVGA3dShaderGetRegType(uint32 token)
442 {
443 SVGA3dShaderSrcToken src;
444 src.value = token;
445 return (SVGA3dShaderRegType)(src.type_upper << 3 | src.type_lower);
446 }
447
448 #if defined __cplusplus
449 }
450 #endif
451
452 #endif
453