1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _SOC_RAMSTAGE_H_ 4 #define _SOC_RAMSTAGE_H_ 5 6 #include <device/device.h> 7 #include <fsp/ramstage.h> 8 9 #include "../../chip.h" 10 11 #define V_PCH_LPC_RID_A0 0x00 // A0 Stepping 12 #define V_PCH_LPC_RID_A1 0x04 // A1 Stepping 13 #define V_PCH_LPC_RID_A2 0x08 // A2 Stepping 14 #define V_PCH_LPC_RID_A3 0x0C // A3 Stepping 15 #define V_PCH_LPC_RID_A4 0x80 // A4 Stepping 16 #define V_PCH_LPC_RID_A5 0x84 // A5 Stepping 17 #define V_PCH_LPC_RID_A6 0x88 // A6 Stepping 18 #define V_PCH_LPC_RID_A7 0x8C // A7 Stepping 19 #define V_PCH_LPC_RID_B0 0x10 // B0 Stepping 20 #define V_PCH_LPC_RID_B1 0x14 // B1 Stepping 21 #define V_PCH_LPC_RID_B2 0x18 // B2 Stepping 22 #define V_PCH_LPC_RID_B3 0x1C // B3 Stepping 23 #define V_PCH_LPC_RID_B4 0x90 // B4 Stepping 24 #define V_PCH_LPC_RID_B5 0x94 // B5 Stepping 25 #define V_PCH_LPC_RID_B6 0x98 // B6 Stepping 26 #define V_PCH_LPC_RID_B7 0x9C // B7 Stepping 27 #define V_PCH_LPC_RID_C0 0x20 // C0 Stepping 28 #define V_PCH_LPC_RID_C1 0x24 // C1 Stepping 29 #define V_PCH_LPC_RID_C2 0x28 // C2 Stepping 30 #define V_PCH_LPC_RID_C3 0x2C // C3 Stepping 31 #define V_PCH_LPC_RID_C4 0xA0 // C4 Stepping 32 #define V_PCH_LPC_RID_C5 0xA4 // C5 Stepping 33 #define V_PCH_LPC_RID_C6 0xA8 // C6 Stepping 34 #define V_PCH_LPC_RID_C7 0xAC // C7 Stepping 35 #define V_PCH_LPC_RID_D0 0x30 // D0 Stepping 36 #define V_PCH_LPC_RID_D1 0x34 // D1 Stepping 37 #define V_PCH_LPC_RID_D2 0x38 // D2 Stepping 38 #define V_PCH_LPC_RID_D3 0x3C // D3 Stepping 39 #define V_PCH_LPC_RID_D4 0xB0 // D4 Stepping 40 #define V_PCH_LPC_RID_D5 0xB4 // D5 Stepping 41 #define V_PCH_LPC_RID_D6 0xB8 // D6 Stepping 42 #define V_PCH_LPC_RID_D7 0xBC // D7 Stepping 43 #define B_PCH_LPC_RID_STEPPING_MASK 0xFC // SoC Stepping Mask (Ignoring Package Type) 44 45 enum { 46 SocA0 = 0, 47 SocA1 = 1, 48 SocA2 = 2, 49 SocA3 = 3, 50 SocA4 = 4, 51 SocA5 = 5, 52 SocA6 = 6, 53 SocA7 = 7, 54 SocB0 = 8, 55 SocB1 = 9, 56 SocB2 = 10, 57 SocB3 = 11, 58 SocB4 = 12, 59 SocB5 = 13, 60 SocB6 = 14, 61 SocB7 = 15, 62 SocC0 = 16, 63 SocC1 = 17, 64 SocC2 = 18, 65 SocC3 = 19, 66 SocC4 = 20, 67 SocC5 = 21, 68 SocC6 = 22, 69 SocC7 = 23, 70 SocD0 = 24, 71 SocD1 = 25, 72 SocD2 = 26, 73 SocD3 = 27, 74 SocD4 = 28, 75 SocD5 = 29, 76 SocD6 = 30, 77 SocD7 = 31, 78 SocSteppingMax 79 }; 80 81 /* 82 * The soc_init_pre_device() function is called prior to device 83 * initialization, but it's after console and cbmem has been reinitialized. 84 */ 85 void soc_init_pre_device(struct soc_intel_braswell_config *config); 86 void southcluster_enable_dev(struct device *dev); 87 void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index); 88 int SocStepping(void); 89 void board_silicon_USB2_override(SILICON_INIT_UPD *params); 90 91 extern struct pci_operations soc_pci_ops; 92 93 #endif /* _SOC_RAMSTAGE_H_ */ 94