| /external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/XRay/ |
| D | FDRTraceExpander.h | 27 int32_t TID = 0; variable
|
| D | FDRRecords.h | 337 int32_t TID = 0; variable
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/XRay/ |
| D | FDRTraceExpander.h | 27 int32_t TID = 0; variable
|
| D | FDRRecords.h | 337 int32_t TID = 0; variable
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 435 const MCInstrDesc &TID = TII->get(N->getMachineOpcode()); in SUSchedulingCost() local
537 const MCInstrDesc &TID = TII->get(N->getMachineOpcode()); in initNumRegDefsLeft() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 436 const MCInstrDesc &TID = TII->get(N->getMachineOpcode()); in SUSchedulingCost() local
538 const MCInstrDesc &TID = TII->get(N->getMachineOpcode()); in initNumRegDefsLeft() local
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 448 const MCInstrDesc &TID = TII->get(N->getMachineOpcode()); in SUSchedulingCost() local
551 const MCInstrDesc &TID = TII->get(N->getMachineOpcode()); in initNumRegDefsLeft() local
|
| /external/swiftshader/third_party/llvm-subzero/include/llvm/IR/ |
| D | DerivedTypes.h | 324 SequentialType(TypeID TID, Type *ElType, uint64_t NumElements) in SequentialType()
|
| /external/llvm/include/llvm/IR/ |
| D | DerivedTypes.h | 320 SequentialType(TypeID TID, Type *ElType) in SequentialType()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/XRay/ |
| D | Profile.cpp | 389 const auto &TID = ThreadPaths.first; in profileFromTrace() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/XRay/ |
| D | Profile.cpp | 389 const auto &TID = ThreadPaths.first; in profileFromTrace() local
|
| /external/llvm/lib/CodeGen/ |
| D | TargetPassConfig.cpp | 570 const char *TID = (const char *)(TPI->getTypeInfo()); in addMachinePasses() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | DerivedTypes.h | 385 SequentialType(TypeID TID, Type *ElType, uint64_t NumElements) in SequentialType()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUPromoteAlloca.cpp | 818 Value *TID = Builder.CreateAdd(Tmp0, Tmp1); in handleAlloca() local
|
| D | SIInstrInfo.h | 1030 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum, in getRegClass()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUPromoteAlloca.cpp | 712 Value *TID = Builder.CreateAdd(Tmp0, Tmp1); in handleAlloca() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetPassConfig.cpp | 883 const char *TID = (const char *)(TPI->getTypeInfo()); in addMachinePasses() local
|
| /external/scapy/scapy/layers/ |
| D | smbclient.py | 690 def set_TID(self, TID): argument
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/IR/ |
| D | Type.cpp | 663 VectorType::VectorType(Type *ElType, unsigned EQ, Type::TypeID TID) in VectorType()
|
| D | AsmWriter.cpp | 1087 for (const auto &TID : TheIndex->typeIds()) in processIndex() local
2926 for (const auto &TID : TheIndex->typeIds()) { in printModuleSummaryIndex() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUPromoteAlloca.cpp | 1021 Value *TID = Builder.CreateAdd(Tmp0, Tmp1); in handleAlloca() local
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonVLIWPacketizer.cpp | 937 const MCInstrDesc& TID = MI.getDesc(); in ignorePseudoInstruction() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| D | HexagonVLIWPacketizer.cpp | 1060 const MCInstrDesc& TID = MI.getDesc(); in ignorePseudoInstruction() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonVLIWPacketizer.cpp | 1053 const MCInstrDesc& TID = MI.getDesc(); in ignorePseudoInstruction() local
|
| /external/bcc/src/python/bcc/ |
| D | __init__.py | 149 TID = (1 << 1) variable in PerfEventSampleFormat
|