1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ 4 #define __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ 5 6 #define MAX_DRAM_ADDRESS 0xFE000000 7 8 #define SDMMC1_BASE 0xFF0C0000 9 #define SDMMC0_BASE 0xFF0D0000 10 #define EMMC_BASE 0xFF0F0000 11 #define SARADC_BASE 0xFF100000 12 13 #define SPI0_BASE 0xFF110000 14 #define SPI1_BASE 0xFF120000 15 #define SPI2_BASE 0xFF130000 16 17 #define I2C1_BASE 0xFF140000 18 #define I2C3_BASE 0xFF150000 19 #define I2C4_BASE 0xFF160000 20 #define I2C5_BASE 0xFF170000 21 #define UART0_BASE 0xFF180000 22 #define UART1_BASE 0xFF190000 23 #define DMAC_PERI_BASE 0xFF250000 24 #define TSADC_BASE 0xFF280000 25 26 #define NANDC0_BASE 0xFF400000 27 #define NANDC1_BASE 0xFF410000 28 29 #define USB_HOST0_EHCI_BASE 0xFF500000 30 #define USB_HOST0_OHCI_BASE 0xFF520000 31 #define USB_HOST1_BASE 0xFF540000 32 #define USB_OTG_BASE 0xFF580000 33 34 #define DMAC_BUS_BASE 0xFF600000 35 36 #define DDR_PCTL0_BASE 0xFF610000 37 #define DDR_PCTL1_BASE 0xFF630000 38 #define DDR_PUBL0_BASE 0xFF620000 39 #define DDR_PUBL1_BASE 0xFF640000 40 41 #define I2C0_BASE 0xFF650000 42 #define I2C2_BASE 0xFF660000 43 #define DW_PWM0123_BASE 0xFF670000 44 #define RK_PWM_BASE 0xFF680000 45 #define UART2_BASE 0xFF690000 46 #define TIMER0_BASE 0xFF6B0000 47 48 #define SRAM_BASE 0xFF700000 49 #define PMU_BASE 0xFF730000 50 #define GRF_SECURE_BASE 0xFF740000 51 #define GPIO0_BASE 0xFF750000 52 #define CRU_BASE 0xFF760000 53 #define GRF_BASE 0xFF770000 54 #define GPIO1_BASE 0xFF780000 55 #define GPIO2_BASE 0xFF790000 56 #define GPIO3_BASE 0xFF7A0000 57 #define GPIO4_BASE 0xFF7B0000 58 #define GPIO5_BASE 0xFF7C0000 59 #define GPIO6_BASE 0xFF7D0000 60 #define GPIO7_BASE 0xFF7E0000 61 #define GPIO8_BASE 0xFF7F0000 62 63 #define TIMER6_BASE 0xFF810000 64 #define TIMER7_BASE 0xFF810020 65 66 #define CRYPTO_BASE 0xFF8A0000 67 68 #define VOP_BIG_BASE 0xFF930000 69 #define VOP_LIT_BASE 0xFF940000 70 #define EDP_BASE 0xFF970000 71 72 #define HDMI_TX_BASE 0xFF980000 73 74 #define SERVICE_CORE_BASE 0xFFA80000 75 #define SERVICE_DMA_BASE 0xFFA90000 76 #define SERVICE_GPU_BASE 0xFFAA0000 77 #define SERVICE_PERI_BASE 0xFFAB0000 78 #define SERVICE_BUS_BASE 0xFFAC0000 79 #define SERVICE_VIO_BASE 0xFFAD0000 80 #define SERVICE_VPU_BASE 0xFFAE0000 81 #define SERVICE_HEVC_BASE 0xFFAF0000 82 83 #define EFUSE_BASE 0xFFB40000 84 85 #define CORE_GICD_BASE 0xFFC01000 86 #define CORE_GICC_BASE 0xFFC02000 87 #define CPU_AXI_BUS_BASE 0xFFE00000 88 89 #define BOOT_ROM_BASE 0xFFFF0000 90 #define BOOT_ROM_CHIP_VER (BOOT_ROM+0x27F0) 91 #define IC_BASES { I2C0_BASE, I2C1_BASE, I2C2_BASE, \ 92 I2C3_BASE, I2C4_BASE, I2C5_BASE } 93 94 #endif /* __SOC_ROCKCHIP_RK3288_ADDRESSMAP_H__ */ 95