1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #ifndef CR50_TSS_STRUCTURES_H_ 3 #define CR50_TSS_STRUCTURES_H_ 4 5 #include <stdint.h> 6 #include <security/tpm/tss_errors.h> 7 8 /* FIXME: below is not enough to differentiate between vendors commands 9 of numerous devices. However, the current tpm2 APIs aren't very amenable 10 to extending generically because the marshaling code is assuming all 11 knowledge of all commands. */ 12 #define TPM2_CR50_VENDOR_COMMAND ((TPM_CC)(TPM_CC_VENDOR_BIT_MASK | 0)) 13 #define TPM2_CR50_SUB_CMD_IMMEDIATE_RESET (19) 14 #define TPM2_CR50_SUB_CMD_NVMEM_ENABLE_COMMITS (21) 15 #define TPM2_CR50_SUB_CMD_TURN_UPDATE_ON (24) 16 #define TPM2_CR50_SUB_CMD_GET_REC_BTN (29) 17 #define TPM2_CR50_SUB_CMD_TPM_MODE (40) 18 #define TPM2_CR50_SUB_CMD_GET_BOOT_MODE (52) 19 #define TPM2_CR50_SUB_CMD_RESET_EC (53) 20 #define TPM2_CR50_SUB_CMD_GET_FACTORY_CONFIG (68) 21 22 /* Cr50 vendor-specific error codes. */ 23 #define VENDOR_RC_ERR 0x00000500 24 enum cr50_vendor_rc { 25 VENDOR_RC_INTERNAL_ERROR = (VENDOR_RC_ERR | 6), 26 VENDOR_RC_NO_SUCH_SUBCOMMAND = (VENDOR_RC_ERR | 8), 27 VENDOR_RC_NO_SUCH_COMMAND = (VENDOR_RC_ERR | 127), 28 }; 29 30 enum cr50_tpm_mode { 31 /* 32 * Default state: TPM is enabled, and may be set to either 33 * TPM_MODE_ENABLED or TPM_MODE_DISABLED. 34 */ 35 TPM_MODE_ENABLED_TENTATIVE = 0, 36 37 /* TPM is enabled, and mode may not be changed. */ 38 TPM_MODE_ENABLED = 1, 39 40 /* TPM is disabled, and mode may not be changed. */ 41 TPM_MODE_DISABLED = 2, 42 43 TPM_MODE_INVALID, 44 }; 45 46 /** 47 * CR50 specific tpm command to enable nvmem commits before internal timeout 48 * expires. 49 */ 50 tpm_result_t tlcl_cr50_enable_nvcommits(void); 51 52 /** 53 * CR50 specific tpm command to restore header(s) of the dormant RO/RW 54 * image(s) and in case there indeed was a dormant image, trigger reboot after 55 * the timeout milliseconds. Note that timeout of zero means "NO REBOOT", not 56 * "IMMEDIATE REBOOT". 57 * 58 * Return value indicates success or failure of accessing the TPM; in case of 59 * success the number of restored headers is saved in num_restored_headers. 60 */ 61 tpm_result_t tlcl_cr50_enable_update(uint16_t timeout_ms, 62 uint8_t *num_restored_headers); 63 64 /** 65 * CR50 specific tpm command to get the latched state of the recovery button. 66 * 67 * Return value indicates success or failure of accessing the TPM; in case of 68 * success the recovery button state is saved in recovery_button_state. 69 */ 70 tpm_result_t tlcl_cr50_get_recovery_button(uint8_t *recovery_button_state); 71 72 /** 73 * CR50 specific TPM command sequence to query the current TPM mode. 74 * 75 * Returns TPM_SUCCESS if TPM mode command completed, the Cr50 does not need a 76 * reboot, and the tpm_mode parameter is set to the current TPM mode. 77 * Returns TPM_CB_MUST_REBOOT if TPM mode command completed, but the Cr50 78 * requires a reboot. 79 * Returns TPM_CB_NO_SUCH_COMMAND if the Cr50 does not support the command. 80 * Other returns value indicate a failure accessing the TPM. 81 */ 82 tpm_result_t tlcl_cr50_get_tpm_mode(uint8_t *tpm_mode); 83 84 /** 85 * CR50 specific TPM command sequence to query the current boot mode. 86 * 87 * Returns TPM_SUCCESS if boot mode is successfully retrieved. 88 * Returns TPM_* for errors. 89 */ 90 tpm_result_t tlcl_cr50_get_boot_mode(uint8_t *boot_mode); 91 92 /** 93 * CR50 specific TPM command sequence to trigger an immediate reset to the Cr50 94 * device after the specified timeout in milliseconds. A timeout of zero means 95 * "IMMEDIATE REBOOT". 96 * 97 * Return value indicates success or failure of accessing the TPM. 98 */ 99 tpm_result_t tlcl_cr50_immediate_reset(uint16_t timeout_ms); 100 101 /** 102 * CR50 specific TPM command sequence to issue an EC reset. 103 * 104 * Returns TPM_* for errors. 105 * On Success, this function invokes halt() and does not return. 106 */ 107 tpm_result_t tlcl_cr50_reset_ec(void); 108 109 /** 110 * TPM command to get the factory config. 111 * 112 * Returns TPM_* for errors. 113 * On Success, TPM_SUCCESS if factory config is successfully retrieved. 114 */ 115 tpm_result_t tlcl_cr50_get_factory_config(uint64_t *factory_config); 116 117 #endif /* CR50_TSS_STRUCTURES_H_ */ 118