| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/ |
| D | RISCVRedundantCopyElimination.cpp | 108 Register TargetReg = Cond[1].getReg(); in optimizeBlock() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RedundantCopyElimination.cpp | 105 unsigned TargetReg = CompBr->getOperand(0).getReg(); in optimizeCopy() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 186 unsigned TargetReg = Inst.getOperand(1).getReg(); in emitInstruction() local
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 178 unsigned TargetReg = Inst.getOperand(1).getReg(); in EmitInstruction() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 186 unsigned TargetReg = Inst.getOperand(1).getReg(); in EmitInstruction() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86SpeculativeLoadHardening.cpp | 987 unsigned TargetReg; in tracePredStateThroughIndirectBranches() local
1105 Register TargetReg = MRI->createVirtualRegister(&X86::GR64RegClass); in tracePredStateThroughIndirectBranches() local
1138 unsigned TargetReg = TargetAddrSSA.GetValueInMiddleOfBlock(&MBB); in tracePredStateThroughIndirectBranches() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| D | X86SpeculativeLoadHardening.cpp | 992 unsigned TargetReg; in tracePredStateThroughIndirectBranches() local
1110 Register TargetReg = MRI->createVirtualRegister(&X86::GR64RegClass); in tracePredStateThroughIndirectBranches() local
1143 Register TargetReg = TargetAddrSSA.GetValueInMiddleOfBlock(&MBB); in tracePredStateThroughIndirectBranches() local
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| D | X86ExpandPseudo.cpp | 229 auto TargetReg = STI->getTargetTriple().isOSWindows() ? X86::RCX : X86::RDI; in expandCALL_RVMARKER() local
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 716 unsigned TargetReg = I->getOperand(1).getReg(); in expandEhReturn() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 882 Register TargetReg = I->getOperand(1).getReg(); in expandEhReturn() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 896 Register TargetReg = I->getOperand(1).getReg(); in expandEhReturn() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 2101 Register TargetReg = MI.getOperand(0).getReg(); in expandVSXMemPseudo() local
2163 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
2185 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 3074 Register TargetReg = MI.getOperand(0).getReg(); in expandVSXMemPseudo() local
3161 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
3183 Register TargetReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| D | SIFrameLowering.cpp | 169 Register TargetReg) { in buildGitPtr()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 2436 Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectBrJT() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/GISel/ |
| D | AArch64InstructionSelector.cpp | 3635 Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in selectBrJT() local
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringX8664.cpp | 7139 RegNumT TargetReg = {}; in emitCallToTarget() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 2841 Register TargetReg, Register InsertReg, in buildBitFieldInsert()
|