1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOUTHBRIDGE_INTEL_IBEXPEAK_PCH_H 4 #define SOUTHBRIDGE_INTEL_IBEXPEAK_PCH_H 5 6 #include <acpi/acpi.h> 7 #include <southbridge/intel/common/rcba.h> /* IWYU pragma: export */ 8 9 /* PCH types */ 10 #define PCH_TYPE_CPT 0x1c /* CougarPoint */ 11 #define PCH_TYPE_PPT 0x1e /* IvyBridge */ 12 #define PCH_TYPE_MOBILE5 0x3b 13 14 /* PCH stepping values for LPC device */ 15 #define PCH_STEP_A0 0 16 #define PCH_STEP_A1 1 17 #define PCH_STEP_B0 2 18 #define PCH_STEP_B1 3 19 #define PCH_STEP_B2 4 20 #define PCH_STEP_B3 5 21 22 #define SMBUS_SLAVE_ADDR 0x24 23 /* TODO Make sure these don't get changed by stage2 */ 24 #define DEFAULT_GPIOBASE 0x0480 25 #define DEFAULT_PMBASE 0x0500 26 #define DEFAULT_HECIBAR ((u8 *)0xfed17000) 27 28 #ifndef __ACPI__ 29 30 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); 31 void enable_usb_bar(void); 32 33 void ibexpeak_setup_bars(void); 34 void early_pch_init(void); 35 36 void early_thermal_init(void); 37 void southbridge_configure_default_intmap(void); 38 void pch_setup_cir(int chipset_type); 39 40 enum current_lookup_idx { 41 IF1_F57 = 0, 42 IF1_F5F, 43 IF1_753, 44 IF1_75F, 45 IF1_14B, 46 IF1_74B, 47 IF1_557, 48 IF1_757, 49 IF1_55F, 50 IF1_54B, 51 }; 52 53 struct southbridge_usb_port { 54 int enabled; 55 enum current_lookup_idx current; 56 int oc_pin; 57 }; 58 59 void early_usb_init(const struct southbridge_usb_port *portmap); 60 61 extern const struct southbridge_usb_port mainboard_usb_ports[14]; 62 #include <device/device.h> 63 void pch_enable(struct device *dev); 64 65 #define MAINBOARD_POWER_OFF 0 66 #define MAINBOARD_POWER_ON 1 67 #define MAINBOARD_POWER_KEEP 2 68 69 /* PCI Configuration Space (D30:F0): PCI2PCI */ 70 #define PSTS 0x06 71 #define SMLT 0x1b 72 #define SECSTS 0x1e 73 #define INTR 0x3c 74 75 #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) 76 #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) 77 #define PCH_XHCI_DEV PCI_DEV(0, 0x14, 0) 78 #define PCH_ME_DEV PCI_DEV(0, 0x16, 0) 79 #define PCH_PCIE_DEV_SLOT 28 80 81 /* PCI Configuration Space (D31:F0): LPC */ 82 #define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0) 83 #define SERIRQ_CNTL 0x64 84 85 #define GEN_PMCON_1 0xa0 86 #define GEN_PMCON_2 0xa2 87 #define GEN_PMCON_3 0xa4 88 #define ETR3 0xac 89 #define ETR3_CWORWRE (1 << 18) 90 #define ETR3_CF9GR (1 << 20) 91 92 #define CIR4 0xa9 93 #define PMIR 0xac 94 95 /* GEN_PMCON_3 bits */ 96 #define RTC_BATTERY_DEAD (1 << 2) 97 #define RTC_POWER_FAILED (1 << 1) 98 #define SLEEP_AFTER_POWER_FAIL (1 << 0) 99 100 #define PMBASE 0x40 101 #define ACPI_CNTL 0x44 102 #define ACPI_EN (1 << 7) 103 #define BIOS_CNTL 0xDC 104 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ 105 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ 106 107 #define GPIO_ROUT 0xb8 108 #define GPI_DISABLE 0x00 109 #define GPI_IS_SMI 0x01 110 #define GPI_IS_SCI 0x02 111 #define GPI_IS_NMI 0x03 112 113 #define PIRQA_ROUT 0x60 114 #define PIRQB_ROUT 0x61 115 #define PIRQC_ROUT 0x62 116 #define PIRQD_ROUT 0x63 117 #define PIRQE_ROUT 0x68 118 #define PIRQF_ROUT 0x69 119 #define PIRQG_ROUT 0x6A 120 #define PIRQH_ROUT 0x6B 121 122 #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ 123 #define LPC_EN 0x82 /* LPC IF Enables Register */ 124 #define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ 125 #define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ 126 #define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ 127 #define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ 128 #define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ 129 #define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ 130 #define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ 131 #define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ 132 #define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ 133 #define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ 134 #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ 135 #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ 136 #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ 137 #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ 138 139 /* PCI Configuration Space (D31:F2): SATA */ 140 #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) 141 #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) 142 #define INTR_LN 0x3c 143 #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ 144 #define IDE_DECODE_ENABLE (1 << 15) 145 #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ 146 147 #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ 148 #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ 149 #define SATA_SP 0xd0 /* Scratchpad */ 150 151 /* SATA IOBP Registers */ 152 #define SATA_IOBP_SP0G3IR 0xea000151 153 #define SATA_IOBP_SP1G3IR 0xea000051 154 155 /* PCI Configuration Space (D31:F3): SMBus */ 156 #define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3) 157 #define SMB_BASE 0x20 158 #define HOSTC 0x40 159 160 /* HOSTC bits */ 161 #define I2C_EN (1 << 2) 162 #define SMB_SMI_EN (1 << 1) 163 #define HST_EN (1 << 0) 164 165 /* Southbridge IO BARs */ 166 167 #define GPIOBASE 0x48 168 169 #define PMBASE 0x40 170 171 #define VCH 0x0000 /* 32bit */ 172 #define VCAP1 0x0004 /* 32bit */ 173 #define VCAP2 0x0008 /* 32bit */ 174 #define PVC 0x000c /* 16bit */ 175 #define PVS 0x000e /* 16bit */ 176 177 #define V0CAP 0x0010 /* 32bit */ 178 #define V0CTL 0x0014 /* 32bit */ 179 #define V0STS 0x001a /* 16bit */ 180 181 #define V1CAP 0x001c /* 32bit */ 182 #define V1CTL 0x0020 /* 32bit */ 183 #define V1STS 0x0026 /* 16bit */ 184 185 #define RCTCL 0x0100 /* 32bit */ 186 #define ESD 0x0104 /* 32bit */ 187 #define ULD 0x0110 /* 32bit */ 188 #define ULBA 0x0118 /* 64bit */ 189 190 #define RP1D 0x0120 /* 32bit */ 191 #define RP1BA 0x0128 /* 64bit */ 192 #define RP2D 0x0130 /* 32bit */ 193 #define RP2BA 0x0138 /* 64bit */ 194 #define RP3D 0x0140 /* 32bit */ 195 #define RP3BA 0x0148 /* 64bit */ 196 #define RP4D 0x0150 /* 32bit */ 197 #define RP4BA 0x0158 /* 64bit */ 198 #define HDD 0x0160 /* 32bit */ 199 #define HDBA 0x0168 /* 64bit */ 200 #define RP5D 0x0170 /* 32bit */ 201 #define RP5BA 0x0178 /* 64bit */ 202 #define RP6D 0x0180 /* 32bit */ 203 #define RP6BA 0x0188 /* 64bit */ 204 205 #define RPC 0x0400 /* 32bit */ 206 #define RPFN 0x0404 /* 32bit */ 207 208 /* Root Port configuratinon space hide */ 209 #define RPFN_HIDE(port) (1 << (((port) * 4) + 3)) 210 /* Get the function number assigned to a Root Port */ 211 #define RPFN_FNGET(reg,port) (((reg) >> ((port) * 4)) & 7) 212 /* Set the function number for a Root Port */ 213 #define RPFN_FNSET(port,func) (((func) & 7) << ((port) * 4)) 214 /* Root Port function number mask */ 215 #define RPFN_FNMASK(port) (7 << ((port) * 4)) 216 217 #define TRSR 0x1e00 /* 8bit */ 218 #define TRCR 0x1e10 /* 64bit */ 219 #define TWDR 0x1e18 /* 64bit */ 220 221 #define IOTR0 0x1e80 /* 64bit */ 222 #define IOTR1 0x1e88 /* 64bit */ 223 #define IOTR2 0x1e90 /* 64bit */ 224 #define IOTR3 0x1e98 /* 64bit */ 225 226 #define TCTL 0x3000 /* 8bit */ 227 228 #define NOINT 0 229 #define INTA 1 230 #define INTB 2 231 #define INTC 3 232 #define INTD 4 233 234 #define DIR_IDR 12 /* Interrupt D Pin Offset */ 235 #define DIR_ICR 8 /* Interrupt C Pin Offset */ 236 #define DIR_IBR 4 /* Interrupt B Pin Offset */ 237 #define DIR_IAR 0 /* Interrupt A Pin Offset */ 238 239 #define PIRQA 0 240 #define PIRQB 1 241 #define PIRQC 2 242 #define PIRQD 3 243 #define PIRQE 4 244 #define PIRQF 5 245 #define PIRQG 6 246 #define PIRQH 7 247 248 /* IO Buffer Programming */ 249 #define IOBPIRI 0x2330 250 #define IOBPD 0x2334 251 #define IOBPS 0x2338 252 #define IOBPS_RW_BX ((1 << 9)|(1 << 10)) 253 #define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) 254 #define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) 255 256 #define D31IP 0x3100 /* 32bit */ 257 #define D31IP_TTIP 24 /* Thermal Throttle Pin */ 258 #define D31IP_SIP2 20 /* SATA Pin 2 */ 259 #define D31IP_UNKIP 16 260 #define D31IP_SMIP 12 /* SMBUS Pin */ 261 #define D31IP_SIP 8 /* SATA Pin */ 262 #define D30IP 0x3104 /* 32bit */ 263 #define D30IP_PIP 0 /* PCI Bridge Pin */ 264 #define D29IP 0x3108 /* 32bit */ 265 #define D29IP_E1P 0 /* EHCI #1 Pin */ 266 #define D28IP 0x310c /* 32bit */ 267 #define D28IP_P8IP 28 /* PCI Express Port 8 */ 268 #define D28IP_P7IP 24 /* PCI Express Port 7 */ 269 #define D28IP_P6IP 20 /* PCI Express Port 6 */ 270 #define D28IP_P5IP 16 /* PCI Express Port 5 */ 271 #define D28IP_P4IP 12 /* PCI Express Port 4 */ 272 #define D28IP_P3IP 8 /* PCI Express Port 3 */ 273 #define D28IP_P2IP 4 /* PCI Express Port 2 */ 274 #define D28IP_P1IP 0 /* PCI Express Port 1 */ 275 #define D27IP 0x3110 /* 32bit */ 276 #define D27IP_ZIP 0 /* HD Audio Pin */ 277 #define D26IP 0x3114 /* 32bit */ 278 #define D26IP_E2P 0 /* EHCI #2 Pin */ 279 #define D25IP 0x3118 /* 32bit */ 280 #define D25IP_LIP 0 /* GbE LAN Pin */ 281 #define D22IP 0x3124 /* 32bit */ 282 #define D22IP_KTIP 12 /* KT Pin */ 283 #define D22IP_IDERIP 8 /* IDE-R Pin */ 284 #define D22IP_MEI2IP 4 /* MEI #2 Pin */ 285 #define D22IP_MEI1IP 0 /* MEI #1 Pin */ 286 #define D20IP 0x3128 /* 32bit */ 287 #define D20IP_XHCIIP 0 288 #define D31IR 0x3140 /* 16bit */ 289 #define D30IR 0x3142 /* 16bit */ 290 #define D29IR 0x3144 /* 16bit */ 291 #define D28IR 0x3146 /* 16bit */ 292 #define D27IR 0x3148 /* 16bit */ 293 #define D26IR 0x314c /* 16bit */ 294 #define D25IR 0x3150 /* 16bit */ 295 #define D22IR 0x315c /* 16bit */ 296 #define D20IR 0x3160 /* 16bit */ 297 #define OIC 0x31fe /* 16bit */ 298 #define SOFT_RESET_CTRL 0x38f4 299 #define SOFT_RESET_DATA 0x38f8 300 301 #define PRSTS 0x3310 302 #define CIR6 0x2024 303 #define CIR7 0x3314 304 #define CIR8 0x3324 305 #define CIR9 0x3330 306 #define CIR10 0x3340 307 #define CIR13 0x3350 308 #define CIR14 0x3368 309 #define CIR15 0x3378 310 #define CIR16 0x3388 311 #define CIR17 0x33a0 312 #define CIR18 0x33a8 313 #define CIR19 0x33c0 314 #define CIR20 0x33cc 315 #define CIR21 0x33d0 316 #define CIR22 0x33d4 317 318 #define DIR_ROUTE(x,a,b,c,d) \ 319 RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ 320 ((b) << DIR_IBR) | ((a) << DIR_IAR)) 321 322 #define RC 0x3400 /* 32bit */ 323 #define HPTC 0x3404 /* 32bit */ 324 #define GCS 0x3410 /* 32bit */ 325 #define BUC 0x3414 /* 32bit */ 326 #define PCH_DISABLE_GBE (1 << 5) 327 #define FD 0x3418 /* 32bit */ 328 #define DISPBDF 0x3424 /* 16bit */ 329 #define FD2 0x3428 /* 32bit */ 330 #define CG 0x341c /* 32bit */ 331 332 /* Function Disable 1 RCBA 0x3418 */ 333 #define PCH_DISABLE_ALWAYS ((1 << 0)|(1 << 26)) 334 #define PCH_DISABLE_P2P (1 << 1) 335 #define PCH_DISABLE_SATA1 (1 << 2) 336 #define PCH_DISABLE_SMBUS (1 << 3) 337 #define PCH_DISABLE_HD_AUDIO (1 << 4) 338 #define PCH_DISABLE_EHCI2 (1 << 13) 339 #define PCH_DISABLE_LPC (1 << 14) 340 #define PCH_DISABLE_EHCI1 (1 << 15) 341 #define PCH_DISABLE_PCIE(x) (1 << (16 + x)) 342 #define PCH_DISABLE_THERMAL (1 << 24) 343 #define PCH_DISABLE_SATA2 (1 << 25) 344 #define PCH_DISABLE_XHCI (1 << 27) 345 346 /* Function Disable 2 RCBA 0x3428 */ 347 #define PCH_DISABLE_KT (1 << 4) 348 #define PCH_DISABLE_IDER (1 << 3) 349 #define PCH_DISABLE_MEI2 (1 << 2) 350 #define PCH_DISABLE_MEI1 (1 << 1) 351 #define PCH_ENABLE_DBDF (1 << 0) 352 353 /* USB Initialization Registers[13:0] */ 354 #define USBIR0 0x3500 /* 32bit */ 355 #define USBIR1 0x3504 /* 32bit */ 356 #define USBIR2 0x3508 /* 32bit */ 357 #define USBIR3 0x350c /* 32bit */ 358 #define USBIR4 0x3510 /* 32bit */ 359 #define USBIR5 0x3514 /* 32bit */ 360 #define USBIR6 0x3518 /* 32bit */ 361 #define USBIR7 0x351c /* 32bit */ 362 #define USBIR8 0x3520 /* 32bit */ 363 #define USBIR9 0x3524 /* 32bit */ 364 #define USBIR10 0x3528 /* 32bit */ 365 #define USBIR11 0x352c /* 32bit */ 366 #define USBIR12 0x3530 /* 32bit */ 367 #define USBIR13 0x3534 /* 32bit */ 368 369 #define USBIRC 0x3564 /* 32bit */ 370 #define USBIRA 0x3570 /* 32bit */ 371 #define USBIRB 0x357c /* 32bit */ 372 373 /* Miscellaneous Control Register */ 374 #define MISCCTL 0x3590 /* 32bit */ 375 /* USB Port Disable Override */ 376 #define USBPDO 0x359c /* 32bit */ 377 /* USB Overcurrent MAP Register */ 378 #define USBOCM1 0x35a0 /* 32bit */ 379 #define USBOCM2 0x35a4 /* 32bit */ 380 /* Rate Matching Hub Wake Control Register */ 381 #define RMHWKCTL 0x35b0 /* 32bit */ 382 383 /* ICH7 PMBASE */ 384 #define PM1_STS 0x00 385 #define WAK_STS (1 << 15) 386 #define PCIEXPWAK_STS (1 << 14) 387 #define PRBTNOR_STS (1 << 11) 388 #define RTC_STS (1 << 10) 389 #define PWRBTN_STS (1 << 8) 390 #define GBL_STS (1 << 5) 391 #define BM_STS (1 << 4) 392 #define TMROF_STS (1 << 0) 393 #define PM1_EN 0x02 394 #define PCIEXPWAK_DIS (1 << 14) 395 #define RTC_EN (1 << 10) 396 #define PWRBTN_EN (1 << 8) 397 #define GBL_EN (1 << 5) 398 #define TMROF_EN (1 << 0) 399 #define PM1_CNT 0x04 400 #define GBL_RLS (1 << 2) 401 #define BM_RLD (1 << 1) 402 #define SCI_EN (1 << 0) 403 #define PM1_TMR 0x08 404 #define PROC_CNT 0x10 405 #define LV2 0x14 406 #define LV3 0x15 407 #define LV4 0x16 408 #define GPE0_STS 0x20 409 #define PME_B0_STS (1 << 13) 410 #define PME_STS (1 << 11) 411 #define BATLOW_STS (1 << 10) 412 #define PCI_EXP_STS (1 << 9) 413 #define RI_STS (1 << 8) 414 #define SMB_WAK_STS (1 << 7) 415 #define TCOSCI_STS (1 << 6) 416 #define SWGPE_STS (1 << 2) 417 #define HOT_PLUG_STS (1 << 1) 418 #define GPE0_EN 0x28 419 #define PME_B0_EN (1 << 13) 420 #define PME_EN (1 << 11) 421 #define TCOSCI_EN (1 << 6) 422 #define SMI_EN 0x30 423 #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic 424 #define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic 425 #define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS 426 #define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) 427 #define MCSMI_EN (1 << 11) // Trap microcontroller range access 428 #define BIOS_RLS (1 << 7) // asserts SCI on bit set 429 #define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set 430 #define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# 431 #define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# 432 #define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic 433 #define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit 434 #define EOS (1 << 1) // End of SMI (deassert SMI#) 435 #define GBL_SMI_EN (1 << 0) // SMI# generation at all? 436 #define SMI_STS 0x34 437 #define ALT_GP_SMI_EN 0x38 438 #define ALT_GP_SMI_STS 0x3a 439 440 /* PM I/O Space */ 441 #define UPRWC 0x3c 442 #define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ 443 444 #define GPE_CNTL 0x42 445 #define DEVACT_STS 0x44 446 #define PM2_CNT 0x50 // mobile only 447 #define C3_RES 0x54 448 449 #if CONFIG(TCO_SPACE_NOT_YET_SPLIT) 450 #define TCO1_STS 0x64 451 #define DMISCI_STS (1 << 9) 452 #define TCO2_STS 0x66 453 #endif 454 455 #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ 456 #define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ 457 #define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ 458 #define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ 459 #define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ 460 #define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ 461 #define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) 462 #define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ 463 #define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ 464 #define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ 465 #define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ 466 #define SPIBAR_FADDR 0x3808 /* SPI flash address */ 467 #define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */ 468 469 #endif /* __ACPI__ */ 470 #endif /* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */ 471