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1 /*
2  * Copyright (c) 2008 Travis Geiselbrecht
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining
5  * a copy of this software and associated documentation files
6  * (the "Software"), to deal in the Software without restriction,
7  * including without limitation the rights to use, copy, modify, merge,
8  * publish, distribute, sublicense, and/or sell copies of the Software,
9  * and to permit persons to whom the Software is furnished to do so,
10  * subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be
13  * included in all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
18  * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
19  * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
20  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
21  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22  */
23 #pragma once
24 
25 #define SHIFT_4K        (12)
26 #define SHIFT_16K       (14)
27 #define SHIFT_64K       (16)
28 
29 /* arm specific stuff */
30 #ifdef ARM64_LARGE_PAGESIZE_64K
31 #define PAGE_SIZE_SHIFT (SHIFT_64K)
32 #elif ARM64_LARGE_PAGESIZE_16K
33 #define PAGE_SIZE_SHIFT (SHIFT_16K)
34 #else
35 #define PAGE_SIZE_SHIFT (SHIFT_4K)
36 #endif
37 #define USER_PAGE_SIZE_SHIFT SHIFT_4K
38 
39 #define PAGE_SIZE (1UL << PAGE_SIZE_SHIFT)
40 #define USER_PAGE_SIZE (1UL << USER_PAGE_SIZE_SHIFT)
41 
42 /* Determine the d-cache line size in bytes, unless already set by the build */
43 #ifndef CACHE_LINE
44 #if ARM64_CPU_CORTEX_A53 || ARM64_CPU_CORTEX_A57 || ARM64_CPU_CORTEX_A72
45 #define CACHE_LINE 64
46 #else
47 #define CACHE_LINE 32
48 #endif
49 #endif
50 
51 #define ARM64_EXC_SP_EL1_BUF_SIZE (16)
52 
53 #define ARM64_PHYSICAL_STACK_CANARY         (0x5A41A5425A43A544UL)
54 #define ARM64_PHYSICAL_STACK_CANARY_WORDS   (8)
55 #define ARM64_PHYSICAL_STACK_CANARY_ROTATE  (8)
56 
57 #define MTE_GRANULE_SIZE (16)
58 
59 /* Macro to remove Pointer Authentication Code ROP protection from a function */
60 #if defined(KERNEL_PAC_ENABLED) && defined(KERNEL_BTI_ENABLED)
61 #define __ARCH_NO_PAC __attribute__((target("branch-protection=bti")))
62 #else
63 #define __ARCH_NO_PAC __attribute__((target("branch-protection=none")))
64 #endif
65