1 // Copyright 2015, VIXL authors
2 // All rights reserved.
3 //
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5 // modification, are permitted provided that the following conditions are met:
6 //
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8 // this list of conditions and the following disclaimer.
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10 // this list of conditions and the following disclaimer in the documentation
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26
27 #ifndef VIXL_AARCH64_CONSTANTS_AARCH64_H_
28 #define VIXL_AARCH64_CONSTANTS_AARCH64_H_
29
30 #include "../globals-vixl.h"
31
32 namespace vixl {
33 namespace aarch64 {
34
35 const unsigned kNumberOfRegisters = 32;
36 const unsigned kNumberOfVRegisters = 32;
37 const unsigned kNumberOfZRegisters = kNumberOfVRegisters;
38 const unsigned kNumberOfPRegisters = 16;
39 // Callee saved registers are x21-x30(lr).
40 const int kNumberOfCalleeSavedRegisters = 10;
41 const int kFirstCalleeSavedRegisterIndex = 21;
42 // Callee saved FP registers are d8-d15. Note that the high parts of v8-v15 are
43 // still caller-saved.
44 const int kNumberOfCalleeSavedFPRegisters = 8;
45 const int kFirstCalleeSavedFPRegisterIndex = 8;
46 // All predicated instructions accept at least p0-p7 as the governing predicate.
47 const unsigned kNumberOfGoverningPRegisters = 8;
48
49 // clang-format off
50 #define AARCH64_P_REGISTER_CODE_LIST(R) \
51 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \
52 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15)
53
54 #define AARCH64_REGISTER_CODE_LIST(R) \
55 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \
56 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \
57 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \
58 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31)
59
60 // SVE loads and stores use "w" instead of "s" for word-sized accesses, so the
61 // mapping from the load/store variant to constants like k*RegSize is irregular.
62 #define VIXL_SVE_LOAD_STORE_VARIANT_LIST(V) \
63 V(b, B) \
64 V(h, H) \
65 V(w, S) \
66 V(d, D)
67
68 // Sign-extending loads don't have double-word variants.
69 #define VIXL_SVE_LOAD_STORE_SIGNED_VARIANT_LIST(V) \
70 V(b, B) \
71 V(h, H) \
72 V(w, S)
73
74 #define INSTRUCTION_FIELDS_LIST(V_) \
75 /* Register fields */ \
76 V_(Rd, 4, 0, ExtractBits) /* Destination register. */ \
77 V_(Rn, 9, 5, ExtractBits) /* First source register. */ \
78 V_(Rm, 20, 16, ExtractBits) /* Second source register. */ \
79 V_(RmLow16, 19, 16, ExtractBits) /* Second source register (code 0-15). */ \
80 V_(Ra, 14, 10, ExtractBits) /* Third source register. */ \
81 V_(Rt, 4, 0, ExtractBits) /* Load/store register. */ \
82 V_(Rt2, 14, 10, ExtractBits) /* Load/store second register. */ \
83 V_(Rs, 20, 16, ExtractBits) /* Exclusive access status. */ \
84 V_(Pt, 3, 0, ExtractBits) /* Load/store register (p0-p7). */ \
85 V_(Pd, 3, 0, ExtractBits) /* SVE destination predicate register. */ \
86 V_(Pn, 8, 5, ExtractBits) /* SVE first source predicate register. */ \
87 V_(Pm, 19, 16, ExtractBits) /* SVE second source predicate register.*/ \
88 V_(PgLow8, 12, 10, ExtractBits) /* Governing predicate (p0-p7). */ \
89 \
90 /* Common bits */ \
91 V_(SixtyFourBits, 31, 31, ExtractBits) \
92 V_(FlagsUpdate, 29, 29, ExtractBits) \
93 \
94 /* PC relative addressing */ \
95 V_(ImmPCRelHi, 23, 5, ExtractSignedBits) \
96 V_(ImmPCRelLo, 30, 29, ExtractBits) \
97 \
98 /* Add/subtract/logical shift register */ \
99 V_(ShiftDP, 23, 22, ExtractBits) \
100 V_(ImmDPShift, 15, 10, ExtractBits) \
101 \
102 /* Add/subtract immediate */ \
103 V_(ImmAddSub, 21, 10, ExtractBits) \
104 V_(ImmAddSubShift, 22, 22, ExtractBits) \
105 \
106 /* Add/substract extend */ \
107 V_(ImmExtendShift, 12, 10, ExtractBits) \
108 V_(ExtendMode, 15, 13, ExtractBits) \
109 \
110 /* Move wide */ \
111 V_(ImmMoveWide, 20, 5, ExtractBits) \
112 V_(ShiftMoveWide, 22, 21, ExtractBits) \
113 \
114 /* Logical immediate, bitfield and extract */ \
115 V_(BitN, 22, 22, ExtractBits) \
116 V_(ImmRotate, 21, 16, ExtractBits) \
117 V_(ImmSetBits, 15, 10, ExtractBits) \
118 V_(ImmR, 21, 16, ExtractBits) \
119 V_(ImmS, 15, 10, ExtractBits) \
120 \
121 /* Test and branch immediate */ \
122 V_(ImmTestBranch, 18, 5, ExtractSignedBits) \
123 V_(ImmTestBranchBit40, 23, 19, ExtractBits) \
124 V_(ImmTestBranchBit5, 31, 31, ExtractBits) \
125 \
126 /* Conditionals */ \
127 V_(Condition, 15, 12, ExtractBits) \
128 V_(ConditionBranch, 3, 0, ExtractBits) \
129 V_(Nzcv, 3, 0, ExtractBits) \
130 V_(ImmCondCmp, 20, 16, ExtractBits) \
131 V_(ImmCondBranch, 23, 5, ExtractSignedBits) \
132 \
133 /* Floating point */ \
134 V_(FPType, 23, 22, ExtractBits) \
135 V_(ImmFP, 20, 13, ExtractBits) \
136 V_(FPScale, 15, 10, ExtractBits) \
137 \
138 /* Load Store */ \
139 V_(ImmLS, 20, 12, ExtractSignedBits) \
140 V_(ImmLSUnsigned, 21, 10, ExtractBits) \
141 V_(ImmLSPair, 21, 15, ExtractSignedBits) \
142 V_(ImmShiftLS, 12, 12, ExtractBits) \
143 V_(LSOpc, 23, 22, ExtractBits) \
144 V_(LSVector, 26, 26, ExtractBits) \
145 V_(LSSize, 31, 30, ExtractBits) \
146 V_(ImmPrefetchOperation, 4, 0, ExtractBits) \
147 V_(PrefetchHint, 4, 3, ExtractBits) \
148 V_(PrefetchTarget, 2, 1, ExtractBits) \
149 V_(PrefetchStream, 0, 0, ExtractBits) \
150 V_(ImmLSPACHi, 22, 22, ExtractSignedBits) \
151 V_(ImmLSPACLo, 20, 12, ExtractBits) \
152 \
153 /* Other immediates */ \
154 V_(ImmUncondBranch, 25, 0, ExtractSignedBits) \
155 V_(ImmCmpBranch, 23, 5, ExtractSignedBits) \
156 V_(ImmLLiteral, 23, 5, ExtractSignedBits) \
157 V_(ImmException, 20, 5, ExtractBits) \
158 V_(ImmHint, 11, 5, ExtractBits) \
159 V_(ImmBarrierDomain, 11, 10, ExtractBits) \
160 V_(ImmBarrierType, 9, 8, ExtractBits) \
161 V_(ImmUdf, 15, 0, ExtractBits) \
162 \
163 /* System (MRS, MSR, SYS) */ \
164 V_(ImmSystemRegister, 20, 5, ExtractBits) \
165 V_(SysO0, 19, 19, ExtractBits) \
166 V_(SysOp, 18, 5, ExtractBits) \
167 V_(SysOp0, 20, 19, ExtractBits) \
168 V_(SysOp1, 18, 16, ExtractBits) \
169 V_(SysOp2, 7, 5, ExtractBits) \
170 V_(CRn, 15, 12, ExtractBits) \
171 V_(CRm, 11, 8, ExtractBits) \
172 V_(ImmRMIFRotation, 20, 15, ExtractBits) \
173 \
174 /* Load-/store-exclusive */ \
175 V_(LdStXLoad, 22, 22, ExtractBits) \
176 V_(LdStXNotExclusive, 23, 23, ExtractBits) \
177 V_(LdStXAcquireRelease, 15, 15, ExtractBits) \
178 V_(LdStXSizeLog2, 31, 30, ExtractBits) \
179 V_(LdStXPair, 21, 21, ExtractBits) \
180 \
181 /* NEON generic fields */ \
182 V_(NEONQ, 30, 30, ExtractBits) \
183 V_(NEONSize, 23, 22, ExtractBits) \
184 V_(NEONLSSize, 11, 10, ExtractBits) \
185 V_(NEONS, 12, 12, ExtractBits) \
186 V_(NEONL, 21, 21, ExtractBits) \
187 V_(NEONM, 20, 20, ExtractBits) \
188 V_(NEONH, 11, 11, ExtractBits) \
189 V_(ImmNEONExt, 14, 11, ExtractBits) \
190 V_(ImmNEON5, 20, 16, ExtractBits) \
191 V_(ImmNEON4, 14, 11, ExtractBits) \
192 \
193 /* NEON extra fields */ \
194 V_(ImmRotFcadd, 12, 12, ExtractBits) \
195 V_(ImmRotFcmlaVec, 12, 11, ExtractBits) \
196 V_(ImmRotFcmlaSca, 14, 13, ExtractBits) \
197 \
198 /* NEON Modified Immediate fields */ \
199 V_(ImmNEONabc, 18, 16, ExtractBits) \
200 V_(ImmNEONdefgh, 9, 5, ExtractBits) \
201 V_(NEONModImmOp, 29, 29, ExtractBits) \
202 V_(NEONCmode, 15, 12, ExtractBits) \
203 \
204 /* NEON Shift Immediate fields */ \
205 V_(ImmNEONImmhImmb, 22, 16, ExtractBits) \
206 V_(ImmNEONImmh, 22, 19, ExtractBits) \
207 V_(ImmNEONImmb, 18, 16, ExtractBits) \
208 \
209 /* SVE generic fields */ \
210 V_(SVESize, 23, 22, ExtractBits) \
211 V_(ImmSVEVLScale, 10, 5, ExtractSignedBits) \
212 V_(ImmSVEIntWideSigned, 12, 5, ExtractSignedBits) \
213 V_(ImmSVEIntWideUnsigned, 12, 5, ExtractBits) \
214 V_(ImmSVEPredicateConstraint, 9, 5, ExtractBits) \
215 \
216 /* SVE Bitwise Immediate bitfield */ \
217 V_(SVEBitN, 17, 17, ExtractBits) \
218 V_(SVEImmRotate, 16, 11, ExtractBits) \
219 V_(SVEImmSetBits, 10, 5, ExtractBits) \
220 \
221 V_(SVEImmPrefetchOperation, 3, 0, ExtractBits) \
222 V_(SVEPrefetchHint, 3, 3, ExtractBits)
223
224 // clang-format on
225
226 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \
227 /* NZCV */ \
228 V_(Flags, 31, 28, ExtractBits) \
229 V_(N, 31, 31, ExtractBits) \
230 V_(Z, 30, 30, ExtractBits) \
231 V_(C, 29, 29, ExtractBits) \
232 V_(V, 28, 28, ExtractBits) \
233 M_(NZCV, Flags_mask) \
234 /* FPCR */ \
235 V_(AHP, 26, 26, ExtractBits) \
236 V_(DN, 25, 25, ExtractBits) \
237 V_(FZ, 24, 24, ExtractBits) \
238 V_(RMode, 23, 22, ExtractBits) \
239 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask)
240
241 // Fields offsets.
242 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, X) \
243 const int Name##_offset = LowBit; \
244 const int Name##_width = HighBit - LowBit + 1; \
245 const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit;
246 #define NOTHING(A, B)
247 INSTRUCTION_FIELDS_LIST(DECLARE_FIELDS_OFFSETS)
248 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING)
249 #undef NOTHING
250 #undef DECLARE_FIELDS_BITS
251
252 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed
253 // from ImmPCRelLo and ImmPCRelHi.
254 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask;
255
256 // Disable `clang-format` for the `enum`s below. We care about the manual
257 // formatting that `clang-format` would destroy.
258 // clang-format off
259
260 // Condition codes.
261 enum Condition {
262 eq = 0, // Z set Equal.
263 ne = 1, // Z clear Not equal.
264 cs = 2, // C set Carry set.
265 cc = 3, // C clear Carry clear.
266 mi = 4, // N set Negative.
267 pl = 5, // N clear Positive or zero.
268 vs = 6, // V set Overflow.
269 vc = 7, // V clear No overflow.
270 hi = 8, // C set, Z clear Unsigned higher.
271 ls = 9, // C clear or Z set Unsigned lower or same.
272 ge = 10, // N == V Greater or equal.
273 lt = 11, // N != V Less than.
274 gt = 12, // Z clear, N == V Greater than.
275 le = 13, // Z set or N != V Less then or equal
276 al = 14, // Always.
277 nv = 15, // Behaves as always/al.
278
279 // Aliases.
280 hs = cs, // C set Unsigned higher or same.
281 lo = cc, // C clear Unsigned lower.
282
283 // Floating-point additional condition code.
284 uo, // Unordered comparison.
285
286 // SVE predicate condition aliases.
287 sve_none = eq, // No active elements were true.
288 sve_any = ne, // An active element was true.
289 sve_nlast = cs, // The last element was not true.
290 sve_last = cc, // The last element was true.
291 sve_first = mi, // The first element was true.
292 sve_nfrst = pl, // The first element was not true.
293 sve_pmore = hi, // An active element was true but not the last element.
294 sve_plast = ls, // The last active element was true or no active elements were true.
295 sve_tcont = ge, // CTERM termination condition not deleted.
296 sve_tstop = lt // CTERM termination condition deleted.
297 };
298
InvertCondition(Condition cond)299 inline Condition InvertCondition(Condition cond) {
300 // Conditions al and nv behave identically, as "always true". They can't be
301 // inverted, because there is no "always false" condition.
302 VIXL_ASSERT((cond != al) && (cond != nv));
303 return static_cast<Condition>(cond ^ 1);
304 }
305
306 enum FPTrapFlags {
307 EnableTrap = 1,
308 DisableTrap = 0
309 };
310
311 enum FlagsUpdate {
312 SetFlags = 1,
313 LeaveFlags = 0
314 };
315
316 enum StatusFlags {
317 NoFlag = 0,
318
319 // Derive the flag combinations from the system register bit descriptions.
320 NFlag = N_mask,
321 ZFlag = Z_mask,
322 CFlag = C_mask,
323 VFlag = V_mask,
324 NZFlag = NFlag | ZFlag,
325 NCFlag = NFlag | CFlag,
326 NVFlag = NFlag | VFlag,
327 ZCFlag = ZFlag | CFlag,
328 ZVFlag = ZFlag | VFlag,
329 CVFlag = CFlag | VFlag,
330 NZCFlag = NFlag | ZFlag | CFlag,
331 NZVFlag = NFlag | ZFlag | VFlag,
332 NCVFlag = NFlag | CFlag | VFlag,
333 ZCVFlag = ZFlag | CFlag | VFlag,
334 NZCVFlag = NFlag | ZFlag | CFlag | VFlag,
335
336 // Floating-point comparison results.
337 FPEqualFlag = ZCFlag,
338 FPLessThanFlag = NFlag,
339 FPGreaterThanFlag = CFlag,
340 FPUnorderedFlag = CVFlag,
341
342 // SVE condition flags.
343 SVEFirstFlag = NFlag,
344 SVENoneFlag = ZFlag,
345 SVENotLastFlag = CFlag
346 };
347
348 enum Shift {
349 NO_SHIFT = -1,
350 LSL = 0x0,
351 LSR = 0x1,
352 ASR = 0x2,
353 ROR = 0x3,
354 MSL = 0x4
355 };
356
357 enum Extend {
358 NO_EXTEND = -1,
359 UXTB = 0,
360 UXTH = 1,
361 UXTW = 2,
362 UXTX = 3,
363 SXTB = 4,
364 SXTH = 5,
365 SXTW = 6,
366 SXTX = 7
367 };
368
369 enum SVEOffsetModifier {
370 NO_SVE_OFFSET_MODIFIER,
371 // Multiply (each element of) the offset by either the vector or predicate
372 // length, according to the context.
373 SVE_MUL_VL,
374 // Shift or extend modifiers (as in `Shift` or `Extend`).
375 SVE_LSL,
376 SVE_UXTW,
377 SVE_SXTW
378 };
379
380 enum SystemHint {
381 NOP = 0,
382 YIELD = 1,
383 WFE = 2,
384 WFI = 3,
385 SEV = 4,
386 SEVL = 5,
387 ESB = 16,
388 CSDB = 20,
389 BTI = 32,
390 BTI_c = 34,
391 BTI_j = 36,
392 BTI_jc = 38,
393 CHKFEAT = 40
394 };
395
396 enum BranchTargetIdentifier {
397 EmitBTI_none = NOP,
398 EmitBTI = BTI,
399 EmitBTI_c = BTI_c,
400 EmitBTI_j = BTI_j,
401 EmitBTI_jc = BTI_jc,
402
403 // These correspond to the values of the CRm:op2 fields in the equivalent HINT
404 // instruction.
405 EmitPACIASP = 25,
406 EmitPACIBSP = 27
407 };
408
409 enum BarrierDomain {
410 OuterShareable = 0,
411 NonShareable = 1,
412 InnerShareable = 2,
413 FullSystem = 3
414 };
415
416 enum BarrierType {
417 BarrierOther = 0,
418 BarrierReads = 1,
419 BarrierWrites = 2,
420 BarrierAll = 3
421 };
422
423 enum PrefetchOperation {
424 PLDL1KEEP = 0x00,
425 PLDL1STRM = 0x01,
426 PLDL2KEEP = 0x02,
427 PLDL2STRM = 0x03,
428 PLDL3KEEP = 0x04,
429 PLDL3STRM = 0x05,
430
431 PrfUnallocated06 = 0x06,
432 PrfUnallocated07 = 0x07,
433
434 PLIL1KEEP = 0x08,
435 PLIL1STRM = 0x09,
436 PLIL2KEEP = 0x0a,
437 PLIL2STRM = 0x0b,
438 PLIL3KEEP = 0x0c,
439 PLIL3STRM = 0x0d,
440
441 PrfUnallocated0e = 0x0e,
442 PrfUnallocated0f = 0x0f,
443
444 PSTL1KEEP = 0x10,
445 PSTL1STRM = 0x11,
446 PSTL2KEEP = 0x12,
447 PSTL2STRM = 0x13,
448 PSTL3KEEP = 0x14,
449 PSTL3STRM = 0x15,
450
451 PrfUnallocated16 = 0x16,
452 PrfUnallocated17 = 0x17,
453 PrfUnallocated18 = 0x18,
454 PrfUnallocated19 = 0x19,
455 PrfUnallocated1a = 0x1a,
456 PrfUnallocated1b = 0x1b,
457 PrfUnallocated1c = 0x1c,
458 PrfUnallocated1d = 0x1d,
459 PrfUnallocated1e = 0x1e,
460 PrfUnallocated1f = 0x1f,
461 };
462
IsNamedPrefetchOperation(int op)463 constexpr bool IsNamedPrefetchOperation(int op) {
464 return ((op >= PLDL1KEEP) && (op <= PLDL3STRM)) ||
465 ((op >= PLIL1KEEP) && (op <= PLIL3STRM)) ||
466 ((op >= PSTL1KEEP) && (op <= PSTL3STRM));
467 }
468
469 enum BType {
470 // Set when executing any instruction on a guarded page, except those cases
471 // listed below.
472 DefaultBType = 0,
473
474 // Set when an indirect branch is taken from an unguarded page to a guarded
475 // page, or from a guarded page to ip0 or ip1 (x16 or x17), eg "br ip0".
476 BranchFromUnguardedOrToIP = 1,
477
478 // Set when an indirect branch and link (call) is taken, eg. "blr x0".
479 BranchAndLink = 2,
480
481 // Set when an indirect branch is taken from a guarded page to a register
482 // that is not ip0 or ip1 (x16 or x17), eg, "br x0".
483 BranchFromGuardedNotToIP = 3
484 };
485
486 template<int op0, int op1, int crn, int crm, int op2>
487 class SystemRegisterEncoder {
488 public:
489 static const uint32_t value =
490 ((op0 << SysO0_offset) |
491 (op1 << SysOp1_offset) |
492 (crn << CRn_offset) |
493 (crm << CRm_offset) |
494 (op2 << SysOp2_offset)) >> ImmSystemRegister_offset;
495 };
496
497 // System/special register names.
498 // This information is not encoded as one field but as the concatenation of
499 // multiple fields (Op0, Op1, Crn, Crm, Op2).
500 enum SystemRegister {
501 NZCV = SystemRegisterEncoder<3, 3, 4, 2, 0>::value,
502 FPCR = SystemRegisterEncoder<3, 3, 4, 4, 0>::value,
503 RNDR = SystemRegisterEncoder<3, 3, 2, 4, 0>::value, // Random number.
504 RNDRRS = SystemRegisterEncoder<3, 3, 2, 4, 1>::value, // Reseeded random number.
505 DCZID_EL0 = SystemRegisterEncoder<3, 3, 0, 0, 7>::value
506 };
507
508 template<int op1, int crn, int crm, int op2>
509 class CacheOpEncoder {
510 public:
511 static const uint32_t value =
512 ((op1 << SysOp1_offset) |
513 (crn << CRn_offset) |
514 (crm << CRm_offset) |
515 (op2 << SysOp2_offset)) >> SysOp_offset;
516 };
517
518 enum InstructionCacheOp {
519 IVAU = CacheOpEncoder<3, 7, 5, 1>::value
520 };
521
522 enum DataCacheOp {
523 CVAC = CacheOpEncoder<3, 7, 10, 1>::value,
524 CVAU = CacheOpEncoder<3, 7, 11, 1>::value,
525 CVAP = CacheOpEncoder<3, 7, 12, 1>::value,
526 CVADP = CacheOpEncoder<3, 7, 13, 1>::value,
527 CIVAC = CacheOpEncoder<3, 7, 14, 1>::value,
528 ZVA = CacheOpEncoder<3, 7, 4, 1>::value,
529 GVA = CacheOpEncoder<3, 7, 4, 3>::value,
530 GZVA = CacheOpEncoder<3, 7, 4, 4>::value,
531 CGVAC = CacheOpEncoder<3, 7, 10, 3>::value,
532 CGDVAC = CacheOpEncoder<3, 7, 10, 5>::value,
533 CGVAP = CacheOpEncoder<3, 7, 12, 3>::value,
534 CGDVAP = CacheOpEncoder<3, 7, 12, 5>::value,
535 CIGVAC = CacheOpEncoder<3, 7, 14, 3>::value,
536 CIGDVAC = CacheOpEncoder<3, 7, 14, 5>::value
537 };
538
539 enum GCSOp {
540 GCSPUSHM = CacheOpEncoder<3, 7, 7, 0>::value,
541 GCSPOPM = CacheOpEncoder<3, 7, 7, 1>::value,
542 GCSSS1 = CacheOpEncoder<3, 7, 7, 2>::value,
543 GCSSS2 = CacheOpEncoder<3, 7, 7, 3>::value
544 };
545
546 // Some SVE instructions support a predicate constraint pattern. This is
547 // interpreted as a VL-dependent value, and is typically used to initialise
548 // predicates, or to otherwise limit the number of processed elements.
549 enum SVEPredicateConstraint {
550 // Select 2^N elements, for the largest possible N.
551 SVE_POW2 = 0x0,
552 // Each VL<N> selects exactly N elements if possible, or zero if N is greater
553 // than the number of elements. Note that the encoding values for VL<N> are
554 // not linearly related to N.
555 SVE_VL1 = 0x1,
556 SVE_VL2 = 0x2,
557 SVE_VL3 = 0x3,
558 SVE_VL4 = 0x4,
559 SVE_VL5 = 0x5,
560 SVE_VL6 = 0x6,
561 SVE_VL7 = 0x7,
562 SVE_VL8 = 0x8,
563 SVE_VL16 = 0x9,
564 SVE_VL32 = 0xa,
565 SVE_VL64 = 0xb,
566 SVE_VL128 = 0xc,
567 SVE_VL256 = 0xd,
568 // Each MUL<N> selects the largest multiple of N elements that the vector
569 // length supports. Note that for D-sized lanes, this can be zero.
570 SVE_MUL4 = 0x1d,
571 SVE_MUL3 = 0x1e,
572 // Select all elements.
573 SVE_ALL = 0x1f
574 };
575
576 // Instruction enumerations.
577 //
578 // These are the masks that define a class of instructions, and the list of
579 // instructions within each class. Each enumeration has a Fixed, FMask and
580 // Mask value.
581 //
582 // Fixed: The fixed bits in this instruction class.
583 // FMask: The mask used to extract the fixed bits in the class.
584 // Mask: The mask used to identify the instructions within a class.
585 //
586 // The enumerations can be used like this:
587 //
588 // VIXL_ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed);
589 // switch(instr->Mask(PCRelAddressingMask)) {
590 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break;
591 // case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break;
592 // default: printf("Unknown instruction\n");
593 // }
594
595
596 // Generic fields.
597 enum GenericInstrField {
598 SixtyFourBits = 0x80000000,
599 ThirtyTwoBits = 0x00000000,
600
601 FPTypeMask = 0x00C00000,
602 FP16 = 0x00C00000,
603 FP32 = 0x00000000,
604 FP64 = 0x00400000
605 };
606
607 enum NEONFormatField {
608 NEONFormatFieldMask = 0x40C00000,
609 NEON_Q = 0x40000000,
610 NEON_8B = 0x00000000,
611 NEON_16B = NEON_8B | NEON_Q,
612 NEON_4H = 0x00400000,
613 NEON_8H = NEON_4H | NEON_Q,
614 NEON_2S = 0x00800000,
615 NEON_4S = NEON_2S | NEON_Q,
616 NEON_1D = 0x00C00000,
617 NEON_2D = 0x00C00000 | NEON_Q
618 };
619
620 enum NEONFPFormatField {
621 NEONFPFormatFieldMask = 0x40400000,
622 NEON_FP_4H = FP16,
623 NEON_FP_2S = FP32,
624 NEON_FP_8H = FP16 | NEON_Q,
625 NEON_FP_4S = FP32 | NEON_Q,
626 NEON_FP_2D = FP64 | NEON_Q
627 };
628
629 enum NEONLSFormatField {
630 NEONLSFormatFieldMask = 0x40000C00,
631 LS_NEON_8B = 0x00000000,
632 LS_NEON_16B = LS_NEON_8B | NEON_Q,
633 LS_NEON_4H = 0x00000400,
634 LS_NEON_8H = LS_NEON_4H | NEON_Q,
635 LS_NEON_2S = 0x00000800,
636 LS_NEON_4S = LS_NEON_2S | NEON_Q,
637 LS_NEON_1D = 0x00000C00,
638 LS_NEON_2D = LS_NEON_1D | NEON_Q
639 };
640
641 enum NEONScalarFormatField {
642 NEONScalarFormatFieldMask = 0x00C00000,
643 NEONScalar = 0x10000000,
644 NEON_B = 0x00000000,
645 NEON_H = 0x00400000,
646 NEON_S = 0x00800000,
647 NEON_D = 0x00C00000
648 };
649
650 enum SVESizeField {
651 SVESizeFieldMask = 0x00C00000,
652 SVE_B = 0x00000000,
653 SVE_H = 0x00400000,
654 SVE_S = 0x00800000,
655 SVE_D = 0x00C00000
656 };
657
658 // PC relative addressing.
659 enum PCRelAddressingOp {
660 PCRelAddressingFixed = 0x10000000,
661 PCRelAddressingFMask = 0x1F000000,
662 PCRelAddressingMask = 0x9F000000,
663 ADR = PCRelAddressingFixed | 0x00000000,
664 ADRP = PCRelAddressingFixed | 0x80000000
665 };
666
667 // Add/sub (immediate, shifted and extended.)
668 const int kSFOffset = 31;
669 enum AddSubOp {
670 AddSubOpMask = 0x60000000,
671 AddSubSetFlagsBit = 0x20000000,
672 ADD = 0x00000000,
673 ADDS = ADD | AddSubSetFlagsBit,
674 SUB = 0x40000000,
675 SUBS = SUB | AddSubSetFlagsBit
676 };
677
678 #define ADD_SUB_OP_LIST(V) \
679 V(ADD), \
680 V(ADDS), \
681 V(SUB), \
682 V(SUBS)
683
684 enum AddSubImmediateOp {
685 AddSubImmediateFixed = 0x11000000,
686 AddSubImmediateFMask = 0x1F800000,
687 AddSubImmediateMask = 0xFF800000,
688 #define ADD_SUB_IMMEDIATE(A) \
689 A##_w_imm = AddSubImmediateFixed | A, \
690 A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits
691 ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE)
692 #undef ADD_SUB_IMMEDIATE
693 };
694
695 enum AddSubShiftedOp {
696 AddSubShiftedFixed = 0x0B000000,
697 AddSubShiftedFMask = 0x1F200000,
698 AddSubShiftedMask = 0xFF200000,
699 #define ADD_SUB_SHIFTED(A) \
700 A##_w_shift = AddSubShiftedFixed | A, \
701 A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits
702 ADD_SUB_OP_LIST(ADD_SUB_SHIFTED)
703 #undef ADD_SUB_SHIFTED
704 };
705
706 enum AddSubExtendedOp {
707 AddSubExtendedFixed = 0x0B200000,
708 AddSubExtendedFMask = 0x1F200000,
709 AddSubExtendedMask = 0xFFE00000,
710 #define ADD_SUB_EXTENDED(A) \
711 A##_w_ext = AddSubExtendedFixed | A, \
712 A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits
713 ADD_SUB_OP_LIST(ADD_SUB_EXTENDED)
714 #undef ADD_SUB_EXTENDED
715 };
716
717 // Add/sub with carry.
718 enum AddSubWithCarryOp {
719 AddSubWithCarryFixed = 0x1A000000,
720 AddSubWithCarryFMask = 0x1FE00000,
721 AddSubWithCarryMask = 0xFFE0FC00,
722 ADC_w = AddSubWithCarryFixed | ADD,
723 ADC_x = AddSubWithCarryFixed | ADD | SixtyFourBits,
724 ADC = ADC_w,
725 ADCS_w = AddSubWithCarryFixed | ADDS,
726 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits,
727 SBC_w = AddSubWithCarryFixed | SUB,
728 SBC_x = AddSubWithCarryFixed | SUB | SixtyFourBits,
729 SBC = SBC_w,
730 SBCS_w = AddSubWithCarryFixed | SUBS,
731 SBCS_x = AddSubWithCarryFixed | SUBS | SixtyFourBits
732 };
733
734 // Rotate right into flags.
735 enum RotateRightIntoFlagsOp {
736 RotateRightIntoFlagsFixed = 0x1A000400,
737 RotateRightIntoFlagsFMask = 0x1FE07C00,
738 RotateRightIntoFlagsMask = 0xFFE07C10,
739 RMIF = RotateRightIntoFlagsFixed | 0xA0000000
740 };
741
742 // Evaluate into flags.
743 enum EvaluateIntoFlagsOp {
744 EvaluateIntoFlagsFixed = 0x1A000800,
745 EvaluateIntoFlagsFMask = 0x1FE03C00,
746 EvaluateIntoFlagsMask = 0xFFE07C1F,
747 SETF8 = EvaluateIntoFlagsFixed | 0x2000000D,
748 SETF16 = EvaluateIntoFlagsFixed | 0x2000400D
749 };
750
751
752 // Logical (immediate and shifted register).
753 enum LogicalOp {
754 LogicalOpMask = 0x60200000,
755 NOT = 0x00200000,
756 AND = 0x00000000,
757 BIC = AND | NOT,
758 ORR = 0x20000000,
759 ORN = ORR | NOT,
760 EOR = 0x40000000,
761 EON = EOR | NOT,
762 ANDS = 0x60000000,
763 BICS = ANDS | NOT
764 };
765
766 // Logical immediate.
767 enum LogicalImmediateOp {
768 LogicalImmediateFixed = 0x12000000,
769 LogicalImmediateFMask = 0x1F800000,
770 LogicalImmediateMask = 0xFF800000,
771 AND_w_imm = LogicalImmediateFixed | AND,
772 AND_x_imm = LogicalImmediateFixed | AND | SixtyFourBits,
773 ORR_w_imm = LogicalImmediateFixed | ORR,
774 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits,
775 EOR_w_imm = LogicalImmediateFixed | EOR,
776 EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits,
777 ANDS_w_imm = LogicalImmediateFixed | ANDS,
778 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits
779 };
780
781 // Logical shifted register.
782 enum LogicalShiftedOp {
783 LogicalShiftedFixed = 0x0A000000,
784 LogicalShiftedFMask = 0x1F000000,
785 LogicalShiftedMask = 0xFF200000,
786 AND_w = LogicalShiftedFixed | AND,
787 AND_x = LogicalShiftedFixed | AND | SixtyFourBits,
788 AND_shift = AND_w,
789 BIC_w = LogicalShiftedFixed | BIC,
790 BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits,
791 BIC_shift = BIC_w,
792 ORR_w = LogicalShiftedFixed | ORR,
793 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits,
794 ORR_shift = ORR_w,
795 ORN_w = LogicalShiftedFixed | ORN,
796 ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits,
797 ORN_shift = ORN_w,
798 EOR_w = LogicalShiftedFixed | EOR,
799 EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits,
800 EOR_shift = EOR_w,
801 EON_w = LogicalShiftedFixed | EON,
802 EON_x = LogicalShiftedFixed | EON | SixtyFourBits,
803 EON_shift = EON_w,
804 ANDS_w = LogicalShiftedFixed | ANDS,
805 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits,
806 ANDS_shift = ANDS_w,
807 BICS_w = LogicalShiftedFixed | BICS,
808 BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits,
809 BICS_shift = BICS_w
810 };
811
812 // Move wide immediate.
813 enum MoveWideImmediateOp {
814 MoveWideImmediateFixed = 0x12800000,
815 MoveWideImmediateFMask = 0x1F800000,
816 MoveWideImmediateMask = 0xFF800000,
817 MOVN = 0x00000000,
818 MOVZ = 0x40000000,
819 MOVK = 0x60000000,
820 MOVN_w = MoveWideImmediateFixed | MOVN,
821 MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits,
822 MOVZ_w = MoveWideImmediateFixed | MOVZ,
823 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits,
824 MOVK_w = MoveWideImmediateFixed | MOVK,
825 MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits
826 };
827
828 // Bitfield.
829 const int kBitfieldNOffset = 22;
830 enum BitfieldOp {
831 BitfieldFixed = 0x13000000,
832 BitfieldFMask = 0x1F800000,
833 BitfieldMask = 0xFF800000,
834 SBFM_w = BitfieldFixed | 0x00000000,
835 SBFM_x = BitfieldFixed | 0x80000000,
836 SBFM = SBFM_w,
837 BFM_w = BitfieldFixed | 0x20000000,
838 BFM_x = BitfieldFixed | 0xA0000000,
839 BFM = BFM_w,
840 UBFM_w = BitfieldFixed | 0x40000000,
841 UBFM_x = BitfieldFixed | 0xC0000000,
842 UBFM = UBFM_w
843 // Bitfield N field.
844 };
845
846 // Extract.
847 enum ExtractOp {
848 ExtractFixed = 0x13800000,
849 ExtractFMask = 0x1F800000,
850 ExtractMask = 0xFFA00000,
851 EXTR_w = ExtractFixed | 0x00000000,
852 EXTR_x = ExtractFixed | 0x80000000,
853 EXTR = EXTR_w
854 };
855
856 // Unconditional branch.
857 enum UnconditionalBranchOp {
858 UnconditionalBranchFixed = 0x14000000,
859 UnconditionalBranchFMask = 0x7C000000,
860 UnconditionalBranchMask = 0xFC000000,
861 B = UnconditionalBranchFixed | 0x00000000,
862 BL = UnconditionalBranchFixed | 0x80000000
863 };
864
865 // Unconditional branch to register.
866 enum UnconditionalBranchToRegisterOp {
867 UnconditionalBranchToRegisterFixed = 0xD6000000,
868 UnconditionalBranchToRegisterFMask = 0xFE000000,
869 UnconditionalBranchToRegisterMask = 0xFFFFFC00,
870 BR = UnconditionalBranchToRegisterFixed | 0x001F0000,
871 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000,
872 RET = UnconditionalBranchToRegisterFixed | 0x005F0000,
873
874 BRAAZ = UnconditionalBranchToRegisterFixed | 0x001F0800,
875 BRABZ = UnconditionalBranchToRegisterFixed | 0x001F0C00,
876 BLRAAZ = UnconditionalBranchToRegisterFixed | 0x003F0800,
877 BLRABZ = UnconditionalBranchToRegisterFixed | 0x003F0C00,
878 RETAA = UnconditionalBranchToRegisterFixed | 0x005F0800,
879 RETAB = UnconditionalBranchToRegisterFixed | 0x005F0C00,
880 BRAA = UnconditionalBranchToRegisterFixed | 0x011F0800,
881 BRAB = UnconditionalBranchToRegisterFixed | 0x011F0C00,
882 BLRAA = UnconditionalBranchToRegisterFixed | 0x013F0800,
883 BLRAB = UnconditionalBranchToRegisterFixed | 0x013F0C00
884 };
885
886 // Compare and branch.
887 enum CompareBranchOp {
888 CompareBranchFixed = 0x34000000,
889 CompareBranchFMask = 0x7E000000,
890 CompareBranchMask = 0xFF000000,
891 CBZ_w = CompareBranchFixed | 0x00000000,
892 CBZ_x = CompareBranchFixed | 0x80000000,
893 CBZ = CBZ_w,
894 CBNZ_w = CompareBranchFixed | 0x01000000,
895 CBNZ_x = CompareBranchFixed | 0x81000000,
896 CBNZ = CBNZ_w
897 };
898
899 // Test and branch.
900 enum TestBranchOp {
901 TestBranchFixed = 0x36000000,
902 TestBranchFMask = 0x7E000000,
903 TestBranchMask = 0x7F000000,
904 TBZ = TestBranchFixed | 0x00000000,
905 TBNZ = TestBranchFixed | 0x01000000
906 };
907
908 // Conditional branch.
909 enum ConditionalBranchOp {
910 ConditionalBranchFixed = 0x54000000,
911 ConditionalBranchFMask = 0xFE000000,
912 ConditionalBranchMask = 0xFF000010,
913 B_cond = ConditionalBranchFixed | 0x00000000
914 };
915
916 // System.
917 // System instruction encoding is complicated because some instructions use op
918 // and CR fields to encode parameters. To handle this cleanly, the system
919 // instructions are split into more than one enum.
920
921 enum SystemOp {
922 SystemFixed = 0xD5000000,
923 SystemFMask = 0xFFC00000
924 };
925
926 enum SystemSysRegOp {
927 SystemSysRegFixed = 0xD5100000,
928 SystemSysRegFMask = 0xFFD00000,
929 SystemSysRegMask = 0xFFF00000,
930 MRS = SystemSysRegFixed | 0x00200000,
931 MSR = SystemSysRegFixed | 0x00000000
932 };
933
934 enum SystemPStateOp {
935 SystemPStateFixed = 0xD5004000,
936 SystemPStateFMask = 0xFFF8F000,
937 SystemPStateMask = 0xFFFFF0FF,
938 CFINV = SystemPStateFixed | 0x0000001F,
939 XAFLAG = SystemPStateFixed | 0x0000003F,
940 AXFLAG = SystemPStateFixed | 0x0000005F
941 };
942
943 enum SystemHintOp {
944 SystemHintFixed = 0xD503201F,
945 SystemHintFMask = 0xFFFFF01F,
946 SystemHintMask = 0xFFFFF01F,
947 HINT = SystemHintFixed | 0x00000000
948 };
949
950 enum SystemSysOp {
951 SystemSysFixed = 0xD5080000,
952 SystemSysFMask = 0xFFF80000,
953 SystemSysMask = 0xFFF80000,
954 SYS = SystemSysFixed | 0x00000000,
955 SYSL = SystemSysFixed | 0x00200000
956 };
957
958 // Exception.
959 enum ExceptionOp {
960 ExceptionFixed = 0xD4000000,
961 ExceptionFMask = 0xFF000000,
962 ExceptionMask = 0xFFE0001F,
963 HLT = ExceptionFixed | 0x00400000,
964 BRK = ExceptionFixed | 0x00200000,
965 SVC = ExceptionFixed | 0x00000001,
966 HVC = ExceptionFixed | 0x00000002,
967 SMC = ExceptionFixed | 0x00000003,
968 DCPS1 = ExceptionFixed | 0x00A00001,
969 DCPS2 = ExceptionFixed | 0x00A00002,
970 DCPS3 = ExceptionFixed | 0x00A00003
971 };
972
973 enum MemBarrierOp {
974 MemBarrierFixed = 0xD503309F,
975 MemBarrierFMask = 0xFFFFF09F,
976 MemBarrierMask = 0xFFFFF0FF,
977 DSB = MemBarrierFixed | 0x00000000,
978 DMB = MemBarrierFixed | 0x00000020,
979 ISB = MemBarrierFixed | 0x00000040
980 };
981
982 enum SystemExclusiveMonitorOp {
983 SystemExclusiveMonitorFixed = 0xD503305F,
984 SystemExclusiveMonitorFMask = 0xFFFFF0FF,
985 SystemExclusiveMonitorMask = 0xFFFFF0FF,
986 CLREX = SystemExclusiveMonitorFixed
987 };
988
989 enum SystemPAuthOp {
990 SystemPAuthFixed = 0xD503211F,
991 SystemPAuthFMask = 0xFFFFFD1F,
992 SystemPAuthMask = 0xFFFFFFFF,
993 PACIA1716 = SystemPAuthFixed | 0x00000100,
994 PACIB1716 = SystemPAuthFixed | 0x00000140,
995 AUTIA1716 = SystemPAuthFixed | 0x00000180,
996 AUTIB1716 = SystemPAuthFixed | 0x000001C0,
997 PACIAZ = SystemPAuthFixed | 0x00000300,
998 PACIASP = SystemPAuthFixed | 0x00000320,
999 PACIBZ = SystemPAuthFixed | 0x00000340,
1000 PACIBSP = SystemPAuthFixed | 0x00000360,
1001 AUTIAZ = SystemPAuthFixed | 0x00000380,
1002 AUTIASP = SystemPAuthFixed | 0x000003A0,
1003 AUTIBZ = SystemPAuthFixed | 0x000003C0,
1004 AUTIBSP = SystemPAuthFixed | 0x000003E0,
1005
1006 // XPACLRI has the same fixed mask as System Hints and needs to be handled
1007 // differently.
1008 XPACLRI = 0xD50320FF
1009 };
1010
1011 // Any load or store.
1012 enum LoadStoreAnyOp {
1013 LoadStoreAnyFMask = 0x0a000000,
1014 LoadStoreAnyFixed = 0x08000000
1015 };
1016
1017 // Any load pair or store pair.
1018 enum LoadStorePairAnyOp {
1019 LoadStorePairAnyFMask = 0x3a000000,
1020 LoadStorePairAnyFixed = 0x28000000
1021 };
1022
1023 #define LOAD_STORE_PAIR_OP_LIST(V) \
1024 V(STP, w, 0x00000000), \
1025 V(LDP, w, 0x00400000), \
1026 V(LDPSW, x, 0x40400000), \
1027 V(STP, x, 0x80000000), \
1028 V(LDP, x, 0x80400000), \
1029 V(STP, s, 0x04000000), \
1030 V(LDP, s, 0x04400000), \
1031 V(STP, d, 0x44000000), \
1032 V(LDP, d, 0x44400000), \
1033 V(STP, q, 0x84000000), \
1034 V(LDP, q, 0x84400000)
1035
1036 // Load/store pair (post, pre and offset.)
1037 enum LoadStorePairOp {
1038 LoadStorePairMask = 0xC4400000,
1039 LoadStorePairLBit = 1 << 22,
1040 #define LOAD_STORE_PAIR(A, B, C) \
1041 A##_##B = C
1042 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR)
1043 #undef LOAD_STORE_PAIR
1044 };
1045
1046 enum LoadStorePairPostIndexOp {
1047 LoadStorePairPostIndexFixed = 0x28800000,
1048 LoadStorePairPostIndexFMask = 0x3B800000,
1049 LoadStorePairPostIndexMask = 0xFFC00000,
1050 #define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \
1051 A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B
1052 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX)
1053 #undef LOAD_STORE_PAIR_POST_INDEX
1054 };
1055
1056 enum LoadStorePairPreIndexOp {
1057 LoadStorePairPreIndexFixed = 0x29800000,
1058 LoadStorePairPreIndexFMask = 0x3B800000,
1059 LoadStorePairPreIndexMask = 0xFFC00000,
1060 #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \
1061 A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B
1062 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX)
1063 #undef LOAD_STORE_PAIR_PRE_INDEX
1064 };
1065
1066 enum LoadStorePairOffsetOp {
1067 LoadStorePairOffsetFixed = 0x29000000,
1068 LoadStorePairOffsetFMask = 0x3B800000,
1069 LoadStorePairOffsetMask = 0xFFC00000,
1070 #define LOAD_STORE_PAIR_OFFSET(A, B, C) \
1071 A##_##B##_off = LoadStorePairOffsetFixed | A##_##B
1072 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET)
1073 #undef LOAD_STORE_PAIR_OFFSET
1074 };
1075
1076 enum LoadStorePairNonTemporalOp {
1077 LoadStorePairNonTemporalFixed = 0x28000000,
1078 LoadStorePairNonTemporalFMask = 0x3B800000,
1079 LoadStorePairNonTemporalMask = 0xFFC00000,
1080 LoadStorePairNonTemporalLBit = 1 << 22,
1081 STNP_w = LoadStorePairNonTemporalFixed | STP_w,
1082 LDNP_w = LoadStorePairNonTemporalFixed | LDP_w,
1083 STNP_x = LoadStorePairNonTemporalFixed | STP_x,
1084 LDNP_x = LoadStorePairNonTemporalFixed | LDP_x,
1085 STNP_s = LoadStorePairNonTemporalFixed | STP_s,
1086 LDNP_s = LoadStorePairNonTemporalFixed | LDP_s,
1087 STNP_d = LoadStorePairNonTemporalFixed | STP_d,
1088 LDNP_d = LoadStorePairNonTemporalFixed | LDP_d,
1089 STNP_q = LoadStorePairNonTemporalFixed | STP_q,
1090 LDNP_q = LoadStorePairNonTemporalFixed | LDP_q
1091 };
1092
1093 // Load with pointer authentication.
1094 enum LoadStorePACOp {
1095 LoadStorePACFixed = 0xF8200400,
1096 LoadStorePACFMask = 0xFF200400,
1097 LoadStorePACMask = 0xFFA00C00,
1098 LoadStorePACPreBit = 0x00000800,
1099 LDRAA = LoadStorePACFixed | 0x00000000,
1100 LDRAA_pre = LoadStorePACPreBit | LDRAA,
1101 LDRAB = LoadStorePACFixed | 0x00800000,
1102 LDRAB_pre = LoadStorePACPreBit | LDRAB
1103 };
1104
1105 // Load literal.
1106 enum LoadLiteralOp {
1107 LoadLiteralFixed = 0x18000000,
1108 LoadLiteralFMask = 0x3B000000,
1109 LoadLiteralMask = 0xFF000000,
1110 LDR_w_lit = LoadLiteralFixed | 0x00000000,
1111 LDR_x_lit = LoadLiteralFixed | 0x40000000,
1112 LDRSW_x_lit = LoadLiteralFixed | 0x80000000,
1113 PRFM_lit = LoadLiteralFixed | 0xC0000000,
1114 LDR_s_lit = LoadLiteralFixed | 0x04000000,
1115 LDR_d_lit = LoadLiteralFixed | 0x44000000,
1116 LDR_q_lit = LoadLiteralFixed | 0x84000000
1117 };
1118
1119 #define LOAD_STORE_OP_LIST(V) \
1120 V(ST, RB, w, 0x00000000), \
1121 V(ST, RH, w, 0x40000000), \
1122 V(ST, R, w, 0x80000000), \
1123 V(ST, R, x, 0xC0000000), \
1124 V(LD, RB, w, 0x00400000), \
1125 V(LD, RH, w, 0x40400000), \
1126 V(LD, R, w, 0x80400000), \
1127 V(LD, R, x, 0xC0400000), \
1128 V(LD, RSB, x, 0x00800000), \
1129 V(LD, RSH, x, 0x40800000), \
1130 V(LD, RSW, x, 0x80800000), \
1131 V(LD, RSB, w, 0x00C00000), \
1132 V(LD, RSH, w, 0x40C00000), \
1133 V(ST, R, b, 0x04000000), \
1134 V(ST, R, h, 0x44000000), \
1135 V(ST, R, s, 0x84000000), \
1136 V(ST, R, d, 0xC4000000), \
1137 V(ST, R, q, 0x04800000), \
1138 V(LD, R, b, 0x04400000), \
1139 V(LD, R, h, 0x44400000), \
1140 V(LD, R, s, 0x84400000), \
1141 V(LD, R, d, 0xC4400000), \
1142 V(LD, R, q, 0x04C00000)
1143
1144 // Load/store (post, pre, offset and unsigned.)
1145 enum LoadStoreOp {
1146 LoadStoreMask = 0xC4C00000,
1147 LoadStoreVMask = 0x04000000,
1148 #define LOAD_STORE(A, B, C, D) \
1149 A##B##_##C = D
1150 LOAD_STORE_OP_LIST(LOAD_STORE),
1151 #undef LOAD_STORE
1152 PRFM = 0xC0800000
1153 };
1154
1155 // Load/store unscaled offset.
1156 enum LoadStoreUnscaledOffsetOp {
1157 LoadStoreUnscaledOffsetFixed = 0x38000000,
1158 LoadStoreUnscaledOffsetFMask = 0x3B200C00,
1159 LoadStoreUnscaledOffsetMask = 0xFFE00C00,
1160 PRFUM = LoadStoreUnscaledOffsetFixed | PRFM,
1161 #define LOAD_STORE_UNSCALED(A, B, C, D) \
1162 A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D
1163 LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED)
1164 #undef LOAD_STORE_UNSCALED
1165 };
1166
1167 // Load/store post index.
1168 enum LoadStorePostIndex {
1169 LoadStorePostIndexFixed = 0x38000400,
1170 LoadStorePostIndexFMask = 0x3B200C00,
1171 LoadStorePostIndexMask = 0xFFE00C00,
1172 #define LOAD_STORE_POST_INDEX(A, B, C, D) \
1173 A##B##_##C##_post = LoadStorePostIndexFixed | D
1174 LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX)
1175 #undef LOAD_STORE_POST_INDEX
1176 };
1177
1178 // Load/store pre index.
1179 enum LoadStorePreIndex {
1180 LoadStorePreIndexFixed = 0x38000C00,
1181 LoadStorePreIndexFMask = 0x3B200C00,
1182 LoadStorePreIndexMask = 0xFFE00C00,
1183 #define LOAD_STORE_PRE_INDEX(A, B, C, D) \
1184 A##B##_##C##_pre = LoadStorePreIndexFixed | D
1185 LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX)
1186 #undef LOAD_STORE_PRE_INDEX
1187 };
1188
1189 // Load/store unsigned offset.
1190 enum LoadStoreUnsignedOffset {
1191 LoadStoreUnsignedOffsetFixed = 0x39000000,
1192 LoadStoreUnsignedOffsetFMask = 0x3B000000,
1193 LoadStoreUnsignedOffsetMask = 0xFFC00000,
1194 PRFM_unsigned = LoadStoreUnsignedOffsetFixed | PRFM,
1195 #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \
1196 A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D
1197 LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET)
1198 #undef LOAD_STORE_UNSIGNED_OFFSET
1199 };
1200
1201 // Load/store register offset.
1202 enum LoadStoreRegisterOffset {
1203 LoadStoreRegisterOffsetFixed = 0x38200800,
1204 LoadStoreRegisterOffsetFMask = 0x3B200C00,
1205 LoadStoreRegisterOffsetMask = 0xFFE00C00,
1206 PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM,
1207 #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \
1208 A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D
1209 LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET)
1210 #undef LOAD_STORE_REGISTER_OFFSET
1211 };
1212
1213 enum LoadStoreExclusive {
1214 LoadStoreExclusiveFixed = 0x08000000,
1215 LoadStoreExclusiveFMask = 0x3F000000,
1216 LoadStoreExclusiveMask = 0xFFE08000,
1217 STXRB_w = LoadStoreExclusiveFixed | 0x00000000,
1218 STXRH_w = LoadStoreExclusiveFixed | 0x40000000,
1219 STXR_w = LoadStoreExclusiveFixed | 0x80000000,
1220 STXR_x = LoadStoreExclusiveFixed | 0xC0000000,
1221 LDXRB_w = LoadStoreExclusiveFixed | 0x00400000,
1222 LDXRH_w = LoadStoreExclusiveFixed | 0x40400000,
1223 LDXR_w = LoadStoreExclusiveFixed | 0x80400000,
1224 LDXR_x = LoadStoreExclusiveFixed | 0xC0400000,
1225 STXP_w = LoadStoreExclusiveFixed | 0x80200000,
1226 STXP_x = LoadStoreExclusiveFixed | 0xC0200000,
1227 LDXP_w = LoadStoreExclusiveFixed | 0x80600000,
1228 LDXP_x = LoadStoreExclusiveFixed | 0xC0600000,
1229 STLXRB_w = LoadStoreExclusiveFixed | 0x00008000,
1230 STLXRH_w = LoadStoreExclusiveFixed | 0x40008000,
1231 STLXR_w = LoadStoreExclusiveFixed | 0x80008000,
1232 STLXR_x = LoadStoreExclusiveFixed | 0xC0008000,
1233 LDAXRB_w = LoadStoreExclusiveFixed | 0x00408000,
1234 LDAXRH_w = LoadStoreExclusiveFixed | 0x40408000,
1235 LDAXR_w = LoadStoreExclusiveFixed | 0x80408000,
1236 LDAXR_x = LoadStoreExclusiveFixed | 0xC0408000,
1237 STLXP_w = LoadStoreExclusiveFixed | 0x80208000,
1238 STLXP_x = LoadStoreExclusiveFixed | 0xC0208000,
1239 LDAXP_w = LoadStoreExclusiveFixed | 0x80608000,
1240 LDAXP_x = LoadStoreExclusiveFixed | 0xC0608000,
1241 STLRB_w = LoadStoreExclusiveFixed | 0x00808000,
1242 STLRH_w = LoadStoreExclusiveFixed | 0x40808000,
1243 STLR_w = LoadStoreExclusiveFixed | 0x80808000,
1244 STLR_x = LoadStoreExclusiveFixed | 0xC0808000,
1245 LDARB_w = LoadStoreExclusiveFixed | 0x00C08000,
1246 LDARH_w = LoadStoreExclusiveFixed | 0x40C08000,
1247 LDAR_w = LoadStoreExclusiveFixed | 0x80C08000,
1248 LDAR_x = LoadStoreExclusiveFixed | 0xC0C08000,
1249
1250 // v8.1 Load/store LORegion ops
1251 STLLRB = LoadStoreExclusiveFixed | 0x00800000,
1252 LDLARB = LoadStoreExclusiveFixed | 0x00C00000,
1253 STLLRH = LoadStoreExclusiveFixed | 0x40800000,
1254 LDLARH = LoadStoreExclusiveFixed | 0x40C00000,
1255 STLLR_w = LoadStoreExclusiveFixed | 0x80800000,
1256 LDLAR_w = LoadStoreExclusiveFixed | 0x80C00000,
1257 STLLR_x = LoadStoreExclusiveFixed | 0xC0800000,
1258 LDLAR_x = LoadStoreExclusiveFixed | 0xC0C00000,
1259
1260 // v8.1 Load/store exclusive ops
1261 LSEBit_l = 0x00400000,
1262 LSEBit_o0 = 0x00008000,
1263 LSEBit_sz = 0x40000000,
1264 CASFixed = LoadStoreExclusiveFixed | 0x80A00000,
1265 CASBFixed = LoadStoreExclusiveFixed | 0x00A00000,
1266 CASHFixed = LoadStoreExclusiveFixed | 0x40A00000,
1267 CASPFixed = LoadStoreExclusiveFixed | 0x00200000,
1268 CAS_w = CASFixed,
1269 CAS_x = CASFixed | LSEBit_sz,
1270 CASA_w = CASFixed | LSEBit_l,
1271 CASA_x = CASFixed | LSEBit_l | LSEBit_sz,
1272 CASL_w = CASFixed | LSEBit_o0,
1273 CASL_x = CASFixed | LSEBit_o0 | LSEBit_sz,
1274 CASAL_w = CASFixed | LSEBit_l | LSEBit_o0,
1275 CASAL_x = CASFixed | LSEBit_l | LSEBit_o0 | LSEBit_sz,
1276 CASB = CASBFixed,
1277 CASAB = CASBFixed | LSEBit_l,
1278 CASLB = CASBFixed | LSEBit_o0,
1279 CASALB = CASBFixed | LSEBit_l | LSEBit_o0,
1280 CASH = CASHFixed,
1281 CASAH = CASHFixed | LSEBit_l,
1282 CASLH = CASHFixed | LSEBit_o0,
1283 CASALH = CASHFixed | LSEBit_l | LSEBit_o0,
1284 CASP_w = CASPFixed,
1285 CASP_x = CASPFixed | LSEBit_sz,
1286 CASPA_w = CASPFixed | LSEBit_l,
1287 CASPA_x = CASPFixed | LSEBit_l | LSEBit_sz,
1288 CASPL_w = CASPFixed | LSEBit_o0,
1289 CASPL_x = CASPFixed | LSEBit_o0 | LSEBit_sz,
1290 CASPAL_w = CASPFixed | LSEBit_l | LSEBit_o0,
1291 CASPAL_x = CASPFixed | LSEBit_l | LSEBit_o0 | LSEBit_sz
1292 };
1293
1294 // Load/store RCpc unscaled offset.
1295 enum LoadStoreRCpcUnscaledOffsetOp {
1296 LoadStoreRCpcUnscaledOffsetFixed = 0x19000000,
1297 LoadStoreRCpcUnscaledOffsetFMask = 0x3F200C00,
1298 LoadStoreRCpcUnscaledOffsetMask = 0xFFE00C00,
1299 STLURB = LoadStoreRCpcUnscaledOffsetFixed | 0x00000000,
1300 LDAPURB = LoadStoreRCpcUnscaledOffsetFixed | 0x00400000,
1301 LDAPURSB_x = LoadStoreRCpcUnscaledOffsetFixed | 0x00800000,
1302 LDAPURSB_w = LoadStoreRCpcUnscaledOffsetFixed | 0x00C00000,
1303 STLURH = LoadStoreRCpcUnscaledOffsetFixed | 0x40000000,
1304 LDAPURH = LoadStoreRCpcUnscaledOffsetFixed | 0x40400000,
1305 LDAPURSH_x = LoadStoreRCpcUnscaledOffsetFixed | 0x40800000,
1306 LDAPURSH_w = LoadStoreRCpcUnscaledOffsetFixed | 0x40C00000,
1307 STLUR_w = LoadStoreRCpcUnscaledOffsetFixed | 0x80000000,
1308 LDAPUR_w = LoadStoreRCpcUnscaledOffsetFixed | 0x80400000,
1309 LDAPURSW = LoadStoreRCpcUnscaledOffsetFixed | 0x80800000,
1310 STLUR_x = LoadStoreRCpcUnscaledOffsetFixed | 0xC0000000,
1311 LDAPUR_x = LoadStoreRCpcUnscaledOffsetFixed | 0xC0400000
1312 };
1313
1314 #define ATOMIC_MEMORY_SIMPLE_OPC_LIST(V) \
1315 V(LDADD, 0x00000000), \
1316 V(LDCLR, 0x00001000), \
1317 V(LDEOR, 0x00002000), \
1318 V(LDSET, 0x00003000), \
1319 V(LDSMAX, 0x00004000), \
1320 V(LDSMIN, 0x00005000), \
1321 V(LDUMAX, 0x00006000), \
1322 V(LDUMIN, 0x00007000)
1323
1324 // Atomic memory.
1325 enum AtomicMemoryOp {
1326 AtomicMemoryFixed = 0x38200000,
1327 AtomicMemoryFMask = 0x3B200C00,
1328 AtomicMemoryMask = 0xFFE0FC00,
1329 SWPB = AtomicMemoryFixed | 0x00008000,
1330 SWPAB = AtomicMemoryFixed | 0x00808000,
1331 SWPLB = AtomicMemoryFixed | 0x00408000,
1332 SWPALB = AtomicMemoryFixed | 0x00C08000,
1333 SWPH = AtomicMemoryFixed | 0x40008000,
1334 SWPAH = AtomicMemoryFixed | 0x40808000,
1335 SWPLH = AtomicMemoryFixed | 0x40408000,
1336 SWPALH = AtomicMemoryFixed | 0x40C08000,
1337 SWP_w = AtomicMemoryFixed | 0x80008000,
1338 SWPA_w = AtomicMemoryFixed | 0x80808000,
1339 SWPL_w = AtomicMemoryFixed | 0x80408000,
1340 SWPAL_w = AtomicMemoryFixed | 0x80C08000,
1341 SWP_x = AtomicMemoryFixed | 0xC0008000,
1342 SWPA_x = AtomicMemoryFixed | 0xC0808000,
1343 SWPL_x = AtomicMemoryFixed | 0xC0408000,
1344 SWPAL_x = AtomicMemoryFixed | 0xC0C08000,
1345 LDAPRB = AtomicMemoryFixed | 0x0080C000,
1346 LDAPRH = AtomicMemoryFixed | 0x4080C000,
1347 LDAPR_w = AtomicMemoryFixed | 0x8080C000,
1348 LDAPR_x = AtomicMemoryFixed | 0xC080C000,
1349
1350 AtomicMemorySimpleFMask = 0x3B208C00,
1351 AtomicMemorySimpleOpMask = 0x00007000,
1352 #define ATOMIC_MEMORY_SIMPLE(N, OP) \
1353 N##Op = OP, \
1354 N##B = AtomicMemoryFixed | OP, \
1355 N##AB = AtomicMemoryFixed | OP | 0x00800000, \
1356 N##LB = AtomicMemoryFixed | OP | 0x00400000, \
1357 N##ALB = AtomicMemoryFixed | OP | 0x00C00000, \
1358 N##H = AtomicMemoryFixed | OP | 0x40000000, \
1359 N##AH = AtomicMemoryFixed | OP | 0x40800000, \
1360 N##LH = AtomicMemoryFixed | OP | 0x40400000, \
1361 N##ALH = AtomicMemoryFixed | OP | 0x40C00000, \
1362 N##_w = AtomicMemoryFixed | OP | 0x80000000, \
1363 N##A_w = AtomicMemoryFixed | OP | 0x80800000, \
1364 N##L_w = AtomicMemoryFixed | OP | 0x80400000, \
1365 N##AL_w = AtomicMemoryFixed | OP | 0x80C00000, \
1366 N##_x = AtomicMemoryFixed | OP | 0xC0000000, \
1367 N##A_x = AtomicMemoryFixed | OP | 0xC0800000, \
1368 N##L_x = AtomicMemoryFixed | OP | 0xC0400000, \
1369 N##AL_x = AtomicMemoryFixed | OP | 0xC0C00000
1370
1371 ATOMIC_MEMORY_SIMPLE_OPC_LIST(ATOMIC_MEMORY_SIMPLE)
1372 #undef ATOMIC_MEMORY_SIMPLE
1373 };
1374
1375 // Conditional compare.
1376 enum ConditionalCompareOp {
1377 ConditionalCompareMask = 0x60000000,
1378 CCMN = 0x20000000,
1379 CCMP = 0x60000000
1380 };
1381
1382 // Conditional compare register.
1383 enum ConditionalCompareRegisterOp {
1384 ConditionalCompareRegisterFixed = 0x1A400000,
1385 ConditionalCompareRegisterFMask = 0x1FE00800,
1386 ConditionalCompareRegisterMask = 0xFFE00C10,
1387 CCMN_w = ConditionalCompareRegisterFixed | CCMN,
1388 CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN,
1389 CCMP_w = ConditionalCompareRegisterFixed | CCMP,
1390 CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP
1391 };
1392
1393 // Conditional compare immediate.
1394 enum ConditionalCompareImmediateOp {
1395 ConditionalCompareImmediateFixed = 0x1A400800,
1396 ConditionalCompareImmediateFMask = 0x1FE00800,
1397 ConditionalCompareImmediateMask = 0xFFE00C10,
1398 CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN,
1399 CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN,
1400 CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP,
1401 CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP
1402 };
1403
1404 // Conditional select.
1405 enum ConditionalSelectOp {
1406 ConditionalSelectFixed = 0x1A800000,
1407 ConditionalSelectFMask = 0x1FE00000,
1408 ConditionalSelectMask = 0xFFE00C00,
1409 CSEL_w = ConditionalSelectFixed | 0x00000000,
1410 CSEL_x = ConditionalSelectFixed | 0x80000000,
1411 CSEL = CSEL_w,
1412 CSINC_w = ConditionalSelectFixed | 0x00000400,
1413 CSINC_x = ConditionalSelectFixed | 0x80000400,
1414 CSINC = CSINC_w,
1415 CSINV_w = ConditionalSelectFixed | 0x40000000,
1416 CSINV_x = ConditionalSelectFixed | 0xC0000000,
1417 CSINV = CSINV_w,
1418 CSNEG_w = ConditionalSelectFixed | 0x40000400,
1419 CSNEG_x = ConditionalSelectFixed | 0xC0000400,
1420 CSNEG = CSNEG_w
1421 };
1422
1423 // Data processing 1 source.
1424 enum DataProcessing1SourceOp {
1425 DataProcessing1SourceFixed = 0x5AC00000,
1426 DataProcessing1SourceFMask = 0x5FE00000,
1427 DataProcessing1SourceMask = 0xFFFFFC00,
1428 RBIT = DataProcessing1SourceFixed | 0x00000000,
1429 RBIT_w = RBIT,
1430 RBIT_x = RBIT | SixtyFourBits,
1431 REV16 = DataProcessing1SourceFixed | 0x00000400,
1432 REV16_w = REV16,
1433 REV16_x = REV16 | SixtyFourBits,
1434 REV = DataProcessing1SourceFixed | 0x00000800,
1435 REV_w = REV,
1436 REV32_x = REV | SixtyFourBits,
1437 REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00,
1438 CLZ = DataProcessing1SourceFixed | 0x00001000,
1439 CLZ_w = CLZ,
1440 CLZ_x = CLZ | SixtyFourBits,
1441 CLS = DataProcessing1SourceFixed | 0x00001400,
1442 CLS_w = CLS,
1443 CLS_x = CLS | SixtyFourBits,
1444
1445 // Pointer authentication instructions in Armv8.3.
1446 PACIA = DataProcessing1SourceFixed | 0x80010000,
1447 PACIB = DataProcessing1SourceFixed | 0x80010400,
1448 PACDA = DataProcessing1SourceFixed | 0x80010800,
1449 PACDB = DataProcessing1SourceFixed | 0x80010C00,
1450 AUTIA = DataProcessing1SourceFixed | 0x80011000,
1451 AUTIB = DataProcessing1SourceFixed | 0x80011400,
1452 AUTDA = DataProcessing1SourceFixed | 0x80011800,
1453 AUTDB = DataProcessing1SourceFixed | 0x80011C00,
1454 PACIZA = DataProcessing1SourceFixed | 0x80012000,
1455 PACIZB = DataProcessing1SourceFixed | 0x80012400,
1456 PACDZA = DataProcessing1SourceFixed | 0x80012800,
1457 PACDZB = DataProcessing1SourceFixed | 0x80012C00,
1458 AUTIZA = DataProcessing1SourceFixed | 0x80013000,
1459 AUTIZB = DataProcessing1SourceFixed | 0x80013400,
1460 AUTDZA = DataProcessing1SourceFixed | 0x80013800,
1461 AUTDZB = DataProcessing1SourceFixed | 0x80013C00,
1462 XPACI = DataProcessing1SourceFixed | 0x80014000,
1463 XPACD = DataProcessing1SourceFixed | 0x80014400
1464 };
1465
1466 // Data processing 2 source.
1467 enum DataProcessing2SourceOp {
1468 DataProcessing2SourceFixed = 0x1AC00000,
1469 DataProcessing2SourceFMask = 0x5FE00000,
1470 DataProcessing2SourceMask = 0xFFE0FC00,
1471 UDIV_w = DataProcessing2SourceFixed | 0x00000800,
1472 UDIV_x = DataProcessing2SourceFixed | 0x80000800,
1473 UDIV = UDIV_w,
1474 SDIV_w = DataProcessing2SourceFixed | 0x00000C00,
1475 SDIV_x = DataProcessing2SourceFixed | 0x80000C00,
1476 SDIV = SDIV_w,
1477 LSLV_w = DataProcessing2SourceFixed | 0x00002000,
1478 LSLV_x = DataProcessing2SourceFixed | 0x80002000,
1479 LSLV = LSLV_w,
1480 LSRV_w = DataProcessing2SourceFixed | 0x00002400,
1481 LSRV_x = DataProcessing2SourceFixed | 0x80002400,
1482 LSRV = LSRV_w,
1483 ASRV_w = DataProcessing2SourceFixed | 0x00002800,
1484 ASRV_x = DataProcessing2SourceFixed | 0x80002800,
1485 ASRV = ASRV_w,
1486 RORV_w = DataProcessing2SourceFixed | 0x00002C00,
1487 RORV_x = DataProcessing2SourceFixed | 0x80002C00,
1488 RORV = RORV_w,
1489 PACGA = DataProcessing2SourceFixed | SixtyFourBits | 0x00003000,
1490 CRC32B = DataProcessing2SourceFixed | 0x00004000,
1491 CRC32H = DataProcessing2SourceFixed | 0x00004400,
1492 CRC32W = DataProcessing2SourceFixed | 0x00004800,
1493 CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00,
1494 CRC32CB = DataProcessing2SourceFixed | 0x00005000,
1495 CRC32CH = DataProcessing2SourceFixed | 0x00005400,
1496 CRC32CW = DataProcessing2SourceFixed | 0x00005800,
1497 CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00
1498 };
1499
1500 // Data processing 3 source.
1501 enum DataProcessing3SourceOp {
1502 DataProcessing3SourceFixed = 0x1B000000,
1503 DataProcessing3SourceFMask = 0x1F000000,
1504 DataProcessing3SourceMask = 0xFFE08000,
1505 MADD_w = DataProcessing3SourceFixed | 0x00000000,
1506 MADD_x = DataProcessing3SourceFixed | 0x80000000,
1507 MADD = MADD_w,
1508 MSUB_w = DataProcessing3SourceFixed | 0x00008000,
1509 MSUB_x = DataProcessing3SourceFixed | 0x80008000,
1510 MSUB = MSUB_w,
1511 SMADDL_x = DataProcessing3SourceFixed | 0x80200000,
1512 SMSUBL_x = DataProcessing3SourceFixed | 0x80208000,
1513 SMULH_x = DataProcessing3SourceFixed | 0x80400000,
1514 UMADDL_x = DataProcessing3SourceFixed | 0x80A00000,
1515 UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000,
1516 UMULH_x = DataProcessing3SourceFixed | 0x80C00000
1517 };
1518
1519 // Floating point compare.
1520 enum FPCompareOp {
1521 FPCompareFixed = 0x1E202000,
1522 FPCompareFMask = 0x5F203C00,
1523 FPCompareMask = 0xFFE0FC1F,
1524 FCMP_h = FPCompareFixed | FP16 | 0x00000000,
1525 FCMP_s = FPCompareFixed | 0x00000000,
1526 FCMP_d = FPCompareFixed | FP64 | 0x00000000,
1527 FCMP = FCMP_s,
1528 FCMP_h_zero = FPCompareFixed | FP16 | 0x00000008,
1529 FCMP_s_zero = FPCompareFixed | 0x00000008,
1530 FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008,
1531 FCMP_zero = FCMP_s_zero,
1532 FCMPE_h = FPCompareFixed | FP16 | 0x00000010,
1533 FCMPE_s = FPCompareFixed | 0x00000010,
1534 FCMPE_d = FPCompareFixed | FP64 | 0x00000010,
1535 FCMPE = FCMPE_s,
1536 FCMPE_h_zero = FPCompareFixed | FP16 | 0x00000018,
1537 FCMPE_s_zero = FPCompareFixed | 0x00000018,
1538 FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018,
1539 FCMPE_zero = FCMPE_s_zero
1540 };
1541
1542 // Floating point conditional compare.
1543 enum FPConditionalCompareOp {
1544 FPConditionalCompareFixed = 0x1E200400,
1545 FPConditionalCompareFMask = 0x5F200C00,
1546 FPConditionalCompareMask = 0xFFE00C10,
1547 FCCMP_h = FPConditionalCompareFixed | FP16 | 0x00000000,
1548 FCCMP_s = FPConditionalCompareFixed | 0x00000000,
1549 FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000,
1550 FCCMP = FCCMP_s,
1551 FCCMPE_h = FPConditionalCompareFixed | FP16 | 0x00000010,
1552 FCCMPE_s = FPConditionalCompareFixed | 0x00000010,
1553 FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010,
1554 FCCMPE = FCCMPE_s
1555 };
1556
1557 // Floating point conditional select.
1558 enum FPConditionalSelectOp {
1559 FPConditionalSelectFixed = 0x1E200C00,
1560 FPConditionalSelectFMask = 0x5F200C00,
1561 FPConditionalSelectMask = 0xFFE00C00,
1562 FCSEL_h = FPConditionalSelectFixed | FP16 | 0x00000000,
1563 FCSEL_s = FPConditionalSelectFixed | 0x00000000,
1564 FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000,
1565 FCSEL = FCSEL_s
1566 };
1567
1568 // Floating point immediate.
1569 enum FPImmediateOp {
1570 FPImmediateFixed = 0x1E201000,
1571 FPImmediateFMask = 0x5F201C00,
1572 FPImmediateMask = 0xFFE01C00,
1573 FMOV_h_imm = FPImmediateFixed | FP16 | 0x00000000,
1574 FMOV_s_imm = FPImmediateFixed | 0x00000000,
1575 FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000
1576 };
1577
1578 // Floating point data processing 1 source.
1579 enum FPDataProcessing1SourceOp {
1580 FPDataProcessing1SourceFixed = 0x1E204000,
1581 FPDataProcessing1SourceFMask = 0x5F207C00,
1582 FPDataProcessing1SourceMask = 0xFFFFFC00,
1583 FMOV_h = FPDataProcessing1SourceFixed | FP16 | 0x00000000,
1584 FMOV_s = FPDataProcessing1SourceFixed | 0x00000000,
1585 FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000,
1586 FMOV = FMOV_s,
1587 FABS_h = FPDataProcessing1SourceFixed | FP16 | 0x00008000,
1588 FABS_s = FPDataProcessing1SourceFixed | 0x00008000,
1589 FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000,
1590 FABS = FABS_s,
1591 FNEG_h = FPDataProcessing1SourceFixed | FP16 | 0x00010000,
1592 FNEG_s = FPDataProcessing1SourceFixed | 0x00010000,
1593 FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000,
1594 FNEG = FNEG_s,
1595 FSQRT_h = FPDataProcessing1SourceFixed | FP16 | 0x00018000,
1596 FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000,
1597 FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000,
1598 FSQRT = FSQRT_s,
1599 FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000,
1600 FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000,
1601 FCVT_hs = FPDataProcessing1SourceFixed | 0x00038000,
1602 FCVT_hd = FPDataProcessing1SourceFixed | FP64 | 0x00038000,
1603 FCVT_sh = FPDataProcessing1SourceFixed | 0x00C20000,
1604 FCVT_dh = FPDataProcessing1SourceFixed | 0x00C28000,
1605 FRINT32X_s = FPDataProcessing1SourceFixed | 0x00088000,
1606 FRINT32X_d = FPDataProcessing1SourceFixed | FP64 | 0x00088000,
1607 FRINT32X = FRINT32X_s,
1608 FRINT32Z_s = FPDataProcessing1SourceFixed | 0x00080000,
1609 FRINT32Z_d = FPDataProcessing1SourceFixed | FP64 | 0x00080000,
1610 FRINT32Z = FRINT32Z_s,
1611 FRINT64X_s = FPDataProcessing1SourceFixed | 0x00098000,
1612 FRINT64X_d = FPDataProcessing1SourceFixed | FP64 | 0x00098000,
1613 FRINT64X = FRINT64X_s,
1614 FRINT64Z_s = FPDataProcessing1SourceFixed | 0x00090000,
1615 FRINT64Z_d = FPDataProcessing1SourceFixed | FP64 | 0x00090000,
1616 FRINT64Z = FRINT64Z_s,
1617 FRINTN_h = FPDataProcessing1SourceFixed | FP16 | 0x00040000,
1618 FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000,
1619 FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000,
1620 FRINTN = FRINTN_s,
1621 FRINTP_h = FPDataProcessing1SourceFixed | FP16 | 0x00048000,
1622 FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000,
1623 FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000,
1624 FRINTP = FRINTP_s,
1625 FRINTM_h = FPDataProcessing1SourceFixed | FP16 | 0x00050000,
1626 FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000,
1627 FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000,
1628 FRINTM = FRINTM_s,
1629 FRINTZ_h = FPDataProcessing1SourceFixed | FP16 | 0x00058000,
1630 FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000,
1631 FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000,
1632 FRINTZ = FRINTZ_s,
1633 FRINTA_h = FPDataProcessing1SourceFixed | FP16 | 0x00060000,
1634 FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000,
1635 FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000,
1636 FRINTA = FRINTA_s,
1637 FRINTX_h = FPDataProcessing1SourceFixed | FP16 | 0x00070000,
1638 FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000,
1639 FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000,
1640 FRINTX = FRINTX_s,
1641 FRINTI_h = FPDataProcessing1SourceFixed | FP16 | 0x00078000,
1642 FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000,
1643 FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000,
1644 FRINTI = FRINTI_s
1645 };
1646
1647 // Floating point data processing 2 source.
1648 enum FPDataProcessing2SourceOp {
1649 FPDataProcessing2SourceFixed = 0x1E200800,
1650 FPDataProcessing2SourceFMask = 0x5F200C00,
1651 FPDataProcessing2SourceMask = 0xFFE0FC00,
1652 FMUL = FPDataProcessing2SourceFixed | 0x00000000,
1653 FMUL_h = FMUL | FP16,
1654 FMUL_s = FMUL,
1655 FMUL_d = FMUL | FP64,
1656 FDIV = FPDataProcessing2SourceFixed | 0x00001000,
1657 FDIV_h = FDIV | FP16,
1658 FDIV_s = FDIV,
1659 FDIV_d = FDIV | FP64,
1660 FADD = FPDataProcessing2SourceFixed | 0x00002000,
1661 FADD_h = FADD | FP16,
1662 FADD_s = FADD,
1663 FADD_d = FADD | FP64,
1664 FSUB = FPDataProcessing2SourceFixed | 0x00003000,
1665 FSUB_h = FSUB | FP16,
1666 FSUB_s = FSUB,
1667 FSUB_d = FSUB | FP64,
1668 FMAX = FPDataProcessing2SourceFixed | 0x00004000,
1669 FMAX_h = FMAX | FP16,
1670 FMAX_s = FMAX,
1671 FMAX_d = FMAX | FP64,
1672 FMIN = FPDataProcessing2SourceFixed | 0x00005000,
1673 FMIN_h = FMIN | FP16,
1674 FMIN_s = FMIN,
1675 FMIN_d = FMIN | FP64,
1676 FMAXNM = FPDataProcessing2SourceFixed | 0x00006000,
1677 FMAXNM_h = FMAXNM | FP16,
1678 FMAXNM_s = FMAXNM,
1679 FMAXNM_d = FMAXNM | FP64,
1680 FMINNM = FPDataProcessing2SourceFixed | 0x00007000,
1681 FMINNM_h = FMINNM | FP16,
1682 FMINNM_s = FMINNM,
1683 FMINNM_d = FMINNM | FP64,
1684 FNMUL = FPDataProcessing2SourceFixed | 0x00008000,
1685 FNMUL_h = FNMUL | FP16,
1686 FNMUL_s = FNMUL,
1687 FNMUL_d = FNMUL | FP64
1688 };
1689
1690 // Floating point data processing 3 source.
1691 enum FPDataProcessing3SourceOp {
1692 FPDataProcessing3SourceFixed = 0x1F000000,
1693 FPDataProcessing3SourceFMask = 0x5F000000,
1694 FPDataProcessing3SourceMask = 0xFFE08000,
1695 FMADD_h = FPDataProcessing3SourceFixed | 0x00C00000,
1696 FMSUB_h = FPDataProcessing3SourceFixed | 0x00C08000,
1697 FNMADD_h = FPDataProcessing3SourceFixed | 0x00E00000,
1698 FNMSUB_h = FPDataProcessing3SourceFixed | 0x00E08000,
1699 FMADD_s = FPDataProcessing3SourceFixed | 0x00000000,
1700 FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000,
1701 FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000,
1702 FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000,
1703 FMADD_d = FPDataProcessing3SourceFixed | 0x00400000,
1704 FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000,
1705 FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000,
1706 FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000
1707 };
1708
1709 // Conversion between floating point and integer.
1710 enum FPIntegerConvertOp {
1711 FPIntegerConvertFixed = 0x1E200000,
1712 FPIntegerConvertFMask = 0x5F20FC00,
1713 FPIntegerConvertMask = 0xFFFFFC00,
1714 FCVTNS = FPIntegerConvertFixed | 0x00000000,
1715 FCVTNS_wh = FCVTNS | FP16,
1716 FCVTNS_xh = FCVTNS | SixtyFourBits | FP16,
1717 FCVTNS_ws = FCVTNS,
1718 FCVTNS_xs = FCVTNS | SixtyFourBits,
1719 FCVTNS_wd = FCVTNS | FP64,
1720 FCVTNS_xd = FCVTNS | SixtyFourBits | FP64,
1721 FCVTNU = FPIntegerConvertFixed | 0x00010000,
1722 FCVTNU_wh = FCVTNU | FP16,
1723 FCVTNU_xh = FCVTNU | SixtyFourBits | FP16,
1724 FCVTNU_ws = FCVTNU,
1725 FCVTNU_xs = FCVTNU | SixtyFourBits,
1726 FCVTNU_wd = FCVTNU | FP64,
1727 FCVTNU_xd = FCVTNU | SixtyFourBits | FP64,
1728 FCVTPS = FPIntegerConvertFixed | 0x00080000,
1729 FCVTPS_wh = FCVTPS | FP16,
1730 FCVTPS_xh = FCVTPS | SixtyFourBits | FP16,
1731 FCVTPS_ws = FCVTPS,
1732 FCVTPS_xs = FCVTPS | SixtyFourBits,
1733 FCVTPS_wd = FCVTPS | FP64,
1734 FCVTPS_xd = FCVTPS | SixtyFourBits | FP64,
1735 FCVTPU = FPIntegerConvertFixed | 0x00090000,
1736 FCVTPU_wh = FCVTPU | FP16,
1737 FCVTPU_xh = FCVTPU | SixtyFourBits | FP16,
1738 FCVTPU_ws = FCVTPU,
1739 FCVTPU_xs = FCVTPU | SixtyFourBits,
1740 FCVTPU_wd = FCVTPU | FP64,
1741 FCVTPU_xd = FCVTPU | SixtyFourBits | FP64,
1742 FCVTMS = FPIntegerConvertFixed | 0x00100000,
1743 FCVTMS_wh = FCVTMS | FP16,
1744 FCVTMS_xh = FCVTMS | SixtyFourBits | FP16,
1745 FCVTMS_ws = FCVTMS,
1746 FCVTMS_xs = FCVTMS | SixtyFourBits,
1747 FCVTMS_wd = FCVTMS | FP64,
1748 FCVTMS_xd = FCVTMS | SixtyFourBits | FP64,
1749 FCVTMU = FPIntegerConvertFixed | 0x00110000,
1750 FCVTMU_wh = FCVTMU | FP16,
1751 FCVTMU_xh = FCVTMU | SixtyFourBits | FP16,
1752 FCVTMU_ws = FCVTMU,
1753 FCVTMU_xs = FCVTMU | SixtyFourBits,
1754 FCVTMU_wd = FCVTMU | FP64,
1755 FCVTMU_xd = FCVTMU | SixtyFourBits | FP64,
1756 FCVTZS = FPIntegerConvertFixed | 0x00180000,
1757 FCVTZS_wh = FCVTZS | FP16,
1758 FCVTZS_xh = FCVTZS | SixtyFourBits | FP16,
1759 FCVTZS_ws = FCVTZS,
1760 FCVTZS_xs = FCVTZS | SixtyFourBits,
1761 FCVTZS_wd = FCVTZS | FP64,
1762 FCVTZS_xd = FCVTZS | SixtyFourBits | FP64,
1763 FCVTZU = FPIntegerConvertFixed | 0x00190000,
1764 FCVTZU_wh = FCVTZU | FP16,
1765 FCVTZU_xh = FCVTZU | SixtyFourBits | FP16,
1766 FCVTZU_ws = FCVTZU,
1767 FCVTZU_xs = FCVTZU | SixtyFourBits,
1768 FCVTZU_wd = FCVTZU | FP64,
1769 FCVTZU_xd = FCVTZU | SixtyFourBits | FP64,
1770 SCVTF = FPIntegerConvertFixed | 0x00020000,
1771 SCVTF_hw = SCVTF | FP16,
1772 SCVTF_hx = SCVTF | SixtyFourBits | FP16,
1773 SCVTF_sw = SCVTF,
1774 SCVTF_sx = SCVTF | SixtyFourBits,
1775 SCVTF_dw = SCVTF | FP64,
1776 SCVTF_dx = SCVTF | SixtyFourBits | FP64,
1777 UCVTF = FPIntegerConvertFixed | 0x00030000,
1778 UCVTF_hw = UCVTF | FP16,
1779 UCVTF_hx = UCVTF | SixtyFourBits | FP16,
1780 UCVTF_sw = UCVTF,
1781 UCVTF_sx = UCVTF | SixtyFourBits,
1782 UCVTF_dw = UCVTF | FP64,
1783 UCVTF_dx = UCVTF | SixtyFourBits | FP64,
1784 FCVTAS = FPIntegerConvertFixed | 0x00040000,
1785 FCVTAS_wh = FCVTAS | FP16,
1786 FCVTAS_xh = FCVTAS | SixtyFourBits | FP16,
1787 FCVTAS_ws = FCVTAS,
1788 FCVTAS_xs = FCVTAS | SixtyFourBits,
1789 FCVTAS_wd = FCVTAS | FP64,
1790 FCVTAS_xd = FCVTAS | SixtyFourBits | FP64,
1791 FCVTAU = FPIntegerConvertFixed | 0x00050000,
1792 FCVTAU_wh = FCVTAU | FP16,
1793 FCVTAU_xh = FCVTAU | SixtyFourBits | FP16,
1794 FCVTAU_ws = FCVTAU,
1795 FCVTAU_xs = FCVTAU | SixtyFourBits,
1796 FCVTAU_wd = FCVTAU | FP64,
1797 FCVTAU_xd = FCVTAU | SixtyFourBits | FP64,
1798 FMOV_wh = FPIntegerConvertFixed | 0x00060000 | FP16,
1799 FMOV_hw = FPIntegerConvertFixed | 0x00070000 | FP16,
1800 FMOV_xh = FMOV_wh | SixtyFourBits,
1801 FMOV_hx = FMOV_hw | SixtyFourBits,
1802 FMOV_ws = FPIntegerConvertFixed | 0x00060000,
1803 FMOV_sw = FPIntegerConvertFixed | 0x00070000,
1804 FMOV_xd = FMOV_ws | SixtyFourBits | FP64,
1805 FMOV_dx = FMOV_sw | SixtyFourBits | FP64,
1806 FMOV_d1_x = FPIntegerConvertFixed | SixtyFourBits | 0x008F0000,
1807 FMOV_x_d1 = FPIntegerConvertFixed | SixtyFourBits | 0x008E0000,
1808 FJCVTZS = FPIntegerConvertFixed | FP64 | 0x001E0000
1809 };
1810
1811 // Conversion between fixed point and floating point.
1812 enum FPFixedPointConvertOp {
1813 FPFixedPointConvertFixed = 0x1E000000,
1814 FPFixedPointConvertFMask = 0x5F200000,
1815 FPFixedPointConvertMask = 0xFFFF0000,
1816 FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000,
1817 FCVTZS_wh_fixed = FCVTZS_fixed | FP16,
1818 FCVTZS_xh_fixed = FCVTZS_fixed | SixtyFourBits | FP16,
1819 FCVTZS_ws_fixed = FCVTZS_fixed,
1820 FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits,
1821 FCVTZS_wd_fixed = FCVTZS_fixed | FP64,
1822 FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64,
1823 FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000,
1824 FCVTZU_wh_fixed = FCVTZU_fixed | FP16,
1825 FCVTZU_xh_fixed = FCVTZU_fixed | SixtyFourBits | FP16,
1826 FCVTZU_ws_fixed = FCVTZU_fixed,
1827 FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits,
1828 FCVTZU_wd_fixed = FCVTZU_fixed | FP64,
1829 FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64,
1830 SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000,
1831 SCVTF_hw_fixed = SCVTF_fixed | FP16,
1832 SCVTF_hx_fixed = SCVTF_fixed | SixtyFourBits | FP16,
1833 SCVTF_sw_fixed = SCVTF_fixed,
1834 SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits,
1835 SCVTF_dw_fixed = SCVTF_fixed | FP64,
1836 SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64,
1837 UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000,
1838 UCVTF_hw_fixed = UCVTF_fixed | FP16,
1839 UCVTF_hx_fixed = UCVTF_fixed | SixtyFourBits | FP16,
1840 UCVTF_sw_fixed = UCVTF_fixed,
1841 UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits,
1842 UCVTF_dw_fixed = UCVTF_fixed | FP64,
1843 UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64
1844 };
1845
1846 // Crypto - two register SHA.
1847 enum Crypto2RegSHAOp {
1848 Crypto2RegSHAFixed = 0x5E280800,
1849 Crypto2RegSHAFMask = 0xFF3E0C00
1850 };
1851
1852 // Crypto - three register SHA.
1853 enum Crypto3RegSHAOp {
1854 Crypto3RegSHAFixed = 0x5E000000,
1855 Crypto3RegSHAFMask = 0xFF208C00
1856 };
1857
1858 // Crypto - AES.
1859 enum CryptoAESOp {
1860 CryptoAESFixed = 0x4E280800,
1861 CryptoAESFMask = 0xFF3E0C00
1862 };
1863
1864 // NEON instructions with two register operands.
1865 enum NEON2RegMiscOp {
1866 NEON2RegMiscFixed = 0x0E200800,
1867 NEON2RegMiscFMask = 0x9F3E0C00,
1868 NEON2RegMiscMask = 0xBF3FFC00,
1869 NEON2RegMiscUBit = 0x20000000,
1870 NEON_REV64 = NEON2RegMiscFixed | 0x00000000,
1871 NEON_REV32 = NEON2RegMiscFixed | 0x20000000,
1872 NEON_REV16 = NEON2RegMiscFixed | 0x00001000,
1873 NEON_SADDLP = NEON2RegMiscFixed | 0x00002000,
1874 NEON_UADDLP = NEON_SADDLP | NEON2RegMiscUBit,
1875 NEON_SUQADD = NEON2RegMiscFixed | 0x00003000,
1876 NEON_USQADD = NEON_SUQADD | NEON2RegMiscUBit,
1877 NEON_CLS = NEON2RegMiscFixed | 0x00004000,
1878 NEON_CLZ = NEON2RegMiscFixed | 0x20004000,
1879 NEON_CNT = NEON2RegMiscFixed | 0x00005000,
1880 NEON_RBIT_NOT = NEON2RegMiscFixed | 0x20005000,
1881 NEON_SADALP = NEON2RegMiscFixed | 0x00006000,
1882 NEON_UADALP = NEON_SADALP | NEON2RegMiscUBit,
1883 NEON_SQABS = NEON2RegMiscFixed | 0x00007000,
1884 NEON_SQNEG = NEON2RegMiscFixed | 0x20007000,
1885 NEON_CMGT_zero = NEON2RegMiscFixed | 0x00008000,
1886 NEON_CMGE_zero = NEON2RegMiscFixed | 0x20008000,
1887 NEON_CMEQ_zero = NEON2RegMiscFixed | 0x00009000,
1888 NEON_CMLE_zero = NEON2RegMiscFixed | 0x20009000,
1889 NEON_CMLT_zero = NEON2RegMiscFixed | 0x0000A000,
1890 NEON_ABS = NEON2RegMiscFixed | 0x0000B000,
1891 NEON_NEG = NEON2RegMiscFixed | 0x2000B000,
1892 NEON_XTN = NEON2RegMiscFixed | 0x00012000,
1893 NEON_SQXTUN = NEON2RegMiscFixed | 0x20012000,
1894 NEON_SHLL = NEON2RegMiscFixed | 0x20013000,
1895 NEON_SQXTN = NEON2RegMiscFixed | 0x00014000,
1896 NEON_UQXTN = NEON_SQXTN | NEON2RegMiscUBit,
1897
1898 NEON2RegMiscOpcode = 0x0001F000,
1899 NEON_RBIT_NOT_opcode = NEON_RBIT_NOT & NEON2RegMiscOpcode,
1900 NEON_NEG_opcode = NEON_NEG & NEON2RegMiscOpcode,
1901 NEON_XTN_opcode = NEON_XTN & NEON2RegMiscOpcode,
1902 NEON_UQXTN_opcode = NEON_UQXTN & NEON2RegMiscOpcode,
1903
1904 // These instructions use only one bit of the size field. The other bit is
1905 // used to distinguish between instructions.
1906 NEON2RegMiscFPMask = NEON2RegMiscMask | 0x00800000,
1907 NEON_FABS = NEON2RegMiscFixed | 0x0080F000,
1908 NEON_FNEG = NEON2RegMiscFixed | 0x2080F000,
1909 NEON_FCVTN = NEON2RegMiscFixed | 0x00016000,
1910 NEON_FCVTXN = NEON2RegMiscFixed | 0x20016000,
1911 NEON_FCVTL = NEON2RegMiscFixed | 0x00017000,
1912 NEON_FRINT32X = NEON2RegMiscFixed | 0x2001E000,
1913 NEON_FRINT32Z = NEON2RegMiscFixed | 0x0001E000,
1914 NEON_FRINT64X = NEON2RegMiscFixed | 0x2001F000,
1915 NEON_FRINT64Z = NEON2RegMiscFixed | 0x0001F000,
1916 NEON_FRINTN = NEON2RegMiscFixed | 0x00018000,
1917 NEON_FRINTA = NEON2RegMiscFixed | 0x20018000,
1918 NEON_FRINTP = NEON2RegMiscFixed | 0x00818000,
1919 NEON_FRINTM = NEON2RegMiscFixed | 0x00019000,
1920 NEON_FRINTX = NEON2RegMiscFixed | 0x20019000,
1921 NEON_FRINTZ = NEON2RegMiscFixed | 0x00819000,
1922 NEON_FRINTI = NEON2RegMiscFixed | 0x20819000,
1923 NEON_FCVTNS = NEON2RegMiscFixed | 0x0001A000,
1924 NEON_FCVTNU = NEON_FCVTNS | NEON2RegMiscUBit,
1925 NEON_FCVTPS = NEON2RegMiscFixed | 0x0081A000,
1926 NEON_FCVTPU = NEON_FCVTPS | NEON2RegMiscUBit,
1927 NEON_FCVTMS = NEON2RegMiscFixed | 0x0001B000,
1928 NEON_FCVTMU = NEON_FCVTMS | NEON2RegMiscUBit,
1929 NEON_FCVTZS = NEON2RegMiscFixed | 0x0081B000,
1930 NEON_FCVTZU = NEON_FCVTZS | NEON2RegMiscUBit,
1931 NEON_FCVTAS = NEON2RegMiscFixed | 0x0001C000,
1932 NEON_FCVTAU = NEON_FCVTAS | NEON2RegMiscUBit,
1933 NEON_FSQRT = NEON2RegMiscFixed | 0x2081F000,
1934 NEON_SCVTF = NEON2RegMiscFixed | 0x0001D000,
1935 NEON_UCVTF = NEON_SCVTF | NEON2RegMiscUBit,
1936 NEON_URSQRTE = NEON2RegMiscFixed | 0x2081C000,
1937 NEON_URECPE = NEON2RegMiscFixed | 0x0081C000,
1938 NEON_FRSQRTE = NEON2RegMiscFixed | 0x2081D000,
1939 NEON_FRECPE = NEON2RegMiscFixed | 0x0081D000,
1940 NEON_FCMGT_zero = NEON2RegMiscFixed | 0x0080C000,
1941 NEON_FCMGE_zero = NEON2RegMiscFixed | 0x2080C000,
1942 NEON_FCMEQ_zero = NEON2RegMiscFixed | 0x0080D000,
1943 NEON_FCMLE_zero = NEON2RegMiscFixed | 0x2080D000,
1944 NEON_FCMLT_zero = NEON2RegMiscFixed | 0x0080E000,
1945
1946 NEON_FCVTL_opcode = NEON_FCVTL & NEON2RegMiscOpcode,
1947 NEON_FCVTN_opcode = NEON_FCVTN & NEON2RegMiscOpcode
1948 };
1949
1950 // NEON instructions with two register operands (FP16).
1951 enum NEON2RegMiscFP16Op {
1952 NEON2RegMiscFP16Fixed = 0x0E780800,
1953 NEON2RegMiscFP16FMask = 0x9F7E0C00,
1954 NEON2RegMiscFP16Mask = 0xBFFFFC00,
1955 NEON_FRINTN_H = NEON2RegMiscFP16Fixed | 0x00018000,
1956 NEON_FRINTM_H = NEON2RegMiscFP16Fixed | 0x00019000,
1957 NEON_FCVTNS_H = NEON2RegMiscFP16Fixed | 0x0001A000,
1958 NEON_FCVTMS_H = NEON2RegMiscFP16Fixed | 0x0001B000,
1959 NEON_FCVTAS_H = NEON2RegMiscFP16Fixed | 0x0001C000,
1960 NEON_SCVTF_H = NEON2RegMiscFP16Fixed | 0x0001D000,
1961 NEON_FCMGT_H_zero = NEON2RegMiscFP16Fixed | 0x0080C000,
1962 NEON_FCMEQ_H_zero = NEON2RegMiscFP16Fixed | 0x0080D000,
1963 NEON_FCMLT_H_zero = NEON2RegMiscFP16Fixed | 0x0080E000,
1964 NEON_FABS_H = NEON2RegMiscFP16Fixed | 0x0080F000,
1965 NEON_FRINTP_H = NEON2RegMiscFP16Fixed | 0x00818000,
1966 NEON_FRINTZ_H = NEON2RegMiscFP16Fixed | 0x00819000,
1967 NEON_FCVTPS_H = NEON2RegMiscFP16Fixed | 0x0081A000,
1968 NEON_FCVTZS_H = NEON2RegMiscFP16Fixed | 0x0081B000,
1969 NEON_FRECPE_H = NEON2RegMiscFP16Fixed | 0x0081D000,
1970 NEON_FRINTA_H = NEON2RegMiscFP16Fixed | 0x20018000,
1971 NEON_FRINTX_H = NEON2RegMiscFP16Fixed | 0x20019000,
1972 NEON_FCVTNU_H = NEON2RegMiscFP16Fixed | 0x2001A000,
1973 NEON_FCVTMU_H = NEON2RegMiscFP16Fixed | 0x2001B000,
1974 NEON_FCVTAU_H = NEON2RegMiscFP16Fixed | 0x2001C000,
1975 NEON_UCVTF_H = NEON2RegMiscFP16Fixed | 0x2001D000,
1976 NEON_FCMGE_H_zero = NEON2RegMiscFP16Fixed | 0x2080C000,
1977 NEON_FCMLE_H_zero = NEON2RegMiscFP16Fixed | 0x2080D000,
1978 NEON_FNEG_H = NEON2RegMiscFP16Fixed | 0x2080F000,
1979 NEON_FRINTI_H = NEON2RegMiscFP16Fixed | 0x20819000,
1980 NEON_FCVTPU_H = NEON2RegMiscFP16Fixed | 0x2081A000,
1981 NEON_FCVTZU_H = NEON2RegMiscFP16Fixed | 0x2081B000,
1982 NEON_FRSQRTE_H = NEON2RegMiscFP16Fixed | 0x2081D000,
1983 NEON_FSQRT_H = NEON2RegMiscFP16Fixed | 0x2081F000
1984 };
1985
1986 // NEON instructions with three same-type operands.
1987 enum NEON3SameOp {
1988 NEON3SameFixed = 0x0E200400,
1989 NEON3SameFMask = 0x9F200400,
1990 NEON3SameMask = 0xBF20FC00,
1991 NEON3SameUBit = 0x20000000,
1992 NEON_ADD = NEON3SameFixed | 0x00008000,
1993 NEON_ADDP = NEON3SameFixed | 0x0000B800,
1994 NEON_SHADD = NEON3SameFixed | 0x00000000,
1995 NEON_SHSUB = NEON3SameFixed | 0x00002000,
1996 NEON_SRHADD = NEON3SameFixed | 0x00001000,
1997 NEON_CMEQ = NEON3SameFixed | NEON3SameUBit | 0x00008800,
1998 NEON_CMGE = NEON3SameFixed | 0x00003800,
1999 NEON_CMGT = NEON3SameFixed | 0x00003000,
2000 NEON_CMHI = NEON3SameFixed | NEON3SameUBit | NEON_CMGT,
2001 NEON_CMHS = NEON3SameFixed | NEON3SameUBit | NEON_CMGE,
2002 NEON_CMTST = NEON3SameFixed | 0x00008800,
2003 NEON_MLA = NEON3SameFixed | 0x00009000,
2004 NEON_MLS = NEON3SameFixed | 0x20009000,
2005 NEON_MUL = NEON3SameFixed | 0x00009800,
2006 NEON_PMUL = NEON3SameFixed | 0x20009800,
2007 NEON_SRSHL = NEON3SameFixed | 0x00005000,
2008 NEON_SQSHL = NEON3SameFixed | 0x00004800,
2009 NEON_SQRSHL = NEON3SameFixed | 0x00005800,
2010 NEON_SSHL = NEON3SameFixed | 0x00004000,
2011 NEON_SMAX = NEON3SameFixed | 0x00006000,
2012 NEON_SMAXP = NEON3SameFixed | 0x0000A000,
2013 NEON_SMIN = NEON3SameFixed | 0x00006800,
2014 NEON_SMINP = NEON3SameFixed | 0x0000A800,
2015 NEON_SABD = NEON3SameFixed | 0x00007000,
2016 NEON_SABA = NEON3SameFixed | 0x00007800,
2017 NEON_UABD = NEON3SameFixed | NEON3SameUBit | NEON_SABD,
2018 NEON_UABA = NEON3SameFixed | NEON3SameUBit | NEON_SABA,
2019 NEON_SQADD = NEON3SameFixed | 0x00000800,
2020 NEON_SQSUB = NEON3SameFixed | 0x00002800,
2021 NEON_SUB = NEON3SameFixed | NEON3SameUBit | 0x00008000,
2022 NEON_UHADD = NEON3SameFixed | NEON3SameUBit | NEON_SHADD,
2023 NEON_UHSUB = NEON3SameFixed | NEON3SameUBit | NEON_SHSUB,
2024 NEON_URHADD = NEON3SameFixed | NEON3SameUBit | NEON_SRHADD,
2025 NEON_UMAX = NEON3SameFixed | NEON3SameUBit | NEON_SMAX,
2026 NEON_UMAXP = NEON3SameFixed | NEON3SameUBit | NEON_SMAXP,
2027 NEON_UMIN = NEON3SameFixed | NEON3SameUBit | NEON_SMIN,
2028 NEON_UMINP = NEON3SameFixed | NEON3SameUBit | NEON_SMINP,
2029 NEON_URSHL = NEON3SameFixed | NEON3SameUBit | NEON_SRSHL,
2030 NEON_UQADD = NEON3SameFixed | NEON3SameUBit | NEON_SQADD,
2031 NEON_UQRSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQRSHL,
2032 NEON_UQSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQSHL,
2033 NEON_UQSUB = NEON3SameFixed | NEON3SameUBit | NEON_SQSUB,
2034 NEON_USHL = NEON3SameFixed | NEON3SameUBit | NEON_SSHL,
2035 NEON_SQDMULH = NEON3SameFixed | 0x0000B000,
2036 NEON_SQRDMULH = NEON3SameFixed | 0x2000B000,
2037
2038 // NEON floating point instructions with three same-type operands.
2039 NEON3SameFPFixed = NEON3SameFixed | 0x0000C000,
2040 NEON3SameFPFMask = NEON3SameFMask | 0x0000C000,
2041 NEON3SameFPMask = NEON3SameMask | 0x00800000,
2042 NEON_FADD = NEON3SameFixed | 0x0000D000,
2043 NEON_FSUB = NEON3SameFixed | 0x0080D000,
2044 NEON_FMUL = NEON3SameFixed | 0x2000D800,
2045 NEON_FDIV = NEON3SameFixed | 0x2000F800,
2046 NEON_FMAX = NEON3SameFixed | 0x0000F000,
2047 NEON_FMAXNM = NEON3SameFixed | 0x0000C000,
2048 NEON_FMAXP = NEON3SameFixed | 0x2000F000,
2049 NEON_FMAXNMP = NEON3SameFixed | 0x2000C000,
2050 NEON_FMIN = NEON3SameFixed | 0x0080F000,
2051 NEON_FMINNM = NEON3SameFixed | 0x0080C000,
2052 NEON_FMINP = NEON3SameFixed | 0x2080F000,
2053 NEON_FMINNMP = NEON3SameFixed | 0x2080C000,
2054 NEON_FMLA = NEON3SameFixed | 0x0000C800,
2055 NEON_FMLS = NEON3SameFixed | 0x0080C800,
2056 NEON_FMULX = NEON3SameFixed | 0x0000D800,
2057 NEON_FRECPS = NEON3SameFixed | 0x0000F800,
2058 NEON_FRSQRTS = NEON3SameFixed | 0x0080F800,
2059 NEON_FABD = NEON3SameFixed | 0x2080D000,
2060 NEON_FADDP = NEON3SameFixed | 0x2000D000,
2061 NEON_FCMEQ = NEON3SameFixed | 0x0000E000,
2062 NEON_FCMGE = NEON3SameFixed | 0x2000E000,
2063 NEON_FCMGT = NEON3SameFixed | 0x2080E000,
2064 NEON_FACGE = NEON3SameFixed | 0x2000E800,
2065 NEON_FACGT = NEON3SameFixed | 0x2080E800,
2066
2067 // NEON logical instructions with three same-type operands.
2068 NEON3SameLogicalFixed = NEON3SameFixed | 0x00001800,
2069 NEON3SameLogicalFMask = NEON3SameFMask | 0x0000F800,
2070 NEON3SameLogicalMask = 0xBFE0FC00,
2071 NEON3SameLogicalFormatMask = NEON_Q,
2072 NEON_AND = NEON3SameLogicalFixed | 0x00000000,
2073 NEON_ORR = NEON3SameLogicalFixed | 0x00A00000,
2074 NEON_ORN = NEON3SameLogicalFixed | 0x00C00000,
2075 NEON_EOR = NEON3SameLogicalFixed | 0x20000000,
2076 NEON_BIC = NEON3SameLogicalFixed | 0x00400000,
2077 NEON_BIF = NEON3SameLogicalFixed | 0x20C00000,
2078 NEON_BIT = NEON3SameLogicalFixed | 0x20800000,
2079 NEON_BSL = NEON3SameLogicalFixed | 0x20400000,
2080
2081 // FHM (FMLAL-like) instructions have an oddball encoding scheme under 3Same.
2082 NEON3SameFHMMask = 0xBFE0FC00, // U size opcode
2083 NEON_FMLAL = NEON3SameFixed | 0x0000E800, // 0 00 11101
2084 NEON_FMLAL2 = NEON3SameFixed | 0x2000C800, // 1 00 11001
2085 NEON_FMLSL = NEON3SameFixed | 0x0080E800, // 0 10 11101
2086 NEON_FMLSL2 = NEON3SameFixed | 0x2080C800 // 1 10 11001
2087 };
2088
2089
2090 enum NEON3SameFP16 {
2091 NEON3SameFP16Fixed = 0x0E400400,
2092 NEON3SameFP16FMask = 0x9F60C400,
2093 NEON3SameFP16Mask = 0xBFE0FC00,
2094 NEON_FMAXNM_H = NEON3SameFP16Fixed | 0x00000000,
2095 NEON_FMLA_H = NEON3SameFP16Fixed | 0x00000800,
2096 NEON_FADD_H = NEON3SameFP16Fixed | 0x00001000,
2097 NEON_FMULX_H = NEON3SameFP16Fixed | 0x00001800,
2098 NEON_FCMEQ_H = NEON3SameFP16Fixed | 0x00002000,
2099 NEON_FMAX_H = NEON3SameFP16Fixed | 0x00003000,
2100 NEON_FRECPS_H = NEON3SameFP16Fixed | 0x00003800,
2101 NEON_FMINNM_H = NEON3SameFP16Fixed | 0x00800000,
2102 NEON_FMLS_H = NEON3SameFP16Fixed | 0x00800800,
2103 NEON_FSUB_H = NEON3SameFP16Fixed | 0x00801000,
2104 NEON_FMIN_H = NEON3SameFP16Fixed | 0x00803000,
2105 NEON_FRSQRTS_H = NEON3SameFP16Fixed | 0x00803800,
2106 NEON_FMAXNMP_H = NEON3SameFP16Fixed | 0x20000000,
2107 NEON_FADDP_H = NEON3SameFP16Fixed | 0x20001000,
2108 NEON_FMUL_H = NEON3SameFP16Fixed | 0x20001800,
2109 NEON_FCMGE_H = NEON3SameFP16Fixed | 0x20002000,
2110 NEON_FACGE_H = NEON3SameFP16Fixed | 0x20002800,
2111 NEON_FMAXP_H = NEON3SameFP16Fixed | 0x20003000,
2112 NEON_FDIV_H = NEON3SameFP16Fixed | 0x20003800,
2113 NEON_FMINNMP_H = NEON3SameFP16Fixed | 0x20800000,
2114 NEON_FABD_H = NEON3SameFP16Fixed | 0x20801000,
2115 NEON_FCMGT_H = NEON3SameFP16Fixed | 0x20802000,
2116 NEON_FACGT_H = NEON3SameFP16Fixed | 0x20802800,
2117 NEON_FMINP_H = NEON3SameFP16Fixed | 0x20803000
2118 };
2119
2120
2121 // 'Extra' NEON instructions with three same-type operands.
2122 enum NEON3SameExtraOp {
2123 NEON3SameExtraFixed = 0x0E008400,
2124 NEON3SameExtraUBit = 0x20000000,
2125 NEON3SameExtraFMask = 0x9E208400,
2126 NEON3SameExtraMask = 0xBE20FC00,
2127 NEON_SQRDMLAH = NEON3SameExtraFixed | NEON3SameExtraUBit,
2128 NEON_SQRDMLSH = NEON3SameExtraFixed | NEON3SameExtraUBit | 0x00000800,
2129 NEON_SDOT = NEON3SameExtraFixed | 0x00001000,
2130 NEON_UDOT = NEON3SameExtraFixed | NEON3SameExtraUBit | 0x00001000,
2131
2132 /* v8.3 Complex Numbers */
2133 NEON3SameExtraFCFixed = 0x2E00C400,
2134 NEON3SameExtraFCFMask = 0xBF20C400,
2135 // FCMLA fixes opcode<3:2>, and uses opcode<1:0> to encode <rotate>.
2136 NEON3SameExtraFCMLAMask = NEON3SameExtraFCFMask | 0x00006000,
2137 NEON_FCMLA = NEON3SameExtraFCFixed,
2138 // FCADD fixes opcode<3:2, 0>, and uses opcode<1> to encode <rotate>.
2139 NEON3SameExtraFCADDMask = NEON3SameExtraFCFMask | 0x00006800,
2140 NEON_FCADD = NEON3SameExtraFCFixed | 0x00002000
2141 // Other encodings under NEON3SameExtraFCFMask are UNALLOCATED.
2142 };
2143
2144 // NEON instructions with three different-type operands.
2145 enum NEON3DifferentOp {
2146 NEON3DifferentFixed = 0x0E200000,
2147 NEON3DifferentFMask = 0x9F200C00,
2148 NEON3DifferentMask = 0xFF20FC00,
2149 NEON_ADDHN = NEON3DifferentFixed | 0x00004000,
2150 NEON_ADDHN2 = NEON_ADDHN | NEON_Q,
2151 NEON_PMULL = NEON3DifferentFixed | 0x0000E000,
2152 NEON_PMULL2 = NEON_PMULL | NEON_Q,
2153 NEON_RADDHN = NEON3DifferentFixed | 0x20004000,
2154 NEON_RADDHN2 = NEON_RADDHN | NEON_Q,
2155 NEON_RSUBHN = NEON3DifferentFixed | 0x20006000,
2156 NEON_RSUBHN2 = NEON_RSUBHN | NEON_Q,
2157 NEON_SABAL = NEON3DifferentFixed | 0x00005000,
2158 NEON_SABAL2 = NEON_SABAL | NEON_Q,
2159 NEON_SABDL = NEON3DifferentFixed | 0x00007000,
2160 NEON_SABDL2 = NEON_SABDL | NEON_Q,
2161 NEON_SADDL = NEON3DifferentFixed | 0x00000000,
2162 NEON_SADDL2 = NEON_SADDL | NEON_Q,
2163 NEON_SADDW = NEON3DifferentFixed | 0x00001000,
2164 NEON_SADDW2 = NEON_SADDW | NEON_Q,
2165 NEON_SMLAL = NEON3DifferentFixed | 0x00008000,
2166 NEON_SMLAL2 = NEON_SMLAL | NEON_Q,
2167 NEON_SMLSL = NEON3DifferentFixed | 0x0000A000,
2168 NEON_SMLSL2 = NEON_SMLSL | NEON_Q,
2169 NEON_SMULL = NEON3DifferentFixed | 0x0000C000,
2170 NEON_SMULL2 = NEON_SMULL | NEON_Q,
2171 NEON_SSUBL = NEON3DifferentFixed | 0x00002000,
2172 NEON_SSUBL2 = NEON_SSUBL | NEON_Q,
2173 NEON_SSUBW = NEON3DifferentFixed | 0x00003000,
2174 NEON_SSUBW2 = NEON_SSUBW | NEON_Q,
2175 NEON_SQDMLAL = NEON3DifferentFixed | 0x00009000,
2176 NEON_SQDMLAL2 = NEON_SQDMLAL | NEON_Q,
2177 NEON_SQDMLSL = NEON3DifferentFixed | 0x0000B000,
2178 NEON_SQDMLSL2 = NEON_SQDMLSL | NEON_Q,
2179 NEON_SQDMULL = NEON3DifferentFixed | 0x0000D000,
2180 NEON_SQDMULL2 = NEON_SQDMULL | NEON_Q,
2181 NEON_SUBHN = NEON3DifferentFixed | 0x00006000,
2182 NEON_SUBHN2 = NEON_SUBHN | NEON_Q,
2183 NEON_UABAL = NEON_SABAL | NEON3SameUBit,
2184 NEON_UABAL2 = NEON_UABAL | NEON_Q,
2185 NEON_UABDL = NEON_SABDL | NEON3SameUBit,
2186 NEON_UABDL2 = NEON_UABDL | NEON_Q,
2187 NEON_UADDL = NEON_SADDL | NEON3SameUBit,
2188 NEON_UADDL2 = NEON_UADDL | NEON_Q,
2189 NEON_UADDW = NEON_SADDW | NEON3SameUBit,
2190 NEON_UADDW2 = NEON_UADDW | NEON_Q,
2191 NEON_UMLAL = NEON_SMLAL | NEON3SameUBit,
2192 NEON_UMLAL2 = NEON_UMLAL | NEON_Q,
2193 NEON_UMLSL = NEON_SMLSL | NEON3SameUBit,
2194 NEON_UMLSL2 = NEON_UMLSL | NEON_Q,
2195 NEON_UMULL = NEON_SMULL | NEON3SameUBit,
2196 NEON_UMULL2 = NEON_UMULL | NEON_Q,
2197 NEON_USUBL = NEON_SSUBL | NEON3SameUBit,
2198 NEON_USUBL2 = NEON_USUBL | NEON_Q,
2199 NEON_USUBW = NEON_SSUBW | NEON3SameUBit,
2200 NEON_USUBW2 = NEON_USUBW | NEON_Q
2201 };
2202
2203 // NEON instructions operating across vectors.
2204 enum NEONAcrossLanesOp {
2205 NEONAcrossLanesFixed = 0x0E300800,
2206 NEONAcrossLanesFMask = 0x9F3E0C00,
2207 NEONAcrossLanesMask = 0xBF3FFC00,
2208 NEON_ADDV = NEONAcrossLanesFixed | 0x0001B000,
2209 NEON_SADDLV = NEONAcrossLanesFixed | 0x00003000,
2210 NEON_UADDLV = NEONAcrossLanesFixed | 0x20003000,
2211 NEON_SMAXV = NEONAcrossLanesFixed | 0x0000A000,
2212 NEON_SMINV = NEONAcrossLanesFixed | 0x0001A000,
2213 NEON_UMAXV = NEONAcrossLanesFixed | 0x2000A000,
2214 NEON_UMINV = NEONAcrossLanesFixed | 0x2001A000,
2215
2216 NEONAcrossLanesFP16Fixed = NEONAcrossLanesFixed | 0x0000C000,
2217 NEONAcrossLanesFP16FMask = NEONAcrossLanesFMask | 0x2000C000,
2218 NEONAcrossLanesFP16Mask = NEONAcrossLanesMask | 0x20800000,
2219 NEON_FMAXNMV_H = NEONAcrossLanesFP16Fixed | 0x00000000,
2220 NEON_FMAXV_H = NEONAcrossLanesFP16Fixed | 0x00003000,
2221 NEON_FMINNMV_H = NEONAcrossLanesFP16Fixed | 0x00800000,
2222 NEON_FMINV_H = NEONAcrossLanesFP16Fixed | 0x00803000,
2223
2224 // NEON floating point across instructions.
2225 NEONAcrossLanesFPFixed = NEONAcrossLanesFixed | 0x2000C000,
2226 NEONAcrossLanesFPFMask = NEONAcrossLanesFMask | 0x2000C000,
2227 NEONAcrossLanesFPMask = NEONAcrossLanesMask | 0x20800000,
2228
2229 NEON_FMAXV = NEONAcrossLanesFPFixed | 0x2000F000,
2230 NEON_FMINV = NEONAcrossLanesFPFixed | 0x2080F000,
2231 NEON_FMAXNMV = NEONAcrossLanesFPFixed | 0x2000C000,
2232 NEON_FMINNMV = NEONAcrossLanesFPFixed | 0x2080C000
2233 };
2234
2235 // NEON instructions with indexed element operand.
2236 enum NEONByIndexedElementOp {
2237 NEONByIndexedElementFixed = 0x0F000000,
2238 NEONByIndexedElementFMask = 0x9F000400,
2239 NEONByIndexedElementMask = 0xBF00F400,
2240 NEON_MUL_byelement = NEONByIndexedElementFixed | 0x00008000,
2241 NEON_MLA_byelement = NEONByIndexedElementFixed | 0x20000000,
2242 NEON_MLS_byelement = NEONByIndexedElementFixed | 0x20004000,
2243 NEON_SMULL_byelement = NEONByIndexedElementFixed | 0x0000A000,
2244 NEON_SMLAL_byelement = NEONByIndexedElementFixed | 0x00002000,
2245 NEON_SMLSL_byelement = NEONByIndexedElementFixed | 0x00006000,
2246 NEON_UMULL_byelement = NEONByIndexedElementFixed | 0x2000A000,
2247 NEON_UMLAL_byelement = NEONByIndexedElementFixed | 0x20002000,
2248 NEON_UMLSL_byelement = NEONByIndexedElementFixed | 0x20006000,
2249 NEON_SQDMULL_byelement = NEONByIndexedElementFixed | 0x0000B000,
2250 NEON_SQDMLAL_byelement = NEONByIndexedElementFixed | 0x00003000,
2251 NEON_SQDMLSL_byelement = NEONByIndexedElementFixed | 0x00007000,
2252 NEON_SQDMULH_byelement = NEONByIndexedElementFixed | 0x0000C000,
2253 NEON_SQRDMULH_byelement = NEONByIndexedElementFixed | 0x0000D000,
2254 NEON_SDOT_byelement = NEONByIndexedElementFixed | 0x0000E000,
2255 NEON_SQRDMLAH_byelement = NEONByIndexedElementFixed | 0x2000D000,
2256 NEON_UDOT_byelement = NEONByIndexedElementFixed | 0x2000E000,
2257 NEON_SQRDMLSH_byelement = NEONByIndexedElementFixed | 0x2000F000,
2258
2259 NEON_FMLA_H_byelement = NEONByIndexedElementFixed | 0x00001000,
2260 NEON_FMLS_H_byelement = NEONByIndexedElementFixed | 0x00005000,
2261 NEON_FMUL_H_byelement = NEONByIndexedElementFixed | 0x00009000,
2262 NEON_FMULX_H_byelement = NEONByIndexedElementFixed | 0x20009000,
2263
2264 // Floating point instructions.
2265 NEONByIndexedElementFPFixed = NEONByIndexedElementFixed | 0x00800000,
2266 NEONByIndexedElementFPMask = NEONByIndexedElementMask | 0x00800000,
2267 NEON_FMLA_byelement = NEONByIndexedElementFPFixed | 0x00001000,
2268 NEON_FMLS_byelement = NEONByIndexedElementFPFixed | 0x00005000,
2269 NEON_FMUL_byelement = NEONByIndexedElementFPFixed | 0x00009000,
2270 NEON_FMULX_byelement = NEONByIndexedElementFPFixed | 0x20009000,
2271
2272 // FMLAL-like instructions.
2273 // For all cases: U = x, size = 10, opcode = xx00
2274 NEONByIndexedElementFPLongFixed = NEONByIndexedElementFixed | 0x00800000,
2275 NEONByIndexedElementFPLongFMask = NEONByIndexedElementFMask | 0x00C03000,
2276 NEONByIndexedElementFPLongMask = 0xBFC0F400,
2277 NEON_FMLAL_H_byelement = NEONByIndexedElementFixed | 0x00800000,
2278 NEON_FMLAL2_H_byelement = NEONByIndexedElementFixed | 0x20808000,
2279 NEON_FMLSL_H_byelement = NEONByIndexedElementFixed | 0x00804000,
2280 NEON_FMLSL2_H_byelement = NEONByIndexedElementFixed | 0x2080C000,
2281
2282 // Complex instruction(s).
2283 // This is necessary because the 'rot' encoding moves into the
2284 // NEONByIndex..Mask space.
2285 NEONByIndexedElementFPComplexMask = 0xBF009400,
2286 NEON_FCMLA_byelement = NEONByIndexedElementFixed | 0x20001000
2287 };
2288
2289 // NEON register copy.
2290 enum NEONCopyOp {
2291 NEONCopyFixed = 0x0E000400,
2292 NEONCopyFMask = 0x9FE08400,
2293 NEONCopyMask = 0x3FE08400,
2294 NEONCopyInsElementMask = NEONCopyMask | 0x40000000,
2295 NEONCopyInsGeneralMask = NEONCopyMask | 0x40007800,
2296 NEONCopyDupElementMask = NEONCopyMask | 0x20007800,
2297 NEONCopyDupGeneralMask = NEONCopyDupElementMask,
2298 NEONCopyUmovMask = NEONCopyMask | 0x20007800,
2299 NEONCopySmovMask = NEONCopyMask | 0x20007800,
2300 NEON_INS_ELEMENT = NEONCopyFixed | 0x60000000,
2301 NEON_INS_GENERAL = NEONCopyFixed | 0x40001800,
2302 NEON_DUP_ELEMENT = NEONCopyFixed | 0x00000000,
2303 NEON_DUP_GENERAL = NEONCopyFixed | 0x00000800,
2304 NEON_SMOV = NEONCopyFixed | 0x00002800,
2305 NEON_UMOV = NEONCopyFixed | 0x00003800
2306 };
2307
2308 // NEON extract.
2309 enum NEONExtractOp {
2310 NEONExtractFixed = 0x2E000000,
2311 NEONExtractFMask = 0xBF208400,
2312 NEONExtractMask = 0xBFE08400,
2313 NEON_EXT = NEONExtractFixed | 0x00000000
2314 };
2315
2316 enum NEONLoadStoreMultiOp {
2317 NEONLoadStoreMultiL = 0x00400000,
2318 NEONLoadStoreMulti1_1v = 0x00007000,
2319 NEONLoadStoreMulti1_2v = 0x0000A000,
2320 NEONLoadStoreMulti1_3v = 0x00006000,
2321 NEONLoadStoreMulti1_4v = 0x00002000,
2322 NEONLoadStoreMulti2 = 0x00008000,
2323 NEONLoadStoreMulti3 = 0x00004000,
2324 NEONLoadStoreMulti4 = 0x00000000
2325 };
2326
2327 // NEON load/store multiple structures.
2328 enum NEONLoadStoreMultiStructOp {
2329 NEONLoadStoreMultiStructFixed = 0x0C000000,
2330 NEONLoadStoreMultiStructFMask = 0xBFBF0000,
2331 NEONLoadStoreMultiStructMask = 0xBFFFF000,
2332 NEONLoadStoreMultiStructStore = NEONLoadStoreMultiStructFixed,
2333 NEONLoadStoreMultiStructLoad = NEONLoadStoreMultiStructFixed |
2334 NEONLoadStoreMultiL,
2335 NEON_LD1_1v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_1v,
2336 NEON_LD1_2v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_2v,
2337 NEON_LD1_3v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_3v,
2338 NEON_LD1_4v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_4v,
2339 NEON_LD2 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti2,
2340 NEON_LD3 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti3,
2341 NEON_LD4 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti4,
2342 NEON_ST1_1v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_1v,
2343 NEON_ST1_2v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_2v,
2344 NEON_ST1_3v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_3v,
2345 NEON_ST1_4v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_4v,
2346 NEON_ST2 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti2,
2347 NEON_ST3 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti3,
2348 NEON_ST4 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti4
2349 };
2350
2351 // NEON load/store multiple structures with post-index addressing.
2352 enum NEONLoadStoreMultiStructPostIndexOp {
2353 NEONLoadStoreMultiStructPostIndexFixed = 0x0C800000,
2354 NEONLoadStoreMultiStructPostIndexFMask = 0xBFA00000,
2355 NEONLoadStoreMultiStructPostIndexMask = 0xBFE0F000,
2356 NEONLoadStoreMultiStructPostIndex = 0x00800000,
2357 NEON_LD1_1v_post = NEON_LD1_1v | NEONLoadStoreMultiStructPostIndex,
2358 NEON_LD1_2v_post = NEON_LD1_2v | NEONLoadStoreMultiStructPostIndex,
2359 NEON_LD1_3v_post = NEON_LD1_3v | NEONLoadStoreMultiStructPostIndex,
2360 NEON_LD1_4v_post = NEON_LD1_4v | NEONLoadStoreMultiStructPostIndex,
2361 NEON_LD2_post = NEON_LD2 | NEONLoadStoreMultiStructPostIndex,
2362 NEON_LD3_post = NEON_LD3 | NEONLoadStoreMultiStructPostIndex,
2363 NEON_LD4_post = NEON_LD4 | NEONLoadStoreMultiStructPostIndex,
2364 NEON_ST1_1v_post = NEON_ST1_1v | NEONLoadStoreMultiStructPostIndex,
2365 NEON_ST1_2v_post = NEON_ST1_2v | NEONLoadStoreMultiStructPostIndex,
2366 NEON_ST1_3v_post = NEON_ST1_3v | NEONLoadStoreMultiStructPostIndex,
2367 NEON_ST1_4v_post = NEON_ST1_4v | NEONLoadStoreMultiStructPostIndex,
2368 NEON_ST2_post = NEON_ST2 | NEONLoadStoreMultiStructPostIndex,
2369 NEON_ST3_post = NEON_ST3 | NEONLoadStoreMultiStructPostIndex,
2370 NEON_ST4_post = NEON_ST4 | NEONLoadStoreMultiStructPostIndex
2371 };
2372
2373 enum NEONLoadStoreSingleOp {
2374 NEONLoadStoreSingle1 = 0x00000000,
2375 NEONLoadStoreSingle2 = 0x00200000,
2376 NEONLoadStoreSingle3 = 0x00002000,
2377 NEONLoadStoreSingle4 = 0x00202000,
2378 NEONLoadStoreSingleL = 0x00400000,
2379 NEONLoadStoreSingle_b = 0x00000000,
2380 NEONLoadStoreSingle_h = 0x00004000,
2381 NEONLoadStoreSingle_s = 0x00008000,
2382 NEONLoadStoreSingle_d = 0x00008400,
2383 NEONLoadStoreSingleAllLanes = 0x0000C000,
2384 NEONLoadStoreSingleLenMask = 0x00202000
2385 };
2386
2387 // NEON load/store single structure.
2388 enum NEONLoadStoreSingleStructOp {
2389 NEONLoadStoreSingleStructFixed = 0x0D000000,
2390 NEONLoadStoreSingleStructFMask = 0xBF9F0000,
2391 NEONLoadStoreSingleStructMask = 0xBFFFE000,
2392 NEONLoadStoreSingleStructStore = NEONLoadStoreSingleStructFixed,
2393 NEONLoadStoreSingleStructLoad = NEONLoadStoreSingleStructFixed |
2394 NEONLoadStoreSingleL,
2395 NEONLoadStoreSingleStructLoad1 = NEONLoadStoreSingle1 |
2396 NEONLoadStoreSingleStructLoad,
2397 NEONLoadStoreSingleStructLoad2 = NEONLoadStoreSingle2 |
2398 NEONLoadStoreSingleStructLoad,
2399 NEONLoadStoreSingleStructLoad3 = NEONLoadStoreSingle3 |
2400 NEONLoadStoreSingleStructLoad,
2401 NEONLoadStoreSingleStructLoad4 = NEONLoadStoreSingle4 |
2402 NEONLoadStoreSingleStructLoad,
2403 NEONLoadStoreSingleStructStore1 = NEONLoadStoreSingle1 |
2404 NEONLoadStoreSingleStructFixed,
2405 NEONLoadStoreSingleStructStore2 = NEONLoadStoreSingle2 |
2406 NEONLoadStoreSingleStructFixed,
2407 NEONLoadStoreSingleStructStore3 = NEONLoadStoreSingle3 |
2408 NEONLoadStoreSingleStructFixed,
2409 NEONLoadStoreSingleStructStore4 = NEONLoadStoreSingle4 |
2410 NEONLoadStoreSingleStructFixed,
2411 NEON_LD1_b = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_b,
2412 NEON_LD1_h = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_h,
2413 NEON_LD1_s = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_s,
2414 NEON_LD1_d = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_d,
2415 NEON_LD1R = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingleAllLanes,
2416 NEON_ST1_b = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_b,
2417 NEON_ST1_h = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_h,
2418 NEON_ST1_s = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_s,
2419 NEON_ST1_d = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_d,
2420
2421 NEON_LD2_b = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_b,
2422 NEON_LD2_h = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_h,
2423 NEON_LD2_s = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_s,
2424 NEON_LD2_d = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_d,
2425 NEON_LD2R = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingleAllLanes,
2426 NEON_ST2_b = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_b,
2427 NEON_ST2_h = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_h,
2428 NEON_ST2_s = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_s,
2429 NEON_ST2_d = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_d,
2430
2431 NEON_LD3_b = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_b,
2432 NEON_LD3_h = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_h,
2433 NEON_LD3_s = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_s,
2434 NEON_LD3_d = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_d,
2435 NEON_LD3R = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingleAllLanes,
2436 NEON_ST3_b = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_b,
2437 NEON_ST3_h = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_h,
2438 NEON_ST3_s = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_s,
2439 NEON_ST3_d = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_d,
2440
2441 NEON_LD4_b = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_b,
2442 NEON_LD4_h = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_h,
2443 NEON_LD4_s = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_s,
2444 NEON_LD4_d = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_d,
2445 NEON_LD4R = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingleAllLanes,
2446 NEON_ST4_b = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_b,
2447 NEON_ST4_h = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_h,
2448 NEON_ST4_s = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_s,
2449 NEON_ST4_d = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_d
2450 };
2451
2452 // NEON load/store single structure with post-index addressing.
2453 enum NEONLoadStoreSingleStructPostIndexOp {
2454 NEONLoadStoreSingleStructPostIndexFixed = 0x0D800000,
2455 NEONLoadStoreSingleStructPostIndexFMask = 0xBF800000,
2456 NEONLoadStoreSingleStructPostIndexMask = 0xBFE0E000,
2457 NEONLoadStoreSingleStructPostIndex = 0x00800000,
2458 NEON_LD1_b_post = NEON_LD1_b | NEONLoadStoreSingleStructPostIndex,
2459 NEON_LD1_h_post = NEON_LD1_h | NEONLoadStoreSingleStructPostIndex,
2460 NEON_LD1_s_post = NEON_LD1_s | NEONLoadStoreSingleStructPostIndex,
2461 NEON_LD1_d_post = NEON_LD1_d | NEONLoadStoreSingleStructPostIndex,
2462 NEON_LD1R_post = NEON_LD1R | NEONLoadStoreSingleStructPostIndex,
2463 NEON_ST1_b_post = NEON_ST1_b | NEONLoadStoreSingleStructPostIndex,
2464 NEON_ST1_h_post = NEON_ST1_h | NEONLoadStoreSingleStructPostIndex,
2465 NEON_ST1_s_post = NEON_ST1_s | NEONLoadStoreSingleStructPostIndex,
2466 NEON_ST1_d_post = NEON_ST1_d | NEONLoadStoreSingleStructPostIndex,
2467
2468 NEON_LD2_b_post = NEON_LD2_b | NEONLoadStoreSingleStructPostIndex,
2469 NEON_LD2_h_post = NEON_LD2_h | NEONLoadStoreSingleStructPostIndex,
2470 NEON_LD2_s_post = NEON_LD2_s | NEONLoadStoreSingleStructPostIndex,
2471 NEON_LD2_d_post = NEON_LD2_d | NEONLoadStoreSingleStructPostIndex,
2472 NEON_LD2R_post = NEON_LD2R | NEONLoadStoreSingleStructPostIndex,
2473 NEON_ST2_b_post = NEON_ST2_b | NEONLoadStoreSingleStructPostIndex,
2474 NEON_ST2_h_post = NEON_ST2_h | NEONLoadStoreSingleStructPostIndex,
2475 NEON_ST2_s_post = NEON_ST2_s | NEONLoadStoreSingleStructPostIndex,
2476 NEON_ST2_d_post = NEON_ST2_d | NEONLoadStoreSingleStructPostIndex,
2477
2478 NEON_LD3_b_post = NEON_LD3_b | NEONLoadStoreSingleStructPostIndex,
2479 NEON_LD3_h_post = NEON_LD3_h | NEONLoadStoreSingleStructPostIndex,
2480 NEON_LD3_s_post = NEON_LD3_s | NEONLoadStoreSingleStructPostIndex,
2481 NEON_LD3_d_post = NEON_LD3_d | NEONLoadStoreSingleStructPostIndex,
2482 NEON_LD3R_post = NEON_LD3R | NEONLoadStoreSingleStructPostIndex,
2483 NEON_ST3_b_post = NEON_ST3_b | NEONLoadStoreSingleStructPostIndex,
2484 NEON_ST3_h_post = NEON_ST3_h | NEONLoadStoreSingleStructPostIndex,
2485 NEON_ST3_s_post = NEON_ST3_s | NEONLoadStoreSingleStructPostIndex,
2486 NEON_ST3_d_post = NEON_ST3_d | NEONLoadStoreSingleStructPostIndex,
2487
2488 NEON_LD4_b_post = NEON_LD4_b | NEONLoadStoreSingleStructPostIndex,
2489 NEON_LD4_h_post = NEON_LD4_h | NEONLoadStoreSingleStructPostIndex,
2490 NEON_LD4_s_post = NEON_LD4_s | NEONLoadStoreSingleStructPostIndex,
2491 NEON_LD4_d_post = NEON_LD4_d | NEONLoadStoreSingleStructPostIndex,
2492 NEON_LD4R_post = NEON_LD4R | NEONLoadStoreSingleStructPostIndex,
2493 NEON_ST4_b_post = NEON_ST4_b | NEONLoadStoreSingleStructPostIndex,
2494 NEON_ST4_h_post = NEON_ST4_h | NEONLoadStoreSingleStructPostIndex,
2495 NEON_ST4_s_post = NEON_ST4_s | NEONLoadStoreSingleStructPostIndex,
2496 NEON_ST4_d_post = NEON_ST4_d | NEONLoadStoreSingleStructPostIndex
2497 };
2498
2499 // NEON modified immediate.
2500 enum NEONModifiedImmediateOp {
2501 NEONModifiedImmediateFixed = 0x0F000400,
2502 NEONModifiedImmediateFMask = 0x9FF80400,
2503 NEONModifiedImmediateOpBit = 0x20000000,
2504 NEONModifiedImmediate_FMOV = NEONModifiedImmediateFixed | 0x00000800,
2505 NEONModifiedImmediate_MOVI = NEONModifiedImmediateFixed | 0x00000000,
2506 NEONModifiedImmediate_MVNI = NEONModifiedImmediateFixed | 0x20000000,
2507 NEONModifiedImmediate_ORR = NEONModifiedImmediateFixed | 0x00001000,
2508 NEONModifiedImmediate_BIC = NEONModifiedImmediateFixed | 0x20001000
2509 };
2510
2511 // NEON shift immediate.
2512 enum NEONShiftImmediateOp {
2513 NEONShiftImmediateFixed = 0x0F000400,
2514 NEONShiftImmediateFMask = 0x9F800400,
2515 NEONShiftImmediateMask = 0xBF80FC00,
2516 NEONShiftImmediateUBit = 0x20000000,
2517 NEON_SHL = NEONShiftImmediateFixed | 0x00005000,
2518 NEON_SSHLL = NEONShiftImmediateFixed | 0x0000A000,
2519 NEON_USHLL = NEONShiftImmediateFixed | 0x2000A000,
2520 NEON_SLI = NEONShiftImmediateFixed | 0x20005000,
2521 NEON_SRI = NEONShiftImmediateFixed | 0x20004000,
2522 NEON_SHRN = NEONShiftImmediateFixed | 0x00008000,
2523 NEON_RSHRN = NEONShiftImmediateFixed | 0x00008800,
2524 NEON_UQSHRN = NEONShiftImmediateFixed | 0x20009000,
2525 NEON_UQRSHRN = NEONShiftImmediateFixed | 0x20009800,
2526 NEON_SQSHRN = NEONShiftImmediateFixed | 0x00009000,
2527 NEON_SQRSHRN = NEONShiftImmediateFixed | 0x00009800,
2528 NEON_SQSHRUN = NEONShiftImmediateFixed | 0x20008000,
2529 NEON_SQRSHRUN = NEONShiftImmediateFixed | 0x20008800,
2530 NEON_SSHR = NEONShiftImmediateFixed | 0x00000000,
2531 NEON_SRSHR = NEONShiftImmediateFixed | 0x00002000,
2532 NEON_USHR = NEONShiftImmediateFixed | 0x20000000,
2533 NEON_URSHR = NEONShiftImmediateFixed | 0x20002000,
2534 NEON_SSRA = NEONShiftImmediateFixed | 0x00001000,
2535 NEON_SRSRA = NEONShiftImmediateFixed | 0x00003000,
2536 NEON_USRA = NEONShiftImmediateFixed | 0x20001000,
2537 NEON_URSRA = NEONShiftImmediateFixed | 0x20003000,
2538 NEON_SQSHLU = NEONShiftImmediateFixed | 0x20006000,
2539 NEON_SCVTF_imm = NEONShiftImmediateFixed | 0x0000E000,
2540 NEON_UCVTF_imm = NEONShiftImmediateFixed | 0x2000E000,
2541 NEON_FCVTZS_imm = NEONShiftImmediateFixed | 0x0000F800,
2542 NEON_FCVTZU_imm = NEONShiftImmediateFixed | 0x2000F800,
2543 NEON_SQSHL_imm = NEONShiftImmediateFixed | 0x00007000,
2544 NEON_UQSHL_imm = NEONShiftImmediateFixed | 0x20007000
2545 };
2546
2547 // NEON table.
2548 enum NEONTableOp {
2549 NEONTableFixed = 0x0E000000,
2550 NEONTableFMask = 0xBF208C00,
2551 NEONTableExt = 0x00001000,
2552 NEONTableMask = 0xBF20FC00,
2553 NEON_TBL_1v = NEONTableFixed | 0x00000000,
2554 NEON_TBL_2v = NEONTableFixed | 0x00002000,
2555 NEON_TBL_3v = NEONTableFixed | 0x00004000,
2556 NEON_TBL_4v = NEONTableFixed | 0x00006000,
2557 NEON_TBX_1v = NEON_TBL_1v | NEONTableExt,
2558 NEON_TBX_2v = NEON_TBL_2v | NEONTableExt,
2559 NEON_TBX_3v = NEON_TBL_3v | NEONTableExt,
2560 NEON_TBX_4v = NEON_TBL_4v | NEONTableExt
2561 };
2562
2563 // NEON perm.
2564 enum NEONPermOp {
2565 NEONPermFixed = 0x0E000800,
2566 NEONPermFMask = 0xBF208C00,
2567 NEONPermMask = 0x3F20FC00,
2568 NEON_UZP1 = NEONPermFixed | 0x00001000,
2569 NEON_TRN1 = NEONPermFixed | 0x00002000,
2570 NEON_ZIP1 = NEONPermFixed | 0x00003000,
2571 NEON_UZP2 = NEONPermFixed | 0x00005000,
2572 NEON_TRN2 = NEONPermFixed | 0x00006000,
2573 NEON_ZIP2 = NEONPermFixed | 0x00007000
2574 };
2575
2576 // NEON scalar instructions with two register operands.
2577 enum NEONScalar2RegMiscOp {
2578 NEONScalar2RegMiscFixed = 0x5E200800,
2579 NEONScalar2RegMiscFMask = 0xDF3E0C00,
2580 NEONScalar2RegMiscMask = NEON_Q | NEONScalar | NEON2RegMiscMask,
2581 NEON_CMGT_zero_scalar = NEON_Q | NEONScalar | NEON_CMGT_zero,
2582 NEON_CMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_CMEQ_zero,
2583 NEON_CMLT_zero_scalar = NEON_Q | NEONScalar | NEON_CMLT_zero,
2584 NEON_CMGE_zero_scalar = NEON_Q | NEONScalar | NEON_CMGE_zero,
2585 NEON_CMLE_zero_scalar = NEON_Q | NEONScalar | NEON_CMLE_zero,
2586 NEON_ABS_scalar = NEON_Q | NEONScalar | NEON_ABS,
2587 NEON_SQABS_scalar = NEON_Q | NEONScalar | NEON_SQABS,
2588 NEON_NEG_scalar = NEON_Q | NEONScalar | NEON_NEG,
2589 NEON_SQNEG_scalar = NEON_Q | NEONScalar | NEON_SQNEG,
2590 NEON_SQXTN_scalar = NEON_Q | NEONScalar | NEON_SQXTN,
2591 NEON_UQXTN_scalar = NEON_Q | NEONScalar | NEON_UQXTN,
2592 NEON_SQXTUN_scalar = NEON_Q | NEONScalar | NEON_SQXTUN,
2593 NEON_SUQADD_scalar = NEON_Q | NEONScalar | NEON_SUQADD,
2594 NEON_USQADD_scalar = NEON_Q | NEONScalar | NEON_USQADD,
2595
2596 NEONScalar2RegMiscOpcode = NEON2RegMiscOpcode,
2597 NEON_NEG_scalar_opcode = NEON_NEG_scalar & NEONScalar2RegMiscOpcode,
2598
2599 NEONScalar2RegMiscFPMask = NEONScalar2RegMiscMask | 0x00800000,
2600 NEON_FRSQRTE_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE,
2601 NEON_FRECPE_scalar = NEON_Q | NEONScalar | NEON_FRECPE,
2602 NEON_SCVTF_scalar = NEON_Q | NEONScalar | NEON_SCVTF,
2603 NEON_UCVTF_scalar = NEON_Q | NEONScalar | NEON_UCVTF,
2604 NEON_FCMGT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_zero,
2605 NEON_FCMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_zero,
2606 NEON_FCMLT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_zero,
2607 NEON_FCMGE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_zero,
2608 NEON_FCMLE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_zero,
2609 NEON_FRECPX_scalar = NEONScalar2RegMiscFixed | 0x0081F000,
2610 NEON_FCVTNS_scalar = NEON_Q | NEONScalar | NEON_FCVTNS,
2611 NEON_FCVTNU_scalar = NEON_Q | NEONScalar | NEON_FCVTNU,
2612 NEON_FCVTPS_scalar = NEON_Q | NEONScalar | NEON_FCVTPS,
2613 NEON_FCVTPU_scalar = NEON_Q | NEONScalar | NEON_FCVTPU,
2614 NEON_FCVTMS_scalar = NEON_Q | NEONScalar | NEON_FCVTMS,
2615 NEON_FCVTMU_scalar = NEON_Q | NEONScalar | NEON_FCVTMU,
2616 NEON_FCVTZS_scalar = NEON_Q | NEONScalar | NEON_FCVTZS,
2617 NEON_FCVTZU_scalar = NEON_Q | NEONScalar | NEON_FCVTZU,
2618 NEON_FCVTAS_scalar = NEON_Q | NEONScalar | NEON_FCVTAS,
2619 NEON_FCVTAU_scalar = NEON_Q | NEONScalar | NEON_FCVTAU,
2620 NEON_FCVTXN_scalar = NEON_Q | NEONScalar | NEON_FCVTXN
2621 };
2622
2623 // NEON instructions with two register operands (FP16).
2624 enum NEONScalar2RegMiscFP16Op {
2625 NEONScalar2RegMiscFP16Fixed = 0x5E780800,
2626 NEONScalar2RegMiscFP16FMask = 0xDF7E0C00,
2627 NEONScalar2RegMiscFP16Mask = 0xFFFFFC00,
2628 NEON_FCVTNS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTNS_H,
2629 NEON_FCVTMS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTMS_H,
2630 NEON_FCVTAS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTAS_H,
2631 NEON_SCVTF_H_scalar = NEON_Q | NEONScalar | NEON_SCVTF_H,
2632 NEON_FCMGT_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_H_zero,
2633 NEON_FCMEQ_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_H_zero,
2634 NEON_FCMLT_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_H_zero,
2635 NEON_FCVTPS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTPS_H,
2636 NEON_FCVTZS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_H,
2637 NEON_FRECPE_H_scalar = NEON_Q | NEONScalar | NEON_FRECPE_H,
2638 NEON_FRECPX_H_scalar = NEONScalar2RegMiscFP16Fixed | 0x0081F000,
2639 NEON_FCVTNU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTNU_H,
2640 NEON_FCVTMU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTMU_H,
2641 NEON_FCVTAU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTAU_H,
2642 NEON_UCVTF_H_scalar = NEON_Q | NEONScalar | NEON_UCVTF_H,
2643 NEON_FCMGE_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_H_zero,
2644 NEON_FCMLE_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_H_zero,
2645 NEON_FCVTPU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTPU_H,
2646 NEON_FCVTZU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_H,
2647 NEON_FRSQRTE_H_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE_H
2648 };
2649
2650 // NEON scalar instructions with three same-type operands.
2651 enum NEONScalar3SameOp {
2652 NEONScalar3SameFixed = 0x5E200400,
2653 NEONScalar3SameFMask = 0xDF200400,
2654 NEONScalar3SameMask = 0xFF20FC00,
2655 NEON_ADD_scalar = NEON_Q | NEONScalar | NEON_ADD,
2656 NEON_CMEQ_scalar = NEON_Q | NEONScalar | NEON_CMEQ,
2657 NEON_CMGE_scalar = NEON_Q | NEONScalar | NEON_CMGE,
2658 NEON_CMGT_scalar = NEON_Q | NEONScalar | NEON_CMGT,
2659 NEON_CMHI_scalar = NEON_Q | NEONScalar | NEON_CMHI,
2660 NEON_CMHS_scalar = NEON_Q | NEONScalar | NEON_CMHS,
2661 NEON_CMTST_scalar = NEON_Q | NEONScalar | NEON_CMTST,
2662 NEON_SUB_scalar = NEON_Q | NEONScalar | NEON_SUB,
2663 NEON_UQADD_scalar = NEON_Q | NEONScalar | NEON_UQADD,
2664 NEON_SQADD_scalar = NEON_Q | NEONScalar | NEON_SQADD,
2665 NEON_UQSUB_scalar = NEON_Q | NEONScalar | NEON_UQSUB,
2666 NEON_SQSUB_scalar = NEON_Q | NEONScalar | NEON_SQSUB,
2667 NEON_USHL_scalar = NEON_Q | NEONScalar | NEON_USHL,
2668 NEON_SSHL_scalar = NEON_Q | NEONScalar | NEON_SSHL,
2669 NEON_UQSHL_scalar = NEON_Q | NEONScalar | NEON_UQSHL,
2670 NEON_SQSHL_scalar = NEON_Q | NEONScalar | NEON_SQSHL,
2671 NEON_URSHL_scalar = NEON_Q | NEONScalar | NEON_URSHL,
2672 NEON_SRSHL_scalar = NEON_Q | NEONScalar | NEON_SRSHL,
2673 NEON_UQRSHL_scalar = NEON_Q | NEONScalar | NEON_UQRSHL,
2674 NEON_SQRSHL_scalar = NEON_Q | NEONScalar | NEON_SQRSHL,
2675 NEON_SQDMULH_scalar = NEON_Q | NEONScalar | NEON_SQDMULH,
2676 NEON_SQRDMULH_scalar = NEON_Q | NEONScalar | NEON_SQRDMULH,
2677
2678 // NEON floating point scalar instructions with three same-type operands.
2679 NEONScalar3SameFPFixed = NEONScalar3SameFixed | 0x0000C000,
2680 NEONScalar3SameFPFMask = NEONScalar3SameFMask | 0x0000C000,
2681 NEONScalar3SameFPMask = NEONScalar3SameMask | 0x00800000,
2682 NEON_FACGE_scalar = NEON_Q | NEONScalar | NEON_FACGE,
2683 NEON_FACGT_scalar = NEON_Q | NEONScalar | NEON_FACGT,
2684 NEON_FCMEQ_scalar = NEON_Q | NEONScalar | NEON_FCMEQ,
2685 NEON_FCMGE_scalar = NEON_Q | NEONScalar | NEON_FCMGE,
2686 NEON_FCMGT_scalar = NEON_Q | NEONScalar | NEON_FCMGT,
2687 NEON_FMULX_scalar = NEON_Q | NEONScalar | NEON_FMULX,
2688 NEON_FRECPS_scalar = NEON_Q | NEONScalar | NEON_FRECPS,
2689 NEON_FRSQRTS_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS,
2690 NEON_FABD_scalar = NEON_Q | NEONScalar | NEON_FABD
2691 };
2692
2693 // NEON scalar FP16 instructions with three same-type operands.
2694 enum NEONScalar3SameFP16Op {
2695 NEONScalar3SameFP16Fixed = 0x5E400400,
2696 NEONScalar3SameFP16FMask = 0xDF60C400,
2697 NEONScalar3SameFP16Mask = 0xFFE0FC00,
2698 NEON_FABD_H_scalar = NEON_Q | NEONScalar | NEON_FABD_H,
2699 NEON_FMULX_H_scalar = NEON_Q | NEONScalar | NEON_FMULX_H,
2700 NEON_FCMEQ_H_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_H,
2701 NEON_FCMGE_H_scalar = NEON_Q | NEONScalar | NEON_FCMGE_H,
2702 NEON_FCMGT_H_scalar = NEON_Q | NEONScalar | NEON_FCMGT_H,
2703 NEON_FACGE_H_scalar = NEON_Q | NEONScalar | NEON_FACGE_H,
2704 NEON_FACGT_H_scalar = NEON_Q | NEONScalar | NEON_FACGT_H,
2705 NEON_FRECPS_H_scalar = NEON_Q | NEONScalar | NEON_FRECPS_H,
2706 NEON_FRSQRTS_H_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS_H
2707 };
2708
2709 // 'Extra' NEON scalar instructions with three same-type operands.
2710 enum NEONScalar3SameExtraOp {
2711 NEONScalar3SameExtraFixed = 0x5E008400,
2712 NEONScalar3SameExtraFMask = 0xDF208400,
2713 NEONScalar3SameExtraMask = 0xFF20FC00,
2714 NEON_SQRDMLAH_scalar = NEON_Q | NEONScalar | NEON_SQRDMLAH,
2715 NEON_SQRDMLSH_scalar = NEON_Q | NEONScalar | NEON_SQRDMLSH
2716 };
2717
2718 // NEON scalar instructions with three different-type operands.
2719 enum NEONScalar3DiffOp {
2720 NEONScalar3DiffFixed = 0x5E200000,
2721 NEONScalar3DiffFMask = 0xDF200C00,
2722 NEONScalar3DiffMask = NEON_Q | NEONScalar | NEON3DifferentMask,
2723 NEON_SQDMLAL_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL,
2724 NEON_SQDMLSL_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL,
2725 NEON_SQDMULL_scalar = NEON_Q | NEONScalar | NEON_SQDMULL
2726 };
2727
2728 // NEON scalar instructions with indexed element operand.
2729 enum NEONScalarByIndexedElementOp {
2730 NEONScalarByIndexedElementFixed = 0x5F000000,
2731 NEONScalarByIndexedElementFMask = 0xDF000400,
2732 NEONScalarByIndexedElementMask = 0xFF00F400,
2733 NEON_SQDMLAL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL_byelement,
2734 NEON_SQDMLSL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL_byelement,
2735 NEON_SQDMULL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULL_byelement,
2736 NEON_SQDMULH_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULH_byelement,
2737 NEON_SQRDMULH_byelement_scalar
2738 = NEON_Q | NEONScalar | NEON_SQRDMULH_byelement,
2739 NEON_SQRDMLAH_byelement_scalar
2740 = NEON_Q | NEONScalar | NEON_SQRDMLAH_byelement,
2741 NEON_SQRDMLSH_byelement_scalar
2742 = NEON_Q | NEONScalar | NEON_SQRDMLSH_byelement,
2743 NEON_FMLA_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_H_byelement,
2744 NEON_FMLS_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_H_byelement,
2745 NEON_FMUL_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_H_byelement,
2746 NEON_FMULX_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_H_byelement,
2747
2748 // Floating point instructions.
2749 NEONScalarByIndexedElementFPFixed
2750 = NEONScalarByIndexedElementFixed | 0x00800000,
2751 NEONScalarByIndexedElementFPMask
2752 = NEONScalarByIndexedElementMask | 0x00800000,
2753 NEON_FMLA_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_byelement,
2754 NEON_FMLS_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_byelement,
2755 NEON_FMUL_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_byelement,
2756 NEON_FMULX_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_byelement
2757 };
2758
2759 // NEON scalar register copy.
2760 enum NEONScalarCopyOp {
2761 NEONScalarCopyFixed = 0x5E000400,
2762 NEONScalarCopyFMask = 0xDFE08400,
2763 NEONScalarCopyMask = 0xFFE0FC00,
2764 NEON_DUP_ELEMENT_scalar = NEON_Q | NEONScalar | NEON_DUP_ELEMENT
2765 };
2766
2767 // NEON scalar pairwise instructions.
2768 enum NEONScalarPairwiseOp {
2769 NEONScalarPairwiseFixed = 0x5E300800,
2770 NEONScalarPairwiseFMask = 0xDF3E0C00,
2771 NEONScalarPairwiseMask = 0xFFB1F800,
2772 NEON_ADDP_scalar = NEONScalarPairwiseFixed | 0x0081B000,
2773 NEON_FMAXNMP_h_scalar = NEONScalarPairwiseFixed | 0x0000C000,
2774 NEON_FADDP_h_scalar = NEONScalarPairwiseFixed | 0x0000D000,
2775 NEON_FMAXP_h_scalar = NEONScalarPairwiseFixed | 0x0000F000,
2776 NEON_FMINNMP_h_scalar = NEONScalarPairwiseFixed | 0x0080C000,
2777 NEON_FMINP_h_scalar = NEONScalarPairwiseFixed | 0x0080F000,
2778 NEON_FMAXNMP_scalar = NEONScalarPairwiseFixed | 0x2000C000,
2779 NEON_FMINNMP_scalar = NEONScalarPairwiseFixed | 0x2080C000,
2780 NEON_FADDP_scalar = NEONScalarPairwiseFixed | 0x2000D000,
2781 NEON_FMAXP_scalar = NEONScalarPairwiseFixed | 0x2000F000,
2782 NEON_FMINP_scalar = NEONScalarPairwiseFixed | 0x2080F000
2783 };
2784
2785 // NEON scalar shift immediate.
2786 enum NEONScalarShiftImmediateOp {
2787 NEONScalarShiftImmediateFixed = 0x5F000400,
2788 NEONScalarShiftImmediateFMask = 0xDF800400,
2789 NEONScalarShiftImmediateMask = 0xFF80FC00,
2790 NEON_SHL_scalar = NEON_Q | NEONScalar | NEON_SHL,
2791 NEON_SLI_scalar = NEON_Q | NEONScalar | NEON_SLI,
2792 NEON_SRI_scalar = NEON_Q | NEONScalar | NEON_SRI,
2793 NEON_SSHR_scalar = NEON_Q | NEONScalar | NEON_SSHR,
2794 NEON_USHR_scalar = NEON_Q | NEONScalar | NEON_USHR,
2795 NEON_SRSHR_scalar = NEON_Q | NEONScalar | NEON_SRSHR,
2796 NEON_URSHR_scalar = NEON_Q | NEONScalar | NEON_URSHR,
2797 NEON_SSRA_scalar = NEON_Q | NEONScalar | NEON_SSRA,
2798 NEON_USRA_scalar = NEON_Q | NEONScalar | NEON_USRA,
2799 NEON_SRSRA_scalar = NEON_Q | NEONScalar | NEON_SRSRA,
2800 NEON_URSRA_scalar = NEON_Q | NEONScalar | NEON_URSRA,
2801 NEON_UQSHRN_scalar = NEON_Q | NEONScalar | NEON_UQSHRN,
2802 NEON_UQRSHRN_scalar = NEON_Q | NEONScalar | NEON_UQRSHRN,
2803 NEON_SQSHRN_scalar = NEON_Q | NEONScalar | NEON_SQSHRN,
2804 NEON_SQRSHRN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRN,
2805 NEON_SQSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQSHRUN,
2806 NEON_SQRSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRUN,
2807 NEON_SQSHLU_scalar = NEON_Q | NEONScalar | NEON_SQSHLU,
2808 NEON_SQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_SQSHL_imm,
2809 NEON_UQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_UQSHL_imm,
2810 NEON_SCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_SCVTF_imm,
2811 NEON_UCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_UCVTF_imm,
2812 NEON_FCVTZS_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_imm,
2813 NEON_FCVTZU_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_imm
2814 };
2815
2816 enum SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsOp {
2817 SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed = 0x84A00000,
2818 SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08000,
2819 SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E000,
2820 LD1SH_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed,
2821 LDFF1SH_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00002000,
2822 LD1H_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00004000,
2823 LDFF1H_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00006000
2824 };
2825
2826 enum SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsOp {
2827 SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed = 0x85200000,
2828 SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08000,
2829 SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E000,
2830 LD1W_z_p_bz_s_x32_scaled = SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed | 0x00004000,
2831 LDFF1W_z_p_bz_s_x32_scaled = SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed | 0x00006000
2832 };
2833
2834 enum SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsOp {
2835 SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed = 0x84000000,
2836 SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFMask = 0xFE208000,
2837 SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsMask = 0xFFA0E000,
2838 LD1SB_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed,
2839 LDFF1SB_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00002000,
2840 LD1B_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00004000,
2841 LDFF1B_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00006000,
2842 LD1SH_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00800000,
2843 LDFF1SH_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00802000,
2844 LD1H_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00804000,
2845 LDFF1H_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00806000,
2846 LD1W_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x01004000,
2847 LDFF1W_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x01006000
2848 };
2849
2850 enum SVE32BitGatherLoad_VectorPlusImmOp {
2851 SVE32BitGatherLoad_VectorPlusImmFixed = 0x84208000,
2852 SVE32BitGatherLoad_VectorPlusImmFMask = 0xFE608000,
2853 SVE32BitGatherLoad_VectorPlusImmMask = 0xFFE0E000,
2854 LD1SB_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed,
2855 LDFF1SB_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00002000,
2856 LD1B_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00004000,
2857 LDFF1B_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00006000,
2858 LD1SH_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00800000,
2859 LDFF1SH_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00802000,
2860 LD1H_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00804000,
2861 LDFF1H_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00806000,
2862 LD1W_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x01004000,
2863 LDFF1W_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x01006000
2864 };
2865
2866 enum SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsOp {
2867 SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed = 0x84200000,
2868 SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08010,
2869 SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E010,
2870 PRFB_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed,
2871 PRFH_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00002000,
2872 PRFW_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00004000,
2873 PRFD_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00006000
2874 };
2875
2876 enum SVE32BitGatherPrefetch_VectorPlusImmOp {
2877 SVE32BitGatherPrefetch_VectorPlusImmFixed = 0x8400E000,
2878 SVE32BitGatherPrefetch_VectorPlusImmFMask = 0xFE60E010,
2879 SVE32BitGatherPrefetch_VectorPlusImmMask = 0xFFE0E010,
2880 PRFB_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed,
2881 PRFH_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x00800000,
2882 PRFW_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x01000000,
2883 PRFD_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x01800000
2884 };
2885
2886 enum SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsOp {
2887 SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed = 0xE4608000,
2888 SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFMask = 0xFE60A000,
2889 SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsMask = 0xFFE0A000,
2890 ST1H_z_p_bz_s_x32_scaled = SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed | 0x00800000,
2891 ST1W_z_p_bz_s_x32_scaled = SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed | 0x01000000
2892 };
2893
2894 enum SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsOp {
2895 SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed = 0xE4408000,
2896 SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFMask = 0xFE60A000,
2897 SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsMask = 0xFFE0A000,
2898 ST1B_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed,
2899 ST1H_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed | 0x00800000,
2900 ST1W_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed | 0x01000000
2901 };
2902
2903 enum SVE32BitScatterStore_VectorPlusImmOp {
2904 SVE32BitScatterStore_VectorPlusImmFixed = 0xE460A000,
2905 SVE32BitScatterStore_VectorPlusImmFMask = 0xFE60E000,
2906 SVE32BitScatterStore_VectorPlusImmMask = 0xFFE0E000,
2907 ST1B_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed,
2908 ST1H_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed | 0x00800000,
2909 ST1W_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed | 0x01000000
2910 };
2911
2912 enum SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsOp {
2913 SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed = 0xC4200000,
2914 SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFMask = 0xFE208000,
2915 SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsMask = 0xFFA0E000,
2916 LD1SH_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00800000,
2917 LDFF1SH_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00802000,
2918 LD1H_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00804000,
2919 LDFF1H_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00806000,
2920 LD1SW_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01000000,
2921 LDFF1SW_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01002000,
2922 LD1W_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01004000,
2923 LDFF1W_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01006000,
2924 LD1D_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01804000,
2925 LDFF1D_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01806000
2926 };
2927
2928 enum SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsOp {
2929 SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed = 0xC4608000,
2930 SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFMask = 0xFE608000,
2931 SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E000,
2932 LD1SH_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00800000,
2933 LDFF1SH_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00802000,
2934 LD1H_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00804000,
2935 LDFF1H_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00806000,
2936 LD1SW_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01000000,
2937 LDFF1SW_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01002000,
2938 LD1W_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01004000,
2939 LDFF1W_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01006000,
2940 LD1D_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01804000,
2941 LDFF1D_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01806000
2942 };
2943
2944 enum SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsOp {
2945 SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed = 0xC4408000,
2946 SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFMask = 0xFE608000,
2947 SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsMask = 0xFFE0E000,
2948 LD1SB_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed,
2949 LDFF1SB_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00002000,
2950 LD1B_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00004000,
2951 LDFF1B_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00006000,
2952 LD1SH_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00800000,
2953 LDFF1SH_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00802000,
2954 LD1H_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00804000,
2955 LDFF1H_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00806000,
2956 LD1SW_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01000000,
2957 LDFF1SW_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01002000,
2958 LD1W_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01004000,
2959 LDFF1W_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01006000,
2960 LD1D_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01804000,
2961 LDFF1D_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01806000
2962 };
2963
2964 enum SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsOp {
2965 SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed = 0xC4000000,
2966 SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFMask = 0xFE208000,
2967 SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsMask = 0xFFA0E000,
2968 LD1SB_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed,
2969 LDFF1SB_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00002000,
2970 LD1B_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00004000,
2971 LDFF1B_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00006000,
2972 LD1SH_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00800000,
2973 LDFF1SH_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00802000,
2974 LD1H_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00804000,
2975 LDFF1H_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00806000,
2976 LD1SW_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01000000,
2977 LDFF1SW_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01002000,
2978 LD1W_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01004000,
2979 LDFF1W_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01006000,
2980 LD1D_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01804000,
2981 LDFF1D_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01806000
2982 };
2983
2984 enum SVE64BitGatherLoad_VectorPlusImmOp {
2985 SVE64BitGatherLoad_VectorPlusImmFixed = 0xC4208000,
2986 SVE64BitGatherLoad_VectorPlusImmFMask = 0xFE608000,
2987 SVE64BitGatherLoad_VectorPlusImmMask = 0xFFE0E000,
2988 LD1SB_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed,
2989 LDFF1SB_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00002000,
2990 LD1B_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00004000,
2991 LDFF1B_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00006000,
2992 LD1SH_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00800000,
2993 LDFF1SH_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00802000,
2994 LD1H_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00804000,
2995 LDFF1H_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00806000,
2996 LD1SW_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01000000,
2997 LDFF1SW_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01002000,
2998 LD1W_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01004000,
2999 LDFF1W_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01006000,
3000 LD1D_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01804000,
3001 LDFF1D_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01806000
3002 };
3003
3004 enum SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsOp {
3005 SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed = 0xC4608000,
3006 SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFMask = 0xFFE08010,
3007 SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E010,
3008 PRFB_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed,
3009 PRFH_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00002000,
3010 PRFW_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00004000,
3011 PRFD_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00006000
3012 };
3013
3014 enum SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsOp {
3015 SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed = 0xC4200000,
3016 SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFMask = 0xFFA08010,
3017 SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsMask = 0xFFA0E010,
3018 PRFB_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed,
3019 PRFH_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00002000,
3020 PRFW_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00004000,
3021 PRFD_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00006000
3022 };
3023
3024 enum SVE64BitGatherPrefetch_VectorPlusImmOp {
3025 SVE64BitGatherPrefetch_VectorPlusImmFixed = 0xC400E000,
3026 SVE64BitGatherPrefetch_VectorPlusImmFMask = 0xFE60E010,
3027 SVE64BitGatherPrefetch_VectorPlusImmMask = 0xFFE0E010,
3028 PRFB_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed,
3029 PRFH_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x00800000,
3030 PRFW_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x01000000,
3031 PRFD_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x01800000
3032 };
3033
3034 enum SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsOp {
3035 SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed = 0xE420A000,
3036 SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFMask = 0xFE60E000,
3037 SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E000,
3038 ST1H_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x00800000,
3039 ST1W_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x01000000,
3040 ST1D_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x01800000
3041 };
3042
3043 enum SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsOp {
3044 SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed = 0xE400A000,
3045 SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFMask = 0xFE60E000,
3046 SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsMask = 0xFFE0E000,
3047 ST1B_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed,
3048 ST1H_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x00800000,
3049 ST1W_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x01000000,
3050 ST1D_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x01800000
3051 };
3052
3053 enum SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsOp {
3054 SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed = 0xE4208000,
3055 SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFMask = 0xFE60A000,
3056 SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsMask = 0xFFE0A000,
3057 ST1H_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00800000,
3058 ST1W_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x01000000,
3059 ST1D_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x01800000
3060 };
3061
3062 enum SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsOp {
3063 SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed = 0xE4008000,
3064 SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFMask = 0xFE60A000,
3065 SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsMask = 0xFFE0A000,
3066 ST1B_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed,
3067 ST1H_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00800000,
3068 ST1W_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01000000,
3069 ST1D_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01800000
3070 };
3071
3072 enum SVE64BitScatterStore_VectorPlusImmOp {
3073 SVE64BitScatterStore_VectorPlusImmFixed = 0xE440A000,
3074 SVE64BitScatterStore_VectorPlusImmFMask = 0xFE60E000,
3075 SVE64BitScatterStore_VectorPlusImmMask = 0xFFE0E000,
3076 ST1B_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed,
3077 ST1H_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x00800000,
3078 ST1W_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x01000000,
3079 ST1D_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x01800000
3080 };
3081
3082 enum SVEAddressGenerationOp {
3083 SVEAddressGenerationFixed = 0x0420A000,
3084 SVEAddressGenerationFMask = 0xFF20F000,
3085 SVEAddressGenerationMask = 0xFFE0F000,
3086 ADR_z_az_d_s32_scaled = SVEAddressGenerationFixed,
3087 ADR_z_az_d_u32_scaled = SVEAddressGenerationFixed | 0x00400000,
3088 ADR_z_az_s_same_scaled = SVEAddressGenerationFixed | 0x00800000,
3089 ADR_z_az_d_same_scaled = SVEAddressGenerationFixed | 0x00C00000
3090 };
3091
3092 enum SVEBitwiseLogicalUnpredicatedOp {
3093 SVEBitwiseLogicalUnpredicatedFixed = 0x04202000,
3094 SVEBitwiseLogicalUnpredicatedFMask = 0xFF20E000,
3095 SVEBitwiseLogicalUnpredicatedMask = 0xFFE0FC00,
3096 AND_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00001000,
3097 ORR_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00401000,
3098 EOR_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00801000,
3099 BIC_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00C01000
3100 };
3101
3102 enum SVEBitwiseLogicalWithImm_UnpredicatedOp {
3103 SVEBitwiseLogicalWithImm_UnpredicatedFixed = 0x05000000,
3104 SVEBitwiseLogicalWithImm_UnpredicatedFMask = 0xFF3C0000,
3105 SVEBitwiseLogicalWithImm_UnpredicatedMask = 0xFFFC0000,
3106 ORR_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed,
3107 EOR_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed | 0x00400000,
3108 AND_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed | 0x00800000
3109 };
3110
3111 enum SVEBitwiseLogical_PredicatedOp {
3112 SVEBitwiseLogical_PredicatedFixed = 0x04180000,
3113 SVEBitwiseLogical_PredicatedFMask = 0xFF38E000,
3114 SVEBitwiseLogical_PredicatedMask = 0xFF3FE000,
3115 ORR_z_p_zz = SVEBitwiseLogical_PredicatedFixed,
3116 EOR_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00010000,
3117 AND_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00020000,
3118 BIC_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00030000
3119 };
3120
3121 enum SVEBitwiseShiftByImm_PredicatedOp {
3122 SVEBitwiseShiftByImm_PredicatedFixed = 0x04008000,
3123 SVEBitwiseShiftByImm_PredicatedFMask = 0xFF30E000,
3124 SVEBitwiseShiftByImm_PredicatedMask = 0xFF3FE000,
3125 ASR_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed,
3126 LSR_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00010000,
3127 LSL_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00030000,
3128 ASRD_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00040000
3129 };
3130
3131 enum SVEBitwiseShiftByVector_PredicatedOp {
3132 SVEBitwiseShiftByVector_PredicatedFixed = 0x04108000,
3133 SVEBitwiseShiftByVector_PredicatedFMask = 0xFF38E000,
3134 SVEBitwiseShiftByVector_PredicatedMask = 0xFF3FE000,
3135 ASR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed,
3136 LSR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00010000,
3137 LSL_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00030000,
3138 ASRR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00040000,
3139 LSRR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00050000,
3140 LSLR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00070000
3141 };
3142
3143 enum SVEBitwiseShiftByWideElements_PredicatedOp {
3144 SVEBitwiseShiftByWideElements_PredicatedFixed = 0x04188000,
3145 SVEBitwiseShiftByWideElements_PredicatedFMask = 0xFF38E000,
3146 SVEBitwiseShiftByWideElements_PredicatedMask = 0xFF3FE000,
3147 ASR_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed,
3148 LSR_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed | 0x00010000,
3149 LSL_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed | 0x00030000
3150 };
3151
3152 enum SVEBitwiseShiftUnpredicatedOp {
3153 SVEBitwiseShiftUnpredicatedFixed = 0x04208000,
3154 SVEBitwiseShiftUnpredicatedFMask = 0xFF20E000,
3155 SVEBitwiseShiftUnpredicatedMask = 0xFF20FC00,
3156 ASR_z_zw = SVEBitwiseShiftUnpredicatedFixed,
3157 LSR_z_zw = SVEBitwiseShiftUnpredicatedFixed | 0x00000400,
3158 LSL_z_zw = SVEBitwiseShiftUnpredicatedFixed | 0x00000C00,
3159 ASR_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001000,
3160 LSR_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001400,
3161 LSL_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001C00
3162 };
3163
3164 enum SVEBroadcastBitmaskImmOp {
3165 SVEBroadcastBitmaskImmFixed = 0x05C00000,
3166 SVEBroadcastBitmaskImmFMask = 0xFFFC0000,
3167 SVEBroadcastBitmaskImmMask = 0xFFFC0000,
3168 DUPM_z_i = SVEBroadcastBitmaskImmFixed
3169 };
3170
3171 enum SVEBroadcastFPImm_UnpredicatedOp {
3172 SVEBroadcastFPImm_UnpredicatedFixed = 0x2539C000,
3173 SVEBroadcastFPImm_UnpredicatedFMask = 0xFF39C000,
3174 SVEBroadcastFPImm_UnpredicatedMask = 0xFF3FE000,
3175 FDUP_z_i = SVEBroadcastFPImm_UnpredicatedFixed
3176 };
3177
3178 enum SVEBroadcastGeneralRegisterOp {
3179 SVEBroadcastGeneralRegisterFixed = 0x05203800,
3180 SVEBroadcastGeneralRegisterFMask = 0xFF3FFC00,
3181 SVEBroadcastGeneralRegisterMask = 0xFF3FFC00,
3182 DUP_z_r = SVEBroadcastGeneralRegisterFixed
3183 };
3184
3185 enum SVEBroadcastIndexElementOp {
3186 SVEBroadcastIndexElementFixed = 0x05202000,
3187 SVEBroadcastIndexElementFMask = 0xFF20FC00,
3188 SVEBroadcastIndexElementMask = 0xFF20FC00,
3189 DUP_z_zi = SVEBroadcastIndexElementFixed
3190 };
3191
3192 enum SVEBroadcastIntImm_UnpredicatedOp {
3193 SVEBroadcastIntImm_UnpredicatedFixed = 0x2538C000,
3194 SVEBroadcastIntImm_UnpredicatedFMask = 0xFF39C000,
3195 SVEBroadcastIntImm_UnpredicatedMask = 0xFF3FC000,
3196 DUP_z_i = SVEBroadcastIntImm_UnpredicatedFixed
3197 };
3198
3199 enum SVECompressActiveElementsOp {
3200 SVECompressActiveElementsFixed = 0x05A18000,
3201 SVECompressActiveElementsFMask = 0xFFBFE000,
3202 SVECompressActiveElementsMask = 0xFFBFE000,
3203 COMPACT_z_p_z = SVECompressActiveElementsFixed
3204 };
3205
3206 enum SVEConditionallyBroadcastElementToVectorOp {
3207 SVEConditionallyBroadcastElementToVectorFixed = 0x05288000,
3208 SVEConditionallyBroadcastElementToVectorFMask = 0xFF3EE000,
3209 SVEConditionallyBroadcastElementToVectorMask = 0xFF3FE000,
3210 CLASTA_z_p_zz = SVEConditionallyBroadcastElementToVectorFixed,
3211 CLASTB_z_p_zz = SVEConditionallyBroadcastElementToVectorFixed | 0x00010000
3212 };
3213
3214 enum SVEConditionallyExtractElementToGeneralRegisterOp {
3215 SVEConditionallyExtractElementToGeneralRegisterFixed = 0x0530A000,
3216 SVEConditionallyExtractElementToGeneralRegisterFMask = 0xFF3EE000,
3217 SVEConditionallyExtractElementToGeneralRegisterMask = 0xFF3FE000,
3218 CLASTA_r_p_z = SVEConditionallyExtractElementToGeneralRegisterFixed,
3219 CLASTB_r_p_z = SVEConditionallyExtractElementToGeneralRegisterFixed | 0x00010000
3220 };
3221
3222 enum SVEConditionallyExtractElementToSIMDFPScalarOp {
3223 SVEConditionallyExtractElementToSIMDFPScalarFixed = 0x052A8000,
3224 SVEConditionallyExtractElementToSIMDFPScalarFMask = 0xFF3EE000,
3225 SVEConditionallyExtractElementToSIMDFPScalarMask = 0xFF3FE000,
3226 CLASTA_v_p_z = SVEConditionallyExtractElementToSIMDFPScalarFixed,
3227 CLASTB_v_p_z = SVEConditionallyExtractElementToSIMDFPScalarFixed | 0x00010000
3228 };
3229
3230 enum SVEConditionallyTerminateScalarsOp {
3231 SVEConditionallyTerminateScalarsFixed = 0x25202000,
3232 SVEConditionallyTerminateScalarsFMask = 0xFF20FC0F,
3233 SVEConditionallyTerminateScalarsMask = 0xFFA0FC1F,
3234 CTERMEQ_rr = SVEConditionallyTerminateScalarsFixed | 0x00800000,
3235 CTERMNE_rr = SVEConditionallyTerminateScalarsFixed | 0x00800010
3236 };
3237
3238 enum SVEConstructivePrefix_UnpredicatedOp {
3239 SVEConstructivePrefix_UnpredicatedFixed = 0x0420BC00,
3240 SVEConstructivePrefix_UnpredicatedFMask = 0xFF20FC00,
3241 SVEConstructivePrefix_UnpredicatedMask = 0xFFFFFC00,
3242 MOVPRFX_z_z = SVEConstructivePrefix_UnpredicatedFixed
3243 };
3244
3245 enum SVEContiguousFirstFaultLoad_ScalarPlusScalarOp {
3246 SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed = 0xA4006000,
3247 SVEContiguousFirstFaultLoad_ScalarPlusScalarFMask = 0xFE00E000,
3248 SVEContiguousFirstFaultLoad_ScalarPlusScalarMask = 0xFFE0E000,
3249 LDFF1B_z_p_br_u8 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed,
3250 LDFF1B_z_p_br_u16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00200000,
3251 LDFF1B_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00400000,
3252 LDFF1B_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00600000,
3253 LDFF1SW_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00800000,
3254 LDFF1H_z_p_br_u16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00A00000,
3255 LDFF1H_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00C00000,
3256 LDFF1H_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00E00000,
3257 LDFF1SH_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01000000,
3258 LDFF1SH_z_p_br_s32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01200000,
3259 LDFF1W_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01400000,
3260 LDFF1W_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01600000,
3261 LDFF1SB_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01800000,
3262 LDFF1SB_z_p_br_s32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01A00000,
3263 LDFF1SB_z_p_br_s16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01C00000,
3264 LDFF1D_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01E00000
3265 };
3266
3267 enum SVEContiguousLoad_ScalarPlusImmOp {
3268 SVEContiguousLoad_ScalarPlusImmFixed = 0xA400A000,
3269 SVEContiguousLoad_ScalarPlusImmFMask = 0xFE10E000,
3270 SVEContiguousLoad_ScalarPlusImmMask = 0xFFF0E000,
3271 LD1B_z_p_bi_u8 = SVEContiguousLoad_ScalarPlusImmFixed,
3272 LD1B_z_p_bi_u16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00200000,
3273 LD1B_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00400000,
3274 LD1B_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00600000,
3275 LD1SW_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00800000,
3276 LD1H_z_p_bi_u16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00A00000,
3277 LD1H_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00C00000,
3278 LD1H_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00E00000,
3279 LD1SH_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01000000,
3280 LD1SH_z_p_bi_s32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01200000,
3281 LD1W_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01400000,
3282 LD1W_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01600000,
3283 LD1SB_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01800000,
3284 LD1SB_z_p_bi_s32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01A00000,
3285 LD1SB_z_p_bi_s16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01C00000,
3286 LD1D_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01E00000
3287 };
3288
3289 enum SVEContiguousLoad_ScalarPlusScalarOp {
3290 SVEContiguousLoad_ScalarPlusScalarFixed = 0xA4004000,
3291 SVEContiguousLoad_ScalarPlusScalarFMask = 0xFE00E000,
3292 SVEContiguousLoad_ScalarPlusScalarMask = 0xFFE0E000,
3293 LD1B_z_p_br_u8 = SVEContiguousLoad_ScalarPlusScalarFixed,
3294 LD1B_z_p_br_u16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00200000,
3295 LD1B_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00400000,
3296 LD1B_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00600000,
3297 LD1SW_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00800000,
3298 LD1H_z_p_br_u16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00A00000,
3299 LD1H_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00C00000,
3300 LD1H_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00E00000,
3301 LD1SH_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01000000,
3302 LD1SH_z_p_br_s32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01200000,
3303 LD1W_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01400000,
3304 LD1W_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01600000,
3305 LD1SB_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01800000,
3306 LD1SB_z_p_br_s32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01A00000,
3307 LD1SB_z_p_br_s16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01C00000,
3308 LD1D_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01E00000
3309 };
3310
3311 enum SVEContiguousNonFaultLoad_ScalarPlusImmOp {
3312 SVEContiguousNonFaultLoad_ScalarPlusImmFixed = 0xA410A000,
3313 SVEContiguousNonFaultLoad_ScalarPlusImmFMask = 0xFE10E000,
3314 SVEContiguousNonFaultLoad_ScalarPlusImmMask = 0xFFF0E000,
3315 LDNF1B_z_p_bi_u8 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed,
3316 LDNF1B_z_p_bi_u16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00200000,
3317 LDNF1B_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00400000,
3318 LDNF1B_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00600000,
3319 LDNF1SW_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00800000,
3320 LDNF1H_z_p_bi_u16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00A00000,
3321 LDNF1H_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00C00000,
3322 LDNF1H_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00E00000,
3323 LDNF1SH_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01000000,
3324 LDNF1SH_z_p_bi_s32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01200000,
3325 LDNF1W_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01400000,
3326 LDNF1W_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01600000,
3327 LDNF1SB_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01800000,
3328 LDNF1SB_z_p_bi_s32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01A00000,
3329 LDNF1SB_z_p_bi_s16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01C00000,
3330 LDNF1D_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01E00000
3331 };
3332
3333 enum SVEContiguousNonTemporalLoad_ScalarPlusImmOp {
3334 SVEContiguousNonTemporalLoad_ScalarPlusImmFixed = 0xA400E000,
3335 SVEContiguousNonTemporalLoad_ScalarPlusImmFMask = 0xFE70E000,
3336 SVEContiguousNonTemporalLoad_ScalarPlusImmMask = 0xFFF0E000,
3337 LDNT1B_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed,
3338 LDNT1H_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x00800000,
3339 LDNT1W_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x01000000,
3340 LDNT1D_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x01800000
3341 };
3342
3343 enum SVEContiguousNonTemporalLoad_ScalarPlusScalarOp {
3344 SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed = 0xA400C000,
3345 SVEContiguousNonTemporalLoad_ScalarPlusScalarFMask = 0xFE60E000,
3346 SVEContiguousNonTemporalLoad_ScalarPlusScalarMask = 0xFFE0E000,
3347 LDNT1B_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed,
3348 LDNT1H_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x00800000,
3349 LDNT1W_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x01000000,
3350 LDNT1D_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x01800000
3351 };
3352
3353 enum SVEContiguousNonTemporalStore_ScalarPlusImmOp {
3354 SVEContiguousNonTemporalStore_ScalarPlusImmFixed = 0xE410E000,
3355 SVEContiguousNonTemporalStore_ScalarPlusImmFMask = 0xFE70E000,
3356 SVEContiguousNonTemporalStore_ScalarPlusImmMask = 0xFFF0E000,
3357 STNT1B_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed,
3358 STNT1H_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x00800000,
3359 STNT1W_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x01000000,
3360 STNT1D_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x01800000
3361 };
3362
3363 enum SVEContiguousNonTemporalStore_ScalarPlusScalarOp {
3364 SVEContiguousNonTemporalStore_ScalarPlusScalarFixed = 0xE4006000,
3365 SVEContiguousNonTemporalStore_ScalarPlusScalarFMask = 0xFE60E000,
3366 SVEContiguousNonTemporalStore_ScalarPlusScalarMask = 0xFFE0E000,
3367 STNT1B_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed,
3368 STNT1H_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x00800000,
3369 STNT1W_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x01000000,
3370 STNT1D_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x01800000
3371 };
3372
3373 enum SVEContiguousPrefetch_ScalarPlusImmOp {
3374 SVEContiguousPrefetch_ScalarPlusImmFixed = 0x85C00000,
3375 SVEContiguousPrefetch_ScalarPlusImmFMask = 0xFFC08010,
3376 SVEContiguousPrefetch_ScalarPlusImmMask = 0xFFC0E010,
3377 PRFB_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed,
3378 PRFH_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00002000,
3379 PRFW_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00004000,
3380 PRFD_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00006000
3381 };
3382
3383 enum SVEContiguousPrefetch_ScalarPlusScalarOp {
3384 SVEContiguousPrefetch_ScalarPlusScalarFixed = 0x8400C000,
3385 SVEContiguousPrefetch_ScalarPlusScalarFMask = 0xFE60E010,
3386 SVEContiguousPrefetch_ScalarPlusScalarMask = 0xFFE0E010,
3387 PRFB_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed,
3388 PRFH_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x00800000,
3389 PRFW_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x01000000,
3390 PRFD_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x01800000
3391 };
3392
3393 enum SVEContiguousStore_ScalarPlusImmOp {
3394 SVEContiguousStore_ScalarPlusImmFixed = 0xE400E000,
3395 SVEContiguousStore_ScalarPlusImmFMask = 0xFE10E000,
3396 SVEContiguousStore_ScalarPlusImmMask = 0xFF90E000,
3397 ST1B_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed,
3398 ST1H_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x00800000,
3399 ST1W_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x01000000,
3400 ST1D_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x01800000
3401 };
3402
3403 enum SVEContiguousStore_ScalarPlusScalarOp {
3404 SVEContiguousStore_ScalarPlusScalarFixed = 0xE4004000,
3405 SVEContiguousStore_ScalarPlusScalarFMask = 0xFE00E000,
3406 SVEContiguousStore_ScalarPlusScalarMask = 0xFF80E000,
3407 ST1B_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed,
3408 ST1H_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x00800000,
3409 ST1W_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x01000000,
3410 ST1D_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x01800000
3411 };
3412
3413 enum SVECopyFPImm_PredicatedOp {
3414 SVECopyFPImm_PredicatedFixed = 0x0510C000,
3415 SVECopyFPImm_PredicatedFMask = 0xFF30E000,
3416 SVECopyFPImm_PredicatedMask = 0xFF30E000,
3417 FCPY_z_p_i = SVECopyFPImm_PredicatedFixed
3418 };
3419
3420 enum SVECopyGeneralRegisterToVector_PredicatedOp {
3421 SVECopyGeneralRegisterToVector_PredicatedFixed = 0x0528A000,
3422 SVECopyGeneralRegisterToVector_PredicatedFMask = 0xFF3FE000,
3423 SVECopyGeneralRegisterToVector_PredicatedMask = 0xFF3FE000,
3424 CPY_z_p_r = SVECopyGeneralRegisterToVector_PredicatedFixed
3425 };
3426
3427 enum SVECopyIntImm_PredicatedOp {
3428 SVECopyIntImm_PredicatedFixed = 0x05100000,
3429 SVECopyIntImm_PredicatedFMask = 0xFF308000,
3430 SVECopyIntImm_PredicatedMask = 0xFF308000,
3431 CPY_z_p_i = SVECopyIntImm_PredicatedFixed
3432 };
3433
3434 enum SVECopySIMDFPScalarRegisterToVector_PredicatedOp {
3435 SVECopySIMDFPScalarRegisterToVector_PredicatedFixed = 0x05208000,
3436 SVECopySIMDFPScalarRegisterToVector_PredicatedFMask = 0xFF3FE000,
3437 SVECopySIMDFPScalarRegisterToVector_PredicatedMask = 0xFF3FE000,
3438 CPY_z_p_v = SVECopySIMDFPScalarRegisterToVector_PredicatedFixed
3439 };
3440
3441 enum SVEElementCountOp {
3442 SVEElementCountFixed = 0x0420E000,
3443 SVEElementCountFMask = 0xFF30F800,
3444 SVEElementCountMask = 0xFFF0FC00,
3445 CNTB_r_s = SVEElementCountFixed,
3446 CNTH_r_s = SVEElementCountFixed | 0x00400000,
3447 CNTW_r_s = SVEElementCountFixed | 0x00800000,
3448 CNTD_r_s = SVEElementCountFixed | 0x00C00000
3449 };
3450
3451 enum SVEExtractElementToGeneralRegisterOp {
3452 SVEExtractElementToGeneralRegisterFixed = 0x0520A000,
3453 SVEExtractElementToGeneralRegisterFMask = 0xFF3EE000,
3454 SVEExtractElementToGeneralRegisterMask = 0xFF3FE000,
3455 LASTA_r_p_z = SVEExtractElementToGeneralRegisterFixed,
3456 LASTB_r_p_z = SVEExtractElementToGeneralRegisterFixed | 0x00010000
3457 };
3458
3459 enum SVEExtractElementToSIMDFPScalarRegisterOp {
3460 SVEExtractElementToSIMDFPScalarRegisterFixed = 0x05228000,
3461 SVEExtractElementToSIMDFPScalarRegisterFMask = 0xFF3EE000,
3462 SVEExtractElementToSIMDFPScalarRegisterMask = 0xFF3FE000,
3463 LASTA_v_p_z = SVEExtractElementToSIMDFPScalarRegisterFixed,
3464 LASTB_v_p_z = SVEExtractElementToSIMDFPScalarRegisterFixed | 0x00010000
3465 };
3466
3467 enum SVEFFRInitialiseOp {
3468 SVEFFRInitialiseFixed = 0x252C9000,
3469 SVEFFRInitialiseFMask = 0xFF3FFFFF,
3470 SVEFFRInitialiseMask = 0xFFFFFFFF,
3471 SETFFR_f = SVEFFRInitialiseFixed
3472 };
3473
3474 enum SVEFFRWriteFromPredicateOp {
3475 SVEFFRWriteFromPredicateFixed = 0x25289000,
3476 SVEFFRWriteFromPredicateFMask = 0xFF3FFE1F,
3477 SVEFFRWriteFromPredicateMask = 0xFFFFFE1F,
3478 WRFFR_f_p = SVEFFRWriteFromPredicateFixed
3479 };
3480
3481 enum SVEFPAccumulatingReductionOp {
3482 SVEFPAccumulatingReductionFixed = 0x65182000,
3483 SVEFPAccumulatingReductionFMask = 0xFF38E000,
3484 SVEFPAccumulatingReductionMask = 0xFF3FE000,
3485 FADDA_v_p_z = SVEFPAccumulatingReductionFixed
3486 };
3487
3488 enum SVEFPArithmeticUnpredicatedOp {
3489 SVEFPArithmeticUnpredicatedFixed = 0x65000000,
3490 SVEFPArithmeticUnpredicatedFMask = 0xFF20E000,
3491 SVEFPArithmeticUnpredicatedMask = 0xFF20FC00,
3492 FADD_z_zz = SVEFPArithmeticUnpredicatedFixed,
3493 FSUB_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000400,
3494 FMUL_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000800,
3495 FTSMUL_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000C00,
3496 FRECPS_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00001800,
3497 FRSQRTS_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00001C00
3498 };
3499
3500 enum SVEFPArithmeticWithImm_PredicatedOp {
3501 SVEFPArithmeticWithImm_PredicatedFixed = 0x65188000,
3502 SVEFPArithmeticWithImm_PredicatedFMask = 0xFF38E3C0,
3503 SVEFPArithmeticWithImm_PredicatedMask = 0xFF3FE3C0,
3504 FADD_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed,
3505 FSUB_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00010000,
3506 FMUL_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00020000,
3507 FSUBR_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00030000,
3508 FMAXNM_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00040000,
3509 FMINNM_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00050000,
3510 FMAX_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00060000,
3511 FMIN_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00070000
3512 };
3513
3514 enum SVEFPArithmetic_PredicatedOp {
3515 SVEFPArithmetic_PredicatedFixed = 0x65008000,
3516 SVEFPArithmetic_PredicatedFMask = 0xFF30E000,
3517 SVEFPArithmetic_PredicatedMask = 0xFF3FE000,
3518 FADD_z_p_zz = SVEFPArithmetic_PredicatedFixed,
3519 FSUB_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00010000,
3520 FMUL_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00020000,
3521 FSUBR_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00030000,
3522 FMAXNM_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00040000,
3523 FMINNM_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00050000,
3524 FMAX_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00060000,
3525 FMIN_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00070000,
3526 FABD_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00080000,
3527 FSCALE_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00090000,
3528 FMULX_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000A0000,
3529 FDIVR_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000C0000,
3530 FDIV_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000D0000
3531 };
3532
3533 enum SVEFPCompareVectorsOp {
3534 SVEFPCompareVectorsFixed = 0x65004000,
3535 SVEFPCompareVectorsFMask = 0xFF204000,
3536 SVEFPCompareVectorsMask = 0xFF20E010,
3537 FCMGE_p_p_zz = SVEFPCompareVectorsFixed,
3538 FCMGT_p_p_zz = SVEFPCompareVectorsFixed | 0x00000010,
3539 FCMEQ_p_p_zz = SVEFPCompareVectorsFixed | 0x00002000,
3540 FCMNE_p_p_zz = SVEFPCompareVectorsFixed | 0x00002010,
3541 FCMUO_p_p_zz = SVEFPCompareVectorsFixed | 0x00008000,
3542 FACGE_p_p_zz = SVEFPCompareVectorsFixed | 0x00008010,
3543 FACGT_p_p_zz = SVEFPCompareVectorsFixed | 0x0000A010
3544 };
3545
3546 enum SVEFPCompareWithZeroOp {
3547 SVEFPCompareWithZeroFixed = 0x65102000,
3548 SVEFPCompareWithZeroFMask = 0xFF38E000,
3549 SVEFPCompareWithZeroMask = 0xFF3FE010,
3550 FCMGE_p_p_z0 = SVEFPCompareWithZeroFixed,
3551 FCMGT_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00000010,
3552 FCMLT_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00010000,
3553 FCMLE_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00010010,
3554 FCMEQ_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00020000,
3555 FCMNE_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00030000
3556 };
3557
3558 enum SVEFPComplexAdditionOp {
3559 SVEFPComplexAdditionFixed = 0x64008000,
3560 SVEFPComplexAdditionFMask = 0xFF3EE000,
3561 SVEFPComplexAdditionMask = 0xFF3EE000,
3562 FCADD_z_p_zz = SVEFPComplexAdditionFixed
3563 };
3564
3565 enum SVEFPComplexMulAddOp {
3566 SVEFPComplexMulAddFixed = 0x64000000,
3567 SVEFPComplexMulAddFMask = 0xFF208000,
3568 SVEFPComplexMulAddMask = 0xFF208000,
3569 FCMLA_z_p_zzz = SVEFPComplexMulAddFixed
3570 };
3571
3572 enum SVEFPComplexMulAddIndexOp {
3573 SVEFPComplexMulAddIndexFixed = 0x64201000,
3574 SVEFPComplexMulAddIndexFMask = 0xFF20F000,
3575 SVEFPComplexMulAddIndexMask = 0xFFE0F000,
3576 FCMLA_z_zzzi_h = SVEFPComplexMulAddIndexFixed | 0x00800000,
3577 FCMLA_z_zzzi_s = SVEFPComplexMulAddIndexFixed | 0x00C00000
3578 };
3579
3580 enum SVEFPConvertPrecisionOp {
3581 SVEFPConvertPrecisionFixed = 0x6508A000,
3582 SVEFPConvertPrecisionFMask = 0xFF3CE000,
3583 SVEFPConvertPrecisionMask = 0xFFFFE000,
3584 FCVT_z_p_z_s2h = SVEFPConvertPrecisionFixed | 0x00800000,
3585 FCVT_z_p_z_h2s = SVEFPConvertPrecisionFixed | 0x00810000,
3586 FCVT_z_p_z_d2h = SVEFPConvertPrecisionFixed | 0x00C00000,
3587 FCVT_z_p_z_h2d = SVEFPConvertPrecisionFixed | 0x00C10000,
3588 FCVT_z_p_z_d2s = SVEFPConvertPrecisionFixed | 0x00C20000,
3589 FCVT_z_p_z_s2d = SVEFPConvertPrecisionFixed | 0x00C30000
3590 };
3591
3592 enum SVEFPConvertToIntOp {
3593 SVEFPConvertToIntFixed = 0x6518A000,
3594 SVEFPConvertToIntFMask = 0xFF38E000,
3595 SVEFPConvertToIntMask = 0xFFFFE000,
3596 FCVTZS_z_p_z_fp162h = SVEFPConvertToIntFixed | 0x00420000,
3597 FCVTZU_z_p_z_fp162h = SVEFPConvertToIntFixed | 0x00430000,
3598 FCVTZS_z_p_z_fp162w = SVEFPConvertToIntFixed | 0x00440000,
3599 FCVTZU_z_p_z_fp162w = SVEFPConvertToIntFixed | 0x00450000,
3600 FCVTZS_z_p_z_fp162x = SVEFPConvertToIntFixed | 0x00460000,
3601 FCVTZU_z_p_z_fp162x = SVEFPConvertToIntFixed | 0x00470000,
3602 FCVTZS_z_p_z_s2w = SVEFPConvertToIntFixed | 0x00840000,
3603 FCVTZU_z_p_z_s2w = SVEFPConvertToIntFixed | 0x00850000,
3604 FCVTZS_z_p_z_d2w = SVEFPConvertToIntFixed | 0x00C00000,
3605 FCVTZU_z_p_z_d2w = SVEFPConvertToIntFixed | 0x00C10000,
3606 FCVTZS_z_p_z_s2x = SVEFPConvertToIntFixed | 0x00C40000,
3607 FCVTZU_z_p_z_s2x = SVEFPConvertToIntFixed | 0x00C50000,
3608 FCVTZS_z_p_z_d2x = SVEFPConvertToIntFixed | 0x00C60000,
3609 FCVTZU_z_p_z_d2x = SVEFPConvertToIntFixed | 0x00C70000
3610 };
3611
3612 enum SVEFPExponentialAcceleratorOp {
3613 SVEFPExponentialAcceleratorFixed = 0x0420B800,
3614 SVEFPExponentialAcceleratorFMask = 0xFF20FC00,
3615 SVEFPExponentialAcceleratorMask = 0xFF3FFC00,
3616 FEXPA_z_z = SVEFPExponentialAcceleratorFixed
3617 };
3618
3619 enum SVEFPFastReductionOp {
3620 SVEFPFastReductionFixed = 0x65002000,
3621 SVEFPFastReductionFMask = 0xFF38E000,
3622 SVEFPFastReductionMask = 0xFF3FE000,
3623 FADDV_v_p_z = SVEFPFastReductionFixed,
3624 FMAXNMV_v_p_z = SVEFPFastReductionFixed | 0x00040000,
3625 FMINNMV_v_p_z = SVEFPFastReductionFixed | 0x00050000,
3626 FMAXV_v_p_z = SVEFPFastReductionFixed | 0x00060000,
3627 FMINV_v_p_z = SVEFPFastReductionFixed | 0x00070000
3628 };
3629
3630 enum SVEFPMulAddOp {
3631 SVEFPMulAddFixed = 0x65200000,
3632 SVEFPMulAddFMask = 0xFF200000,
3633 SVEFPMulAddMask = 0xFF20E000,
3634 FMLA_z_p_zzz = SVEFPMulAddFixed,
3635 FMLS_z_p_zzz = SVEFPMulAddFixed | 0x00002000,
3636 FNMLA_z_p_zzz = SVEFPMulAddFixed | 0x00004000,
3637 FNMLS_z_p_zzz = SVEFPMulAddFixed | 0x00006000,
3638 FMAD_z_p_zzz = SVEFPMulAddFixed | 0x00008000,
3639 FMSB_z_p_zzz = SVEFPMulAddFixed | 0x0000A000,
3640 FNMAD_z_p_zzz = SVEFPMulAddFixed | 0x0000C000,
3641 FNMSB_z_p_zzz = SVEFPMulAddFixed | 0x0000E000
3642 };
3643
3644 enum SVEFPMulAddIndexOp {
3645 SVEFPMulAddIndexFixed = 0x64200000,
3646 SVEFPMulAddIndexFMask = 0xFF20F800,
3647 SVEFPMulAddIndexMask = 0xFFE0FC00,
3648 FMLA_z_zzzi_h = SVEFPMulAddIndexFixed,
3649 FMLA_z_zzzi_h_i3h = FMLA_z_zzzi_h | 0x00400000,
3650 FMLS_z_zzzi_h = SVEFPMulAddIndexFixed | 0x00000400,
3651 FMLS_z_zzzi_h_i3h = FMLS_z_zzzi_h | 0x00400000,
3652 FMLA_z_zzzi_s = SVEFPMulAddIndexFixed | 0x00800000,
3653 FMLS_z_zzzi_s = SVEFPMulAddIndexFixed | 0x00800400,
3654 FMLA_z_zzzi_d = SVEFPMulAddIndexFixed | 0x00C00000,
3655 FMLS_z_zzzi_d = SVEFPMulAddIndexFixed | 0x00C00400
3656 };
3657
3658 enum SVEFPMulIndexOp {
3659 SVEFPMulIndexFixed = 0x64202000,
3660 SVEFPMulIndexFMask = 0xFF20FC00,
3661 SVEFPMulIndexMask = 0xFFE0FC00,
3662 FMUL_z_zzi_h = SVEFPMulIndexFixed,
3663 FMUL_z_zzi_h_i3h = FMUL_z_zzi_h | 0x00400000,
3664 FMUL_z_zzi_s = SVEFPMulIndexFixed | 0x00800000,
3665 FMUL_z_zzi_d = SVEFPMulIndexFixed | 0x00C00000
3666 };
3667
3668 enum SVEFPRoundToIntegralValueOp {
3669 SVEFPRoundToIntegralValueFixed = 0x6500A000,
3670 SVEFPRoundToIntegralValueFMask = 0xFF38E000,
3671 SVEFPRoundToIntegralValueMask = 0xFF3FE000,
3672 FRINTN_z_p_z = SVEFPRoundToIntegralValueFixed,
3673 FRINTP_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00010000,
3674 FRINTM_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00020000,
3675 FRINTZ_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00030000,
3676 FRINTA_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00040000,
3677 FRINTX_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00060000,
3678 FRINTI_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00070000
3679 };
3680
3681 enum SVEFPTrigMulAddCoefficientOp {
3682 SVEFPTrigMulAddCoefficientFixed = 0x65108000,
3683 SVEFPTrigMulAddCoefficientFMask = 0xFF38FC00,
3684 SVEFPTrigMulAddCoefficientMask = 0xFF38FC00,
3685 FTMAD_z_zzi = SVEFPTrigMulAddCoefficientFixed
3686 };
3687
3688 enum SVEFPTrigSelectCoefficientOp {
3689 SVEFPTrigSelectCoefficientFixed = 0x0420B000,
3690 SVEFPTrigSelectCoefficientFMask = 0xFF20F800,
3691 SVEFPTrigSelectCoefficientMask = 0xFF20FC00,
3692 FTSSEL_z_zz = SVEFPTrigSelectCoefficientFixed
3693 };
3694
3695 enum SVEFPUnaryOpOp {
3696 SVEFPUnaryOpFixed = 0x650CA000,
3697 SVEFPUnaryOpFMask = 0xFF3CE000,
3698 SVEFPUnaryOpMask = 0xFF3FE000,
3699 FRECPX_z_p_z = SVEFPUnaryOpFixed,
3700 FSQRT_z_p_z = SVEFPUnaryOpFixed | 0x00010000
3701 };
3702
3703 enum SVEFPUnaryOpUnpredicatedOp {
3704 SVEFPUnaryOpUnpredicatedFixed = 0x65083000,
3705 SVEFPUnaryOpUnpredicatedFMask = 0xFF38F000,
3706 SVEFPUnaryOpUnpredicatedMask = 0xFF3FFC00,
3707 FRECPE_z_z = SVEFPUnaryOpUnpredicatedFixed | 0x00060000,
3708 FRSQRTE_z_z = SVEFPUnaryOpUnpredicatedFixed | 0x00070000
3709 };
3710
3711 enum SVEIncDecByPredicateCountOp {
3712 SVEIncDecByPredicateCountFixed = 0x25288000,
3713 SVEIncDecByPredicateCountFMask = 0xFF38F000,
3714 SVEIncDecByPredicateCountMask = 0xFF3FFE00,
3715 SQINCP_z_p_z = SVEIncDecByPredicateCountFixed,
3716 SQINCP_r_p_r_sx = SVEIncDecByPredicateCountFixed | 0x00000800,
3717 SQINCP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00000C00,
3718 UQINCP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00010000,
3719 UQINCP_r_p_r_uw = SVEIncDecByPredicateCountFixed | 0x00010800,
3720 UQINCP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00010C00,
3721 SQDECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00020000,
3722 SQDECP_r_p_r_sx = SVEIncDecByPredicateCountFixed | 0x00020800,
3723 SQDECP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00020C00,
3724 UQDECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00030000,
3725 UQDECP_r_p_r_uw = SVEIncDecByPredicateCountFixed | 0x00030800,
3726 UQDECP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00030C00,
3727 INCP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00040000,
3728 INCP_r_p_r = SVEIncDecByPredicateCountFixed | 0x00040800,
3729 DECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00050000,
3730 DECP_r_p_r = SVEIncDecByPredicateCountFixed | 0x00050800
3731 };
3732
3733 enum SVEIncDecRegisterByElementCountOp {
3734 SVEIncDecRegisterByElementCountFixed = 0x0430E000,
3735 SVEIncDecRegisterByElementCountFMask = 0xFF30F800,
3736 SVEIncDecRegisterByElementCountMask = 0xFFF0FC00,
3737 INCB_r_rs = SVEIncDecRegisterByElementCountFixed,
3738 DECB_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00000400,
3739 INCH_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00400000,
3740 DECH_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00400400,
3741 INCW_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00800000,
3742 DECW_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00800400,
3743 INCD_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00C00000,
3744 DECD_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00C00400
3745 };
3746
3747 enum SVEIncDecVectorByElementCountOp {
3748 SVEIncDecVectorByElementCountFixed = 0x0430C000,
3749 SVEIncDecVectorByElementCountFMask = 0xFF30F800,
3750 SVEIncDecVectorByElementCountMask = 0xFFF0FC00,
3751 INCH_z_zs = SVEIncDecVectorByElementCountFixed | 0x00400000,
3752 DECH_z_zs = SVEIncDecVectorByElementCountFixed | 0x00400400,
3753 INCW_z_zs = SVEIncDecVectorByElementCountFixed | 0x00800000,
3754 DECW_z_zs = SVEIncDecVectorByElementCountFixed | 0x00800400,
3755 INCD_z_zs = SVEIncDecVectorByElementCountFixed | 0x00C00000,
3756 DECD_z_zs = SVEIncDecVectorByElementCountFixed | 0x00C00400
3757 };
3758
3759 enum SVEIndexGenerationOp {
3760 SVEIndexGenerationFixed = 0x04204000,
3761 SVEIndexGenerationFMask = 0xFF20F000,
3762 SVEIndexGenerationMask = 0xFF20FC00,
3763 INDEX_z_ii = SVEIndexGenerationFixed,
3764 INDEX_z_ri = SVEIndexGenerationFixed | 0x00000400,
3765 INDEX_z_ir = SVEIndexGenerationFixed | 0x00000800,
3766 INDEX_z_rr = SVEIndexGenerationFixed | 0x00000C00
3767 };
3768
3769 enum SVEInsertGeneralRegisterOp {
3770 SVEInsertGeneralRegisterFixed = 0x05243800,
3771 SVEInsertGeneralRegisterFMask = 0xFF3FFC00,
3772 SVEInsertGeneralRegisterMask = 0xFF3FFC00,
3773 INSR_z_r = SVEInsertGeneralRegisterFixed
3774 };
3775
3776 enum SVEInsertSIMDFPScalarRegisterOp {
3777 SVEInsertSIMDFPScalarRegisterFixed = 0x05343800,
3778 SVEInsertSIMDFPScalarRegisterFMask = 0xFF3FFC00,
3779 SVEInsertSIMDFPScalarRegisterMask = 0xFF3FFC00,
3780 INSR_z_v = SVEInsertSIMDFPScalarRegisterFixed
3781 };
3782
3783 enum SVEIntAddSubtractImm_UnpredicatedOp {
3784 SVEIntAddSubtractImm_UnpredicatedFixed = 0x2520C000,
3785 SVEIntAddSubtractImm_UnpredicatedFMask = 0xFF38C000,
3786 SVEIntAddSubtractImm_UnpredicatedMask = 0xFF3FC000,
3787 ADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed,
3788 SUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00010000,
3789 SUBR_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00030000,
3790 SQADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00040000,
3791 UQADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00050000,
3792 SQSUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00060000,
3793 UQSUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00070000
3794 };
3795
3796 enum SVEIntAddSubtractVectors_PredicatedOp {
3797 SVEIntAddSubtractVectors_PredicatedFixed = 0x04000000,
3798 SVEIntAddSubtractVectors_PredicatedFMask = 0xFF38E000,
3799 SVEIntAddSubtractVectors_PredicatedMask = 0xFF3FE000,
3800 ADD_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed,
3801 SUB_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed | 0x00010000,
3802 SUBR_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed | 0x00030000
3803 };
3804
3805 enum SVEIntArithmeticUnpredicatedOp {
3806 SVEIntArithmeticUnpredicatedFixed = 0x04200000,
3807 SVEIntArithmeticUnpredicatedFMask = 0xFF20E000,
3808 SVEIntArithmeticUnpredicatedMask = 0xFF20FC00,
3809 ADD_z_zz = SVEIntArithmeticUnpredicatedFixed,
3810 SUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00000400,
3811 SQADD_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001000,
3812 UQADD_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001400,
3813 SQSUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001800,
3814 UQSUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001C00
3815 };
3816
3817 enum SVEIntCompareScalarCountAndLimitOp {
3818 SVEIntCompareScalarCountAndLimitFixed = 0x25200000,
3819 SVEIntCompareScalarCountAndLimitFMask = 0xFF20E000,
3820 SVEIntCompareScalarCountAndLimitMask = 0xFF20EC10,
3821 WHILELT_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000400,
3822 WHILELE_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000410,
3823 WHILELO_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000C00,
3824 WHILELS_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000C10
3825 };
3826
3827 enum SVEIntCompareSignedImmOp {
3828 SVEIntCompareSignedImmFixed = 0x25000000,
3829 SVEIntCompareSignedImmFMask = 0xFF204000,
3830 SVEIntCompareSignedImmMask = 0xFF20E010,
3831 CMPGE_p_p_zi = SVEIntCompareSignedImmFixed,
3832 CMPGT_p_p_zi = SVEIntCompareSignedImmFixed | 0x00000010,
3833 CMPLT_p_p_zi = SVEIntCompareSignedImmFixed | 0x00002000,
3834 CMPLE_p_p_zi = SVEIntCompareSignedImmFixed | 0x00002010,
3835 CMPEQ_p_p_zi = SVEIntCompareSignedImmFixed | 0x00008000,
3836 CMPNE_p_p_zi = SVEIntCompareSignedImmFixed | 0x00008010
3837 };
3838
3839 enum SVEIntCompareUnsignedImmOp {
3840 SVEIntCompareUnsignedImmFixed = 0x24200000,
3841 SVEIntCompareUnsignedImmFMask = 0xFF200000,
3842 SVEIntCompareUnsignedImmMask = 0xFF202010,
3843 CMPHS_p_p_zi = SVEIntCompareUnsignedImmFixed,
3844 CMPHI_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00000010,
3845 CMPLO_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00002000,
3846 CMPLS_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00002010
3847 };
3848
3849 enum SVEIntCompareVectorsOp {
3850 SVEIntCompareVectorsFixed = 0x24000000,
3851 SVEIntCompareVectorsFMask = 0xFF200000,
3852 SVEIntCompareVectorsMask = 0xFF20E010,
3853 CMPHS_p_p_zz = SVEIntCompareVectorsFixed,
3854 CMPHI_p_p_zz = SVEIntCompareVectorsFixed | 0x00000010,
3855 CMPEQ_p_p_zw = SVEIntCompareVectorsFixed | 0x00002000,
3856 CMPNE_p_p_zw = SVEIntCompareVectorsFixed | 0x00002010,
3857 CMPGE_p_p_zw = SVEIntCompareVectorsFixed | 0x00004000,
3858 CMPGT_p_p_zw = SVEIntCompareVectorsFixed | 0x00004010,
3859 CMPLT_p_p_zw = SVEIntCompareVectorsFixed | 0x00006000,
3860 CMPLE_p_p_zw = SVEIntCompareVectorsFixed | 0x00006010,
3861 CMPGE_p_p_zz = SVEIntCompareVectorsFixed | 0x00008000,
3862 CMPGT_p_p_zz = SVEIntCompareVectorsFixed | 0x00008010,
3863 CMPEQ_p_p_zz = SVEIntCompareVectorsFixed | 0x0000A000,
3864 CMPNE_p_p_zz = SVEIntCompareVectorsFixed | 0x0000A010,
3865 CMPHS_p_p_zw = SVEIntCompareVectorsFixed | 0x0000C000,
3866 CMPHI_p_p_zw = SVEIntCompareVectorsFixed | 0x0000C010,
3867 CMPLO_p_p_zw = SVEIntCompareVectorsFixed | 0x0000E000,
3868 CMPLS_p_p_zw = SVEIntCompareVectorsFixed | 0x0000E010
3869 };
3870
3871 enum SVEIntConvertToFPOp {
3872 SVEIntConvertToFPFixed = 0x6510A000,
3873 SVEIntConvertToFPFMask = 0xFF38E000,
3874 SVEIntConvertToFPMask = 0xFFFFE000,
3875 SCVTF_z_p_z_h2fp16 = SVEIntConvertToFPFixed | 0x00420000,
3876 UCVTF_z_p_z_h2fp16 = SVEIntConvertToFPFixed | 0x00430000,
3877 SCVTF_z_p_z_w2fp16 = SVEIntConvertToFPFixed | 0x00440000,
3878 UCVTF_z_p_z_w2fp16 = SVEIntConvertToFPFixed | 0x00450000,
3879 SCVTF_z_p_z_x2fp16 = SVEIntConvertToFPFixed | 0x00460000,
3880 UCVTF_z_p_z_x2fp16 = SVEIntConvertToFPFixed | 0x00470000,
3881 SCVTF_z_p_z_w2s = SVEIntConvertToFPFixed | 0x00840000,
3882 UCVTF_z_p_z_w2s = SVEIntConvertToFPFixed | 0x00850000,
3883 SCVTF_z_p_z_w2d = SVEIntConvertToFPFixed | 0x00C00000,
3884 UCVTF_z_p_z_w2d = SVEIntConvertToFPFixed | 0x00C10000,
3885 SCVTF_z_p_z_x2s = SVEIntConvertToFPFixed | 0x00C40000,
3886 UCVTF_z_p_z_x2s = SVEIntConvertToFPFixed | 0x00C50000,
3887 SCVTF_z_p_z_x2d = SVEIntConvertToFPFixed | 0x00C60000,
3888 UCVTF_z_p_z_x2d = SVEIntConvertToFPFixed | 0x00C70000
3889 };
3890
3891 enum SVEIntDivideVectors_PredicatedOp {
3892 SVEIntDivideVectors_PredicatedFixed = 0x04140000,
3893 SVEIntDivideVectors_PredicatedFMask = 0xFF3CE000,
3894 SVEIntDivideVectors_PredicatedMask = 0xFF3FE000,
3895 SDIV_z_p_zz = SVEIntDivideVectors_PredicatedFixed,
3896 UDIV_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00010000,
3897 SDIVR_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00020000,
3898 UDIVR_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00030000
3899 };
3900
3901 enum SVEIntMinMaxDifference_PredicatedOp {
3902 SVEIntMinMaxDifference_PredicatedFixed = 0x04080000,
3903 SVEIntMinMaxDifference_PredicatedFMask = 0xFF38E000,
3904 SVEIntMinMaxDifference_PredicatedMask = 0xFF3FE000,
3905 SMAX_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed,
3906 UMAX_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00010000,
3907 SMIN_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00020000,
3908 UMIN_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00030000,
3909 SABD_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00040000,
3910 UABD_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00050000
3911 };
3912
3913 enum SVEIntMinMaxImm_UnpredicatedOp {
3914 SVEIntMinMaxImm_UnpredicatedFixed = 0x2528C000,
3915 SVEIntMinMaxImm_UnpredicatedFMask = 0xFF38C000,
3916 SVEIntMinMaxImm_UnpredicatedMask = 0xFF3FE000,
3917 SMAX_z_zi = SVEIntMinMaxImm_UnpredicatedFixed,
3918 UMAX_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00010000,
3919 SMIN_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00020000,
3920 UMIN_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00030000
3921 };
3922
3923 enum SVEIntMulAddPredicatedOp {
3924 SVEIntMulAddPredicatedFixed = 0x04004000,
3925 SVEIntMulAddPredicatedFMask = 0xFF204000,
3926 SVEIntMulAddPredicatedMask = 0xFF20E000,
3927 MLA_z_p_zzz = SVEIntMulAddPredicatedFixed,
3928 MLS_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x00002000,
3929 MAD_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x00008000,
3930 MSB_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x0000A000
3931 };
3932
3933 enum SVEIntMulAddUnpredicatedOp {
3934 SVEIntMulAddUnpredicatedFixed = 0x44000000,
3935 SVEIntMulAddUnpredicatedFMask = 0xFF208000,
3936 SVEIntMulAddUnpredicatedMask = 0xFF20FC00,
3937 SDOT_z_zzz = SVEIntMulAddUnpredicatedFixed,
3938 UDOT_z_zzz = SVEIntMulAddUnpredicatedFixed | 0x00000400
3939 };
3940
3941 enum SVEIntMulImm_UnpredicatedOp {
3942 SVEIntMulImm_UnpredicatedFixed = 0x2530C000,
3943 SVEIntMulImm_UnpredicatedFMask = 0xFF38C000,
3944 SVEIntMulImm_UnpredicatedMask = 0xFF3FE000,
3945 MUL_z_zi = SVEIntMulImm_UnpredicatedFixed
3946 };
3947
3948 enum SVEIntMulVectors_PredicatedOp {
3949 SVEIntMulVectors_PredicatedFixed = 0x04100000,
3950 SVEIntMulVectors_PredicatedFMask = 0xFF3CE000,
3951 SVEIntMulVectors_PredicatedMask = 0xFF3FE000,
3952 MUL_z_p_zz = SVEIntMulVectors_PredicatedFixed,
3953 SMULH_z_p_zz = SVEIntMulVectors_PredicatedFixed | 0x00020000,
3954 UMULH_z_p_zz = SVEIntMulVectors_PredicatedFixed | 0x00030000
3955 };
3956
3957 enum SVEMovprfxOp {
3958 SVEMovprfxFixed = 0x04002000,
3959 SVEMovprfxFMask = 0xFF20E000,
3960 SVEMovprfxMask = 0xFF3EE000,
3961 MOVPRFX_z_p_z = SVEMovprfxFixed | 0x00100000
3962 };
3963
3964 enum SVEIntReductionOp {
3965 SVEIntReductionFixed = 0x04002000,
3966 SVEIntReductionFMask = 0xFF20E000,
3967 SVEIntReductionMask = 0xFF3FE000,
3968 SADDV_r_p_z = SVEIntReductionFixed,
3969 UADDV_r_p_z = SVEIntReductionFixed | 0x00010000,
3970 SMAXV_r_p_z = SVEIntReductionFixed | 0x00080000,
3971 UMAXV_r_p_z = SVEIntReductionFixed | 0x00090000,
3972 SMINV_r_p_z = SVEIntReductionFixed | 0x000A0000,
3973 UMINV_r_p_z = SVEIntReductionFixed | 0x000B0000
3974 };
3975
3976 enum SVEIntReductionLogicalOp {
3977 SVEIntReductionLogicalFixed = 0x04182000,
3978 SVEIntReductionLogicalFMask = 0xFF38E000,
3979 SVEIntReductionLogicalMask = 0xFF3FE000,
3980 ORV_r_p_z = SVEIntReductionLogicalFixed | 0x00180000,
3981 EORV_r_p_z = SVEIntReductionLogicalFixed | 0x00190000,
3982 ANDV_r_p_z = SVEIntReductionLogicalFixed | 0x001A0000
3983 };
3984
3985 enum SVEIntUnaryArithmeticPredicatedOp {
3986 SVEIntUnaryArithmeticPredicatedFixed = 0x0400A000,
3987 SVEIntUnaryArithmeticPredicatedFMask = 0xFF20E000,
3988 SVEIntUnaryArithmeticPredicatedMask = 0xFF3FE000,
3989 SXTB_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00100000,
3990 UXTB_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00110000,
3991 SXTH_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00120000,
3992 UXTH_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00130000,
3993 SXTW_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00140000,
3994 UXTW_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00150000,
3995 ABS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00160000,
3996 NEG_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00170000,
3997 CLS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00180000,
3998 CLZ_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00190000,
3999 CNT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001A0000,
4000 CNOT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001B0000,
4001 FABS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001C0000,
4002 FNEG_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001D0000,
4003 NOT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001E0000
4004 };
4005
4006 enum SVELoadAndBroadcastElementOp {
4007 SVELoadAndBroadcastElementFixed = 0x84408000,
4008 SVELoadAndBroadcastElementFMask = 0xFE408000,
4009 SVELoadAndBroadcastElementMask = 0xFFC0E000,
4010 LD1RB_z_p_bi_u8 = SVELoadAndBroadcastElementFixed,
4011 LD1RB_z_p_bi_u16 = SVELoadAndBroadcastElementFixed | 0x00002000,
4012 LD1RB_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x00004000,
4013 LD1RB_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x00006000,
4014 LD1RSW_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x00800000,
4015 LD1RH_z_p_bi_u16 = SVELoadAndBroadcastElementFixed | 0x00802000,
4016 LD1RH_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x00804000,
4017 LD1RH_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x00806000,
4018 LD1RSH_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x01000000,
4019 LD1RSH_z_p_bi_s32 = SVELoadAndBroadcastElementFixed | 0x01002000,
4020 LD1RW_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x01004000,
4021 LD1RW_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x01006000,
4022 LD1RSB_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x01800000,
4023 LD1RSB_z_p_bi_s32 = SVELoadAndBroadcastElementFixed | 0x01802000,
4024 LD1RSB_z_p_bi_s16 = SVELoadAndBroadcastElementFixed | 0x01804000,
4025 LD1RD_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x01806000
4026 };
4027
4028 enum SVELoadAndBroadcastQuadword_ScalarPlusImmOp {
4029 SVELoadAndBroadcastQuadword_ScalarPlusImmFixed = 0xA4002000,
4030 SVELoadAndBroadcastQuadword_ScalarPlusImmFMask = 0xFE10E000,
4031 SVELoadAndBroadcastQuadword_ScalarPlusImmMask = 0xFFF0E000,
4032 LD1RQB_z_p_bi_u8 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed,
4033 LD1RQH_z_p_bi_u16 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x00800000,
4034 LD1RQW_z_p_bi_u32 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x01000000,
4035 LD1RQD_z_p_bi_u64 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x01800000
4036 };
4037
4038 enum SVELoadAndBroadcastQuadword_ScalarPlusScalarOp {
4039 SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed = 0xA4000000,
4040 SVELoadAndBroadcastQuadword_ScalarPlusScalarFMask = 0xFE00E000,
4041 SVELoadAndBroadcastQuadword_ScalarPlusScalarMask = 0xFFE0E000,
4042 LD1RQB_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed,
4043 LD1RQH_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x00800000,
4044 LD1RQW_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x01000000,
4045 LD1RQD_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x01800000
4046 };
4047
4048 enum SVELoadMultipleStructures_ScalarPlusImmOp {
4049 SVELoadMultipleStructures_ScalarPlusImmFixed = 0xA400E000,
4050 SVELoadMultipleStructures_ScalarPlusImmFMask = 0xFE10E000,
4051 SVELoadMultipleStructures_ScalarPlusImmMask = 0xFFF0E000,
4052 LD2B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00200000,
4053 LD3B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00400000,
4054 LD4B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00600000,
4055 LD2H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00A00000,
4056 LD3H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00C00000,
4057 LD4H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00E00000,
4058 LD2W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01200000,
4059 LD3W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01400000,
4060 LD4W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01600000,
4061 LD2D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01A00000,
4062 LD3D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01C00000,
4063 LD4D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01E00000
4064 };
4065
4066 enum SVELoadMultipleStructures_ScalarPlusScalarOp {
4067 SVELoadMultipleStructures_ScalarPlusScalarFixed = 0xA400C000,
4068 SVELoadMultipleStructures_ScalarPlusScalarFMask = 0xFE00E000,
4069 SVELoadMultipleStructures_ScalarPlusScalarMask = 0xFFE0E000,
4070 LD2B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00200000,
4071 LD3B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00400000,
4072 LD4B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00600000,
4073 LD2H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00A00000,
4074 LD3H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00C00000,
4075 LD4H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00E00000,
4076 LD2W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01200000,
4077 LD3W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01400000,
4078 LD4W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01600000,
4079 LD2D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01A00000,
4080 LD3D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01C00000,
4081 LD4D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01E00000
4082 };
4083
4084 enum SVELoadPredicateRegisterOp {
4085 SVELoadPredicateRegisterFixed = 0x85800000,
4086 SVELoadPredicateRegisterFMask = 0xFFC0E010,
4087 SVELoadPredicateRegisterMask = 0xFFC0E010,
4088 LDR_p_bi = SVELoadPredicateRegisterFixed
4089 };
4090
4091 enum SVELoadVectorRegisterOp {
4092 SVELoadVectorRegisterFixed = 0x85804000,
4093 SVELoadVectorRegisterFMask = 0xFFC0E000,
4094 SVELoadVectorRegisterMask = 0xFFC0E000,
4095 LDR_z_bi = SVELoadVectorRegisterFixed
4096 };
4097
4098 enum SVEMulIndexOp {
4099 SVEMulIndexFixed = 0x44200000,
4100 SVEMulIndexFMask = 0xFF200000,
4101 SVEMulIndexMask = 0xFFE0FC00,
4102 SDOT_z_zzzi_s = SVEMulIndexFixed | 0x00800000,
4103 UDOT_z_zzzi_s = SVEMulIndexFixed | 0x00800400,
4104 SDOT_z_zzzi_d = SVEMulIndexFixed | 0x00C00000,
4105 UDOT_z_zzzi_d = SVEMulIndexFixed | 0x00C00400
4106 };
4107
4108 enum SVEPartitionBreakConditionOp {
4109 SVEPartitionBreakConditionFixed = 0x25104000,
4110 SVEPartitionBreakConditionFMask = 0xFF3FC200,
4111 SVEPartitionBreakConditionMask = 0xFFFFC200,
4112 BRKA_p_p_p = SVEPartitionBreakConditionFixed,
4113 BRKAS_p_p_p_z = SVEPartitionBreakConditionFixed | 0x00400000,
4114 BRKB_p_p_p = SVEPartitionBreakConditionFixed | 0x00800000,
4115 BRKBS_p_p_p_z = SVEPartitionBreakConditionFixed | 0x00C00000
4116 };
4117
4118 enum SVEPermutePredicateElementsOp {
4119 SVEPermutePredicateElementsFixed = 0x05204000,
4120 SVEPermutePredicateElementsFMask = 0xFF30E210,
4121 SVEPermutePredicateElementsMask = 0xFF30FE10,
4122 ZIP1_p_pp = SVEPermutePredicateElementsFixed,
4123 ZIP2_p_pp = SVEPermutePredicateElementsFixed | 0x00000400,
4124 UZP1_p_pp = SVEPermutePredicateElementsFixed | 0x00000800,
4125 UZP2_p_pp = SVEPermutePredicateElementsFixed | 0x00000C00,
4126 TRN1_p_pp = SVEPermutePredicateElementsFixed | 0x00001000,
4127 TRN2_p_pp = SVEPermutePredicateElementsFixed | 0x00001400
4128 };
4129
4130 enum SVEPermuteVectorExtractOp {
4131 SVEPermuteVectorExtractFixed = 0x05200000,
4132 SVEPermuteVectorExtractFMask = 0xFF20E000,
4133 SVEPermuteVectorExtractMask = 0xFFE0E000,
4134 EXT_z_zi_des = SVEPermuteVectorExtractFixed
4135 };
4136
4137 enum SVEPermuteVectorInterleavingOp {
4138 SVEPermuteVectorInterleavingFixed = 0x05206000,
4139 SVEPermuteVectorInterleavingFMask = 0xFF20E000,
4140 SVEPermuteVectorInterleavingMask = 0xFF20FC00,
4141 ZIP1_z_zz = SVEPermuteVectorInterleavingFixed,
4142 ZIP2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000400,
4143 UZP1_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000800,
4144 UZP2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000C00,
4145 TRN1_z_zz = SVEPermuteVectorInterleavingFixed | 0x00001000,
4146 TRN2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00001400
4147 };
4148
4149 enum SVEPredicateCountOp {
4150 SVEPredicateCountFixed = 0x25208000,
4151 SVEPredicateCountFMask = 0xFF38C000,
4152 SVEPredicateCountMask = 0xFF3FC200,
4153 CNTP_r_p_p = SVEPredicateCountFixed
4154 };
4155
4156 enum SVEPredicateFirstActiveOp {
4157 SVEPredicateFirstActiveFixed = 0x2518C000,
4158 SVEPredicateFirstActiveFMask = 0xFF3FFE10,
4159 SVEPredicateFirstActiveMask = 0xFFFFFE10,
4160 PFIRST_p_p_p = SVEPredicateFirstActiveFixed | 0x00400000
4161 };
4162
4163 enum SVEPredicateInitializeOp {
4164 SVEPredicateInitializeFixed = 0x2518E000,
4165 SVEPredicateInitializeFMask = 0xFF3EFC10,
4166 SVEPredicateInitializeMask = 0xFF3FFC10,
4167 SVEPredicateInitializeSetFlagsBit = 0x00010000,
4168 PTRUE_p_s = SVEPredicateInitializeFixed | 0x00000000,
4169 PTRUES_p_s = SVEPredicateInitializeFixed | SVEPredicateInitializeSetFlagsBit
4170 };
4171
4172 enum SVEPredicateLogicalOp {
4173 SVEPredicateLogicalFixed = 0x25004000,
4174 SVEPredicateLogicalFMask = 0xFF30C000,
4175 SVEPredicateLogicalMask = 0xFFF0C210,
4176 SVEPredicateLogicalSetFlagsBit = 0x00400000,
4177 AND_p_p_pp_z = SVEPredicateLogicalFixed,
4178 ANDS_p_p_pp_z = AND_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
4179 BIC_p_p_pp_z = SVEPredicateLogicalFixed | 0x00000010,
4180 BICS_p_p_pp_z = BIC_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
4181 EOR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00000200,
4182 EORS_p_p_pp_z = EOR_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
4183 ORR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800000,
4184 ORRS_p_p_pp_z = ORR_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
4185 ORN_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800010,
4186 ORNS_p_p_pp_z = ORN_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
4187 NAND_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800210,
4188 NANDS_p_p_pp_z = NAND_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
4189 NOR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800200,
4190 NORS_p_p_pp_z = NOR_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
4191 SEL_p_p_pp = SVEPredicateLogicalFixed | 0x00000210
4192 };
4193
4194 enum SVEPredicateNextActiveOp {
4195 SVEPredicateNextActiveFixed = 0x2519C400,
4196 SVEPredicateNextActiveFMask = 0xFF3FFE10,
4197 SVEPredicateNextActiveMask = 0xFF3FFE10,
4198 PNEXT_p_p_p = SVEPredicateNextActiveFixed
4199 };
4200
4201 enum SVEPredicateReadFromFFR_PredicatedOp {
4202 SVEPredicateReadFromFFR_PredicatedFixed = 0x2518F000,
4203 SVEPredicateReadFromFFR_PredicatedFMask = 0xFF3FFE10,
4204 SVEPredicateReadFromFFR_PredicatedMask = 0xFFFFFE10,
4205 RDFFR_p_p_f = SVEPredicateReadFromFFR_PredicatedFixed,
4206 RDFFRS_p_p_f = SVEPredicateReadFromFFR_PredicatedFixed | 0x00400000
4207 };
4208
4209 enum SVEPredicateReadFromFFR_UnpredicatedOp {
4210 SVEPredicateReadFromFFR_UnpredicatedFixed = 0x2519F000,
4211 SVEPredicateReadFromFFR_UnpredicatedFMask = 0xFF3FFFF0,
4212 SVEPredicateReadFromFFR_UnpredicatedMask = 0xFFFFFFF0,
4213 RDFFR_p_f = SVEPredicateReadFromFFR_UnpredicatedFixed
4214 };
4215
4216 enum SVEPredicateTestOp {
4217 SVEPredicateTestFixed = 0x2510C000,
4218 SVEPredicateTestFMask = 0xFF3FC210,
4219 SVEPredicateTestMask = 0xFFFFC21F,
4220 PTEST_p_p = SVEPredicateTestFixed | 0x00400000
4221 };
4222
4223 enum SVEPredicateZeroOp {
4224 SVEPredicateZeroFixed = 0x2518E400,
4225 SVEPredicateZeroFMask = 0xFF3FFFF0,
4226 SVEPredicateZeroMask = 0xFFFFFFF0,
4227 PFALSE_p = SVEPredicateZeroFixed
4228 };
4229
4230 enum SVEPropagateBreakOp {
4231 SVEPropagateBreakFixed = 0x2500C000,
4232 SVEPropagateBreakFMask = 0xFF30C000,
4233 SVEPropagateBreakMask = 0xFFF0C210,
4234 BRKPA_p_p_pp = SVEPropagateBreakFixed,
4235 BRKPB_p_p_pp = SVEPropagateBreakFixed | 0x00000010,
4236 BRKPAS_p_p_pp = SVEPropagateBreakFixed | 0x00400000,
4237 BRKPBS_p_p_pp = SVEPropagateBreakFixed | 0x00400010
4238 };
4239
4240 enum SVEPropagateBreakToNextPartitionOp {
4241 SVEPropagateBreakToNextPartitionFixed = 0x25184000,
4242 SVEPropagateBreakToNextPartitionFMask = 0xFFBFC210,
4243 SVEPropagateBreakToNextPartitionMask = 0xFFFFC210,
4244 BRKN_p_p_pp = SVEPropagateBreakToNextPartitionFixed,
4245 BRKNS_p_p_pp = SVEPropagateBreakToNextPartitionFixed | 0x00400000
4246 };
4247
4248 enum SVEReversePredicateElementsOp {
4249 SVEReversePredicateElementsFixed = 0x05344000,
4250 SVEReversePredicateElementsFMask = 0xFF3FFE10,
4251 SVEReversePredicateElementsMask = 0xFF3FFE10,
4252 REV_p_p = SVEReversePredicateElementsFixed
4253 };
4254
4255 enum SVEReverseVectorElementsOp {
4256 SVEReverseVectorElementsFixed = 0x05383800,
4257 SVEReverseVectorElementsFMask = 0xFF3FFC00,
4258 SVEReverseVectorElementsMask = 0xFF3FFC00,
4259 REV_z_z = SVEReverseVectorElementsFixed
4260 };
4261
4262 enum SVEReverseWithinElementsOp {
4263 SVEReverseWithinElementsFixed = 0x05248000,
4264 SVEReverseWithinElementsFMask = 0xFF3CE000,
4265 SVEReverseWithinElementsMask = 0xFF3FE000,
4266 REVB_z_z = SVEReverseWithinElementsFixed,
4267 REVH_z_z = SVEReverseWithinElementsFixed | 0x00010000,
4268 REVW_z_z = SVEReverseWithinElementsFixed | 0x00020000,
4269 RBIT_z_p_z = SVEReverseWithinElementsFixed | 0x00030000
4270 };
4271
4272 enum SVESaturatingIncDecRegisterByElementCountOp {
4273 SVESaturatingIncDecRegisterByElementCountFixed = 0x0420F000,
4274 SVESaturatingIncDecRegisterByElementCountFMask = 0xFF20F000,
4275 SVESaturatingIncDecRegisterByElementCountMask = 0xFFF0FC00,
4276 SQINCB_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed,
4277 UQINCB_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000400,
4278 SQDECB_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000800,
4279 UQDECB_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000C00,
4280 SQINCB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100000,
4281 UQINCB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100400,
4282 SQDECB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100800,
4283 UQDECB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100C00,
4284 SQINCH_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400000,
4285 UQINCH_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400400,
4286 SQDECH_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400800,
4287 UQDECH_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400C00,
4288 SQINCH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500000,
4289 UQINCH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500400,
4290 SQDECH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500800,
4291 UQDECH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500C00,
4292 SQINCW_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800000,
4293 UQINCW_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800400,
4294 SQDECW_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800800,
4295 UQDECW_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800C00,
4296 SQINCW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900000,
4297 UQINCW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900400,
4298 SQDECW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900800,
4299 UQDECW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900C00,
4300 SQINCD_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00000,
4301 UQINCD_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00400,
4302 SQDECD_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00800,
4303 UQDECD_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00C00,
4304 SQINCD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00000,
4305 UQINCD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00400,
4306 SQDECD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00800,
4307 UQDECD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00C00
4308 };
4309
4310 enum SVESaturatingIncDecVectorByElementCountOp {
4311 SVESaturatingIncDecVectorByElementCountFixed = 0x0420C000,
4312 SVESaturatingIncDecVectorByElementCountFMask = 0xFF30F000,
4313 SVESaturatingIncDecVectorByElementCountMask = 0xFFF0FC00,
4314 SQINCH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400000,
4315 UQINCH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400400,
4316 SQDECH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400800,
4317 UQDECH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400C00,
4318 SQINCW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800000,
4319 UQINCW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800400,
4320 SQDECW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800800,
4321 UQDECW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800C00,
4322 SQINCD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00000,
4323 UQINCD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00400,
4324 SQDECD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00800,
4325 UQDECD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00C00
4326 };
4327
4328 enum SVEStackFrameAdjustmentOp {
4329 SVEStackFrameAdjustmentFixed = 0x04205000,
4330 SVEStackFrameAdjustmentFMask = 0xFFA0F800,
4331 SVEStackFrameAdjustmentMask = 0xFFE0F800,
4332 ADDVL_r_ri = SVEStackFrameAdjustmentFixed,
4333 ADDPL_r_ri = SVEStackFrameAdjustmentFixed | 0x00400000
4334 };
4335
4336 enum SVEStackFrameSizeOp {
4337 SVEStackFrameSizeFixed = 0x04BF5000,
4338 SVEStackFrameSizeFMask = 0xFFFFF800,
4339 SVEStackFrameSizeMask = 0xFFFFF800,
4340 RDVL_r_i = SVEStackFrameSizeFixed
4341 };
4342
4343 enum SVEStoreMultipleStructures_ScalarPlusImmOp {
4344 SVEStoreMultipleStructures_ScalarPlusImmFixed = 0xE410E000,
4345 SVEStoreMultipleStructures_ScalarPlusImmFMask = 0xFE10E000,
4346 SVEStoreMultipleStructures_ScalarPlusImmMask = 0xFFF0E000,
4347 ST2B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00200000,
4348 ST3B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00400000,
4349 ST4B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00600000,
4350 ST2H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00A00000,
4351 ST3H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00C00000,
4352 ST4H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00E00000,
4353 ST2W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01200000,
4354 ST3W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01400000,
4355 ST4W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01600000,
4356 ST2D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01A00000,
4357 ST3D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01C00000,
4358 ST4D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01E00000
4359 };
4360
4361 enum SVEStoreMultipleStructures_ScalarPlusScalarOp {
4362 SVEStoreMultipleStructures_ScalarPlusScalarFixed = 0xE4006000,
4363 SVEStoreMultipleStructures_ScalarPlusScalarFMask = 0xFE00E000,
4364 SVEStoreMultipleStructures_ScalarPlusScalarMask = 0xFFE0E000,
4365 ST2B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00200000,
4366 ST3B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00400000,
4367 ST4B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00600000,
4368 ST2H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00A00000,
4369 ST3H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00C00000,
4370 ST4H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00E00000,
4371 ST2W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01200000,
4372 ST3W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01400000,
4373 ST4W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01600000,
4374 ST2D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01A00000,
4375 ST3D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01C00000,
4376 ST4D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01E00000
4377 };
4378
4379 enum SVEStorePredicateRegisterOp {
4380 SVEStorePredicateRegisterFixed = 0xE5800000,
4381 SVEStorePredicateRegisterFMask = 0xFFC0E010,
4382 SVEStorePredicateRegisterMask = 0xFFC0E010,
4383 STR_p_bi = SVEStorePredicateRegisterFixed
4384 };
4385
4386 enum SVEStoreVectorRegisterOp {
4387 SVEStoreVectorRegisterFixed = 0xE5804000,
4388 SVEStoreVectorRegisterFMask = 0xFFC0E000,
4389 SVEStoreVectorRegisterMask = 0xFFC0E000,
4390 STR_z_bi = SVEStoreVectorRegisterFixed
4391 };
4392
4393 enum SVETableLookupOp {
4394 SVETableLookupFixed = 0x05203000,
4395 SVETableLookupFMask = 0xFF20FC00,
4396 SVETableLookupMask = 0xFF20FC00,
4397 TBL_z_zz_1 = SVETableLookupFixed
4398 };
4399
4400 enum SVEUnpackPredicateElementsOp {
4401 SVEUnpackPredicateElementsFixed = 0x05304000,
4402 SVEUnpackPredicateElementsFMask = 0xFFFEFE10,
4403 SVEUnpackPredicateElementsMask = 0xFFFFFE10,
4404 PUNPKLO_p_p = SVEUnpackPredicateElementsFixed,
4405 PUNPKHI_p_p = SVEUnpackPredicateElementsFixed | 0x00010000
4406 };
4407
4408 enum SVEUnpackVectorElementsOp {
4409 SVEUnpackVectorElementsFixed = 0x05303800,
4410 SVEUnpackVectorElementsFMask = 0xFF3CFC00,
4411 SVEUnpackVectorElementsMask = 0xFF3FFC00,
4412 SUNPKLO_z_z = SVEUnpackVectorElementsFixed,
4413 SUNPKHI_z_z = SVEUnpackVectorElementsFixed | 0x00010000,
4414 UUNPKLO_z_z = SVEUnpackVectorElementsFixed | 0x00020000,
4415 UUNPKHI_z_z = SVEUnpackVectorElementsFixed | 0x00030000
4416 };
4417
4418 enum SVEVectorSelectOp {
4419 SVEVectorSelectFixed = 0x0520C000,
4420 SVEVectorSelectFMask = 0xFF20C000,
4421 SVEVectorSelectMask = 0xFF20C000,
4422 SEL_z_p_zz = SVEVectorSelectFixed
4423 };
4424
4425 enum SVEVectorSpliceOp {
4426 SVEVectorSpliceFixed = 0x052C8000,
4427 SVEVectorSpliceFMask = 0xFF3FE000,
4428 SVEVectorSpliceMask = 0xFF3FE000,
4429 SPLICE_z_p_zz_des = SVEVectorSpliceFixed
4430 };
4431
4432 enum ReservedOp {
4433 ReservedFixed = 0x00000000,
4434 ReservedFMask = 0x1E000000,
4435 ReservedMask = 0xFFFF0000,
4436 UDF = ReservedFixed | 0x00000000
4437 };
4438
4439 // Unimplemented and unallocated instructions. These are defined to make fixed
4440 // bit assertion easier.
4441 enum UnimplementedOp {
4442 UnimplementedFixed = 0x00000000,
4443 UnimplementedFMask = 0x00000000
4444 };
4445
4446 enum UnallocatedOp {
4447 UnallocatedFixed = 0x00000000,
4448 UnallocatedFMask = 0x00000000
4449 };
4450
4451 // Re-enable `clang-format` after the `enum`s.
4452 // clang-format on
4453
4454 } // namespace aarch64
4455 } // namespace vixl
4456
4457 #endif // VIXL_AARCH64_CONSTANTS_AARCH64_H_
4458