| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| D | SIOptimizeVGPRLiveRange.cpp | 508 Register UndefReg = MRI->createVirtualRegister(RC); in optimizeLiveRange() local
551 Register UndefReg = MRI->createVirtualRegister(RC); in optimizeWaterfallLiveRange() local
|
| D | R600OptimizeVectorRegisters.cpp | 53 std::vector<Register> UndefReg; member in __anon4c872a770111::RegSeqInfo
|
| D | SILowerI1Copies.cpp | 419 unsigned UndefReg = createLaneMaskReg(MF); in insertUndefLaneMask() local
|
| D | AMDGPUInstructionSelector.cpp | 2315 Register UndefReg = MRI->createVirtualRegister(SrcRC); in selectG_SZA_EXT() local
2397 Register UndefReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_SZA_EXT() local
|
| D | SIISelLowering.cpp | 11976 SDValue UndefReg = DAG.getRegister(MRI.createVirtualRegister(RC), VT); in PostISelFolding() local
|
| /external/llvm/lib/Target/X86/ |
| D | X86CallFrameOptimization.cpp | 495 unsigned UndefReg = MRI->createVirtualRegister(&X86::GR64RegClass); in adjustCallSequence() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86CallFrameOptimization.cpp | 542 Register UndefReg = MRI->createVirtualRegister(&X86::GR64RegClass); in adjustCallSequence() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| D | X86CallFrameOptimization.cpp | 543 Register UndefReg = MRI->createVirtualRegister(&X86::GR64RegClass); in adjustCallSequence() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | R600OptimizeVectorRegisters.cpp | 73 std::vector<unsigned> UndefReg; member in __anonbc4d5fb10111::RegSeqInfo
|
| D | SILowerI1Copies.cpp | 439 unsigned UndefReg = createLaneMaskReg(MF); in insertUndefLaneMask() local
|
| D | AMDGPUInstructionSelector.cpp | 1384 Register UndefReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_SZA_EXT() local
|
| D | SIISelLowering.cpp | 10379 SDValue UndefReg = DAG.getRegister(MRI.createVirtualRegister(RC), VT); in PostISelFolding() local
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | R600OptimizeVectorRegisters.cpp | 67 std::vector<unsigned> UndefReg; member in __anonbf372acf0111::RegSeqInfo
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CombinerHelper.cpp | 260 Register UndefReg; in matchCombineShuffleVector() local
|
| D | LegalizerHelper.cpp | 1270 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in widenScalarMergeValues() local
2854 Register UndefReg; in fewerElementsVectorBuildVector() local
|
| /external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CombinerHelper.cpp | 366 Register UndefReg; in matchCombineShuffleVector() local
2689 Register UndefReg; in applyCombineInsertVecElts() local
|
| D | LegalizerHelper.cpp | 1596 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); in widenScalarMergeValues() local
|