1 /* 2 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef V2M_DEF_H 7 #define V2M_DEF_H 8 9 #include <lib/utils_def.h> 10 11 /* Base address of all V2M */ 12 #ifdef PLAT_V2M_OFFSET 13 #define V2M_OFFSET PLAT_V2M_OFFSET 14 #else 15 #define V2M_OFFSET UL(0) 16 #endif 17 18 /* V2M motherboard system registers & offsets */ 19 #define V2M_SYSREGS_BASE UL(0x1c010000) 20 #define V2M_SYSREGS_SIZE UL(0x00010000) 21 #define V2M_SYS_ID UL(0x0) 22 #define V2M_SYS_SWITCH UL(0x4) 23 #define V2M_SYS_LED UL(0x8) 24 #define V2M_SYS_NVFLAGS UL(0x38) 25 #define V2M_SYS_NVFLAGSSET UL(0x38) 26 #define V2M_SYS_NVFLAGSCLR UL(0x3c) 27 #define V2M_SYS_CFGDATA UL(0xa0) 28 #define V2M_SYS_CFGCTRL UL(0xa4) 29 #define V2M_SYS_CFGSTATUS UL(0xa8) 30 31 #define V2M_CFGCTRL_START BIT_32(31) 32 #define V2M_CFGCTRL_RW BIT_32(30) 33 #define V2M_CFGCTRL_FUNC_SHIFT 20 34 #define V2M_CFGCTRL_FUNC(fn) ((fn) << V2M_CFGCTRL_FUNC_SHIFT) 35 #define V2M_FUNC_CLK_GEN U(0x01) 36 #define V2M_FUNC_TEMP U(0x04) 37 #define V2M_FUNC_DB_RESET U(0x05) 38 #define V2M_FUNC_SCC_CFG U(0x06) 39 #define V2M_FUNC_SHUTDOWN U(0x08) 40 #define V2M_FUNC_REBOOT U(0x09) 41 42 /* NVFLAGS in the V2M motherboard which is preserved after a watchdog reset */ 43 #define V2M_SYS_NVFLAGS_ADDR (V2M_SYSREGS_BASE + V2M_SYS_NVFLAGS) 44 45 /* 46 * V2M sysled bit definitions. The values written to this 47 * register are defined in arch.h & runtime_svc.h. Only 48 * used by the primary cpu to diagnose any cold boot issues. 49 * 50 * SYS_LED[0] - Security state (S=0/NS=1) 51 * SYS_LED[2:1] - Exception Level (EL3-EL0) 52 * SYS_LED[7:3] - Exception Class (Sync/Async & origin) 53 * 54 */ 55 #define V2M_SYS_LED_SS_SHIFT 0x0 56 #define V2M_SYS_LED_EL_SHIFT 0x1 57 #define V2M_SYS_LED_EC_SHIFT 0x3 58 59 #define V2M_SYS_LED_SS_MASK U(0x1) 60 #define V2M_SYS_LED_EL_MASK U(0x3) 61 #define V2M_SYS_LED_EC_MASK U(0x1f) 62 63 /* V2M sysid register bits */ 64 #define V2M_SYS_ID_REV_SHIFT 28 65 #define V2M_SYS_ID_HBI_SHIFT 16 66 #define V2M_SYS_ID_BLD_SHIFT 12 67 #define V2M_SYS_ID_ARCH_SHIFT 8 68 #define V2M_SYS_ID_FPGA_SHIFT 0 69 70 #define V2M_SYS_ID_REV_MASK U(0xf) 71 #define V2M_SYS_ID_HBI_MASK U(0xfff) 72 #define V2M_SYS_ID_BLD_MASK U(0xf) 73 #define V2M_SYS_ID_ARCH_MASK U(0xf) 74 #define V2M_SYS_ID_FPGA_MASK U(0xff) 75 76 #define V2M_SYS_ID_BLD_LENGTH 4 77 78 79 /* NOR Flash */ 80 #define V2M_FLASH0_BASE (V2M_OFFSET + UL(0x08000000)) 81 #define V2M_FLASH0_SIZE UL(0x04000000) 82 #define V2M_FLASH1_BASE (V2M_OFFSET + UL(0x0c000000)) 83 #define V2M_FLASH1_SIZE UL(0x04000000) 84 #define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */ 85 86 #define V2M_IOFPGA_BASE (V2M_OFFSET + UL(0x1c000000)) 87 #define V2M_IOFPGA_SIZE UL(0x03000000) 88 89 /* PL011 UART related constants */ 90 #define V2M_IOFPGA_UART0_BASE (V2M_OFFSET + UL(0x1c090000)) 91 #define V2M_IOFPGA_UART1_BASE (V2M_OFFSET + UL(0x1c0a0000)) 92 #define V2M_IOFPGA_UART2_BASE (V2M_OFFSET + UL(0x1c0b0000)) 93 #define V2M_IOFPGA_UART3_BASE (V2M_OFFSET + UL(0x1c0c0000)) 94 95 #define V2M_IOFPGA_UART0_CLK_IN_HZ 24000000 96 #define V2M_IOFPGA_UART1_CLK_IN_HZ 24000000 97 #define V2M_IOFPGA_UART2_CLK_IN_HZ 24000000 98 #define V2M_IOFPGA_UART3_CLK_IN_HZ 24000000 99 100 /* SP804 timer related constants */ 101 #define V2M_SP804_TIMER0_BASE (V2M_OFFSET + UL(0x1C110000)) 102 #define V2M_SP804_TIMER1_BASE (V2M_OFFSET + UL(0x1C120000)) 103 104 /* SP810 controller */ 105 #define V2M_SP810_BASE (V2M_OFFSET + UL(0x1c020000)) 106 #define V2M_SP810_CTRL_TIM0_SEL BIT_32(15) 107 #define V2M_SP810_CTRL_TIM1_SEL BIT_32(17) 108 #define V2M_SP810_CTRL_TIM2_SEL BIT_32(19) 109 #define V2M_SP810_CTRL_TIM3_SEL BIT_32(21) 110 111 /* 112 * The flash can be mapped either as read-only or read-write. 113 * 114 * If it is read-write then it should also be mapped as device memory because 115 * NOR flash programming involves sending a fixed, ordered sequence of commands. 116 * 117 * If it is read-only then it should also be mapped as: 118 * - Normal memory, because reading from NOR flash is transparent, it is like 119 * reading from RAM. 120 * - Non-executable by default. If some parts of the flash need to be executable 121 * then platform code is responsible for re-mapping the appropriate portion 122 * of it as executable. 123 */ 124 #define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 125 V2M_FLASH0_SIZE, \ 126 MT_DEVICE | MT_RW | MT_SECURE) 127 128 #define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 129 V2M_FLASH0_SIZE, \ 130 MT_RO_DATA | MT_SECURE) 131 132 #define V2M_MAP_FLASH1_RW MAP_REGION_FLAT(V2M_FLASH1_BASE,\ 133 V2M_FLASH1_SIZE, \ 134 MT_DEVICE | MT_RW | MT_SECURE) 135 136 #define V2M_MAP_FLASH1_RO MAP_REGION_FLAT(V2M_FLASH1_BASE,\ 137 V2M_FLASH1_SIZE, \ 138 MT_RO_DATA | MT_SECURE) 139 140 #define V2M_MAP_IOFPGA MAP_REGION_FLAT(V2M_IOFPGA_BASE,\ 141 V2M_IOFPGA_SIZE, \ 142 MT_DEVICE | MT_RW | MT_SECURE) 143 144 /* Region equivalent to V2M_MAP_IOFPGA suitable for mapping at EL0 */ 145 #define V2M_MAP_IOFPGA_EL0 MAP_REGION_FLAT( \ 146 V2M_IOFPGA_BASE, \ 147 V2M_IOFPGA_SIZE, \ 148 MT_DEVICE | MT_RW | MT_SECURE | MT_USER) 149 150 #define V2M_MAP_SECURE_SYSTEMREG_EL0 MAP_REGION_FLAT( \ 151 V2M_SYSREGS_BASE, \ 152 V2M_SYSREGS_SIZE, \ 153 MT_DEVICE | MT_RW | MT_SECURE | MT_USER) 154 155 #define V2M_MAP_FLASH0_RW_EL0 MAP_REGION_FLAT( \ 156 V2M_FLASH0_BASE, \ 157 V2M_FLASH0_SIZE, \ 158 MT_DEVICE | MT_RW | MT_SECURE | MT_USER) 159 160 #define V2M_MAP_FLASH1_RW_EL0 MAP_REGION_FLAT( \ 161 V2M_FLASH1_BASE, \ 162 V2M_FLASH1_SIZE, \ 163 MT_DEVICE | MT_RW | MT_SECURE | MT_USER) 164 165 #endif /* V2M_DEF_H */ 166