1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 3 #ifndef MT8195_H 4 #define MT8195_H 5 6 /*=======================================================================*/ 7 /* Constant Definitions */ 8 /*=======================================================================*/ 9 10 #define IO_PHYS (0x10000000) 11 #define IO_SIZE (0x02000000) 12 13 #define VER_BASE (0x08000000) 14 15 /*=======================================================================*/ 16 /* Register Bases */ 17 /*=======================================================================*/ 18 #define MCUCFG_BASE (0x0C530000) 19 #define TOPCKGEN_BASE (IO_PHYS) 20 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 21 #define APMIXED_BASE (IO_PHYS + 0x0000C000) 22 #define INFRA_AO_BCRM_BASE (IO_PHYS + 0x00022000) 23 #define AUDIO_BASE (IO_PHYS + 0x00890000) 24 #define AUDIO_SRC_BASE (IO_PHYS + 0x008a0000) 25 #define CAMSYS_YUVB_BASE (IO_PHYS + 0x060af000) 26 #define CAMSYS_MAIN_BASE (IO_PHYS + 0x06000000) 27 #define CAMSYS_MRAW_BASE (IO_PHYS + 0x06140000) 28 #define CAMSYS_RAWA_BASE (IO_PHYS + 0x0604f000) 29 #define CAMSYS_RAWB_BASE (IO_PHYS + 0x0608f000) 30 #define CAMSYS_YUVA_BASE (IO_PHYS + 0x0606f000) 31 #define CCU_MAIN_BASE (IO_PHYS + 0x07200000) 32 #define IMGSYS1_DIP_NR_BASE (IO_PHYS + 0x05130000) 33 #define IMGSYS1_DIP_TOP_BASE (IO_PHYS + 0x05110000) 34 #define IMGSYS1_WPE_BASE (IO_PHYS + 0x05220000) 35 #define IMGSYS_MAIN_BASE (IO_PHYS + 0x05000000) 36 #define IPESYS_BASE (IO_PHYS + 0x05330000) 37 #define MFGCFG_BASE (IO_PHYS + 0x03fbf000) 38 #define PERICFG_AO_BASE (IO_PHYS + 0x01003000) 39 #define SCP_PAR_TOP_BASE (IO_PHYS + 0x00720000) 40 #define IPNNA_BASE (IO_PHYS + 0x00211000) 41 #define VDEC_CORE1_GCON_BASE (IO_PHYS + 0x0803f000) 42 #define VDEC_GCON_BASE (IO_PHYS + 0x0802f000) 43 #define VDEC_SOC_GCON_BASE (IO_PHYS + 0x0800f000) 44 #define VDOSYS0_CONFIG_BASE (IO_PHYS + 0x0c01a000) 45 #define VDOSYS1_CONFIG_BASE (IO_PHYS + 0x0c100000) 46 #define VENC_CORE1_GCON_BASE (IO_PHYS + 0x0b000000) 47 #define VENC_GCON_BASE (IO_PHYS + 0x0a000000) 48 #define VPP0_REG_BASE (IO_PHYS + 0x04000000) 49 #define VPPSYS1_CONFIG_BASE (IO_PHYS + 0x04f00000) 50 #define WPESYS_TOP_REG_BASE (IO_PHYS + 0x04e00000) 51 #define WPE_VPP0_BASE (IO_PHYS + 0x04e02000) 52 #define WPE_VPP1_BASE (IO_PHYS + 0x04e03000) 53 54 #define IOCFG_BM_BASE (0x11D10000) 55 #define IOCFG_BL_BASE (0x11D30000) 56 #define IOCFG_BR_BASE (0x11D40000) 57 #define IOCFG_LM_BASE (0x11E20000) 58 #define IOCFG_RB_BASE (0x11EB0000) 59 #define IOCFG_TL_BASE (0x11F40000) 60 61 /*should be removed*/ 62 #define PERICFG_BASE (IO_PHYS + 0x00003000) 63 64 //#define PERI_CON_BASE (IO_PHYS + 0x00003000) 65 66 #define GPIO_BASE (IO_PHYS + 0x00005000) 67 #define SPM_BASE (IO_PHYS + 0x00006000) 68 #define RGU_BASE (IO_PHYS + 0x00007000) 69 #define GPT_BASE (IO_PHYS + 0x00008000) 70 #define SYSTIMER_BASE (IO_PHYS + 0x00017000) 71 #define TIA_BASE (IO_PHYS + 0x0001C000) 72 #define PMIF_SPI_BASE (IO_PHYS + 0x00024000) 73 #define PMICSPI_MST_BASE (IO_PHYS + 0x00025000) 74 #define PMIF_SPMI_BASE (IO_PHYS + 0x00027000) 75 #define SPMI_MST_BASE (IO_PHYS + 0x00029000) 76 #define DDRPHY_BASE (IO_PHYS + 0x00330000) 77 #define KPD_BASE (IO_PHYS + 0x00010000) 78 79 #define DEM_BASE (0x0D0A0000) 80 81 #define MCUSYS_CFGREG_BASE (0x0C530000) 82 //#define CA7MCUCFG_BASE (IO_PHYS + 0x00200100) 83 //#define CA15L_CONFIG_BASE (IO_PHYS + 0x00200200) 84 #define SRAMROM_BASE (IO_PHYS + 0x00214000) 85 #define GICD_BASE (0x0c000000) 86 #define GICR_BASE (0x0c040000) 87 88 #define AUXADC_BASE (IO_PHYS + 0X01002000) 89 #define DEVINFO_BASE (IO_PHYS + 0x01C10000) 90 #define UART0_BASE (IO_PHYS + 0x01001100) 91 #define UART1_BASE (IO_PHYS + 0x01001200) 92 #define UART2_BASE (IO_PHYS + 0x01001300) 93 #define UART3_BASE (IO_PHYS + 0x01001400) 94 #define SPI_BASE (IO_PHYS + 0x010F0000) 95 #define NFI_BASE (IO_PHYS + 0x0100D000) /* FIXME: not list in memory map */ 96 #define NFIECC_BASE (IO_PHYS + 0x0100E000) /* FIXME: not list in memory map */ 97 #define MSDC0_TOP_BASE (IO_PHYS + 0x01F50000) 98 #define MSDC1_TOP_BASE (IO_PHYS + 0x01E10000) 99 #define MSDC0_BASE (IO_PHYS + 0x01230000) 100 #define MSDC1_BASE (IO_PHYS + 0x01240000) 101 #define MSDC2_BASE (IO_PHYS + 0x01250000) 102 #define MSDC3_BASE (IO_PHYS + 0x01260000) /* Reserved in Sylvia */ 103 #define U3D_BASE (IO_PHYS + 0x01200000) /* MAC: 0x1120_0000 */ 104 #define USB_SIF_BASE (IO_PHYS + 0x01E40000) /* PHY: 0x11E4_0000 */ 105 #define USB1P_SIF_BASE (IO_PHYS + 0x01C40000) 106 #define PCIE_BASE (IO_PHYS + 0x093F0000) 107 #define PCIE_PHY_BASE (IO_PHYS + 0x01E20000) 108 109 #define CPUXGPT_BASE (IO_PHYS + 0x00200000) 110 111 #define SUB_INFRACFG_AO_BASE (IO_PHYS + 0x0030E000) 112 113 /*=======================================================================*/ 114 /* AP HW code offset */ 115 /*=======================================================================*/ 116 #define APHW_CODE (VER_BASE) 117 #define APHW_SUBCODE (VER_BASE + 0x04) 118 #define APHW_VER (VER_BASE + 0x08) 119 #define APSW_VER (VER_BASE + 0x0C) 120 121 // #define AMCONFG_BASE (0xFFFFFFFF) 122 123 /*=======================================================================*/ 124 /* USB register offset */ 125 /*=======================================================================*/ 126 #define SSUSB_DEV_BASE (U3D_BASE + 0x1000) /* FIXME: not list in memory map */ 127 #define SSUSB_EPCTL_CSR_BASE (U3D_BASE + 0x1800) /* FIXME: not list in memory map */ 128 #define SSUSB_USB3_MAC_CSR_BASE (U3D_BASE + 0x2400) /* FIXME: not list in memory map */ 129 #define SSUSB_USB3_SYS_CSR_BASE (U3D_BASE + 0x2400) /* FIXME: not list in memory map */ 130 #define SSUSB_USB2_CSR_BASE (U3D_BASE + 0x3400) /* FIXME: not list in memory map */ 131 132 #define SSUSB_SIFSLV_IPPC_BASE (U3D_BASE + 0x3E00) /* FIXME: not list in memory map */ 133 134 #define SSUSB_SIFSLV_SPLLC_BASE (USB_SIF_BASE + 0x700) /* FIXME: not list in memory map */ 135 #define SSUSB_SIFSLV_U2PHY_COM_BASE (USB_SIF_BASE + 0x300) /* FIXME: not list in memory map */ 136 #define SSUSB_SIFSLV_U3PHYD_BASE (USB_SIF_BASE + 0x900) /* FIXME: not list in memory map */ 137 #define SSUSB_SIFSLV_U2PHY_COM_SIV_B_BASE (USB_SIF_BASE + 0x300) /* FIXME: not list in memory map */ 138 #define SSUSB_USB30_PHYA_SIV_B2_BASE (USB_SIF_BASE + 0xA00) /* FIXME: not list in memory map */ 139 #define SSUSB_USB30_PHYA_SIV_B_BASE (USB_SIF_BASE + 0xB00) /* FIXME: not list in memory map */ 140 #define SSUSB_SIFSLV_U3PHYA_DA_BASE (USB_SIF_BASE + 0xC00) /* FIXME: not list in memory map */ 141 142 143 /*=======================================================================*/ 144 /* USB download control */ 145 /*=======================================================================*/ 146 #define SECURITY_AO (0x1001A000) 147 #define BOOT_MISC0 (SECURITY_AO + 0x0080) 148 #define MISC_LOCK_KEY (SECURITY_AO + 0x0100) 149 #define RST_CON (SECURITY_AO + 0x0108) 150 151 #define MISC_LOCK_KEY_MAGIC 0xAD98 152 #define USBDL_FLAG BOOT_MISC0 153 154 155 #define USBDL_BIT_EN (0x00000001) /* 1: download bit enabled */ 156 #define USBDL_BROM (0x00000002) /* 0: usbdl by brom; 1: usbdl by bootloader */ 157 #define USBDL_TIMEOUT_MASK (0x0000FFFC) /* 14-bit timeout: 0x0000~0x3FFE: second; 0x3FFFF: no timeout */ 158 #define USBDL_TIMEOUT_MAX (USBDL_TIMEOUT_MASK >> 2) /* maximum timeout indicates no timeout */ 159 #define USBDL_MAGIC (0x444C0000) /* Brom will check this magic number */ 160 161 162 #define SRAMROM_USBDL_TO_DIS (SRAMROM_BASE + 0x0054) 163 #define USBDL_TO_DIS (0x00000001) 164 165 /*=======================================================================*/ 166 /* NAND Control */ 167 /*=======================================================================*/ 168 #define NAND_PAGE_SIZE (2048) // (Bytes) 169 #define NAND_BLOCK_BLKS (64) // 64 nand pages = 128KB 170 #define NAND_PAGE_SHIFT (9) 171 #define NAND_LARGE_PAGE (11) // large page 172 #define NAND_SMALL_PAGE (9) // small page 173 #define NAND_BUS_WIDTH_8 (8) 174 #define NAND_BUS_WIDTH_16 (16) 175 #define NAND_FDM_SIZE (8) 176 #define NAND_ECC_SW (0) 177 #define NAND_ECC_HW (1) 178 179 #define NFI_MAX_FDM_SIZE (8) 180 #define NFI_MAX_FDM_SEC_NUM (8) 181 #define NFI_MAX_LOCK_CHANNEL (16) 182 183 #define ECC_MAX_CORRECTABLE_BITS (12) 184 #define ECC_MAX_PARITY_SIZE (20) /* in bytes */ 185 186 #define ECC_ERR_LOCATION_MASK (0x1FFF) 187 #define ECC_ERR_LOCATION_SHIFT (16) 188 189 #define NAND_FFBUF_SIZE (2048 + 64) 190 191 /*=======================================================================*/ 192 /* SW Reset Vector */ 193 /*=======================================================================*/ 194 /* setup the reset vector base address after warm reset to Aarch64 */ 195 #define RVBADDRESS_CPU0 (MCUSYS_CFGREG_BASE + 0xC900) 196 197 /* IRQ */ 198 #define SYS_TIMER_IRQ (233 + 32) 199 #define GZ_SW_IRQ (513 + 32) 200 201 #endif 202