1 /* 2 * Copyright (c) 2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2021-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef VERSAL_NET_DEF_H 10 #define VERSAL_NET_DEF_H 11 12 #include <plat/arm/common/smccc_def.h> 13 #include <plat/common/common_def.h> 14 15 #define MAX_INTR_EL3 2 16 17 /* List all consoles */ 18 #define VERSAL_NET_CONSOLE_ID_none U(0) 19 #define VERSAL_NET_CONSOLE_ID_pl011 U(1) 20 #define VERSAL_NET_CONSOLE_ID_pl011_0 U(1) 21 #define VERSAL_NET_CONSOLE_ID_pl011_1 U(2) 22 #define VERSAL_NET_CONSOLE_ID_dcc U(3) 23 #define VERSAL_NET_CONSOLE_ID_dtb U(4) 24 25 #define CONSOLE_IS(con) (VERSAL_NET_CONSOLE_ID_ ## con == VERSAL_NET_CONSOLE) 26 27 /* Runtime console */ 28 #define RT_CONSOLE_ID_pl011 1 29 #define RT_CONSOLE_ID_pl011_0 1 30 #define RT_CONSOLE_ID_pl011_1 2 31 #define RT_CONSOLE_ID_dcc 3 32 #define RT_CONSOLE_ID_dtb 4 33 34 #define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME) 35 36 /* List all platforms */ 37 #define VERSAL_NET_SILICON U(0) 38 #define VERSAL_NET_SPP U(1) 39 #define VERSAL_NET_EMU U(2) 40 #define VERSAL_NET_QEMU U(3) 41 #define VERSAL_NET_QEMU_COSIM U(7) 42 43 /* For platform detection */ 44 #define PMC_TAP U(0xF11A0000) 45 #define PMC_TAP_VERSION (PMC_TAP + 0x4U) 46 # define PLATFORM_MASK GENMASK(27U, 24U) 47 # define PLATFORM_VERSION_MASK GENMASK(31U, 28U) 48 49 /* Global timer reset */ 50 #define PSX_CRF U(0xEC200000) 51 #define ACPU0_CLK_CTRL U(0x10C) 52 #define ACPU_CLK_CTRL_CLKACT BIT(25) 53 54 #define RST_APU0_OFFSET U(0x300) 55 #define RST_APU_COLD_RESET BIT(0) 56 #define RST_APU_WARN_RESET BIT(4) 57 #define RST_APU_CLUSTER_COLD_RESET BIT(8) 58 #define RST_APU_CLUSTER_WARM_RESET BIT(9) 59 60 #define PSX_CRF_RST_TIMESTAMP_OFFSET U(0x33C) 61 62 #define APU_PCLI (0xECB10000ULL) 63 #define APU_PCLI_CPU_STEP (0x30ULL) 64 #define APU_PCLI_CLUSTER_CPU_STEP (4ULL * APU_PCLI_CPU_STEP) 65 #define APU_PCLI_CLUSTER_OFFSET U(0x8000) 66 #define APU_PCLI_CLUSTER_STEP U(0x1000) 67 #define PCLI_PREQ_OFFSET U(0x4) 68 #define PREQ_CHANGE_REQUEST BIT(0) 69 #define PCLI_PSTATE_OFFSET U(0x8) 70 #define PCLI_PSTATE_VAL_SET U(0x48) 71 #define PCLI_PSTATE_VAL_CLEAR U(0x38) 72 73 /* Firmware Image Package */ 74 #define VERSAL_NET_PRIMARY_CPU U(0) 75 76 #define CORE_0_ISR_WAKE_OFFSET (0x00000020ULL) 77 #define APU_PCIL_CORE_X_ISR_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_WAKE_OFFSET + \ 78 (APU_PCLI_CPU_STEP * (cpu_id)))) 79 #define APU_PCIL_CORE_X_ISR_WAKE_MASK (0x00000001U) 80 #define CORE_0_IEN_WAKE_OFFSET (0x00000028ULL) 81 #define APU_PCIL_CORE_X_IEN_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_WAKE_OFFSET + \ 82 (APU_PCLI_CPU_STEP * (cpu_id)))) 83 #define APU_PCIL_CORE_X_IEN_WAKE_MASK (0x00000001U) 84 #define CORE_0_IDS_WAKE_OFFSET (0x0000002CULL) 85 #define APU_PCIL_CORE_X_IDS_WAKE_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_WAKE_OFFSET + \ 86 (APU_PCLI_CPU_STEP * (cpu_id)))) 87 #define APU_PCIL_CORE_X_IDS_WAKE_MASK (0x00000001U) 88 #define CORE_0_ISR_POWER_OFFSET (0x00000010ULL) 89 #define APU_PCIL_CORE_X_ISR_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_ISR_POWER_OFFSET + \ 90 (APU_PCLI_CPU_STEP * (cpu_id)))) 91 #define APU_PCIL_CORE_X_ISR_POWER_MASK U(0x00000001) 92 #define CORE_0_IEN_POWER_OFFSET (0x00000018ULL) 93 #define APU_PCIL_CORE_X_IEN_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IEN_POWER_OFFSET + \ 94 (APU_PCLI_CPU_STEP * (cpu_id)))) 95 #define APU_PCIL_CORE_X_IEN_POWER_MASK (0x00000001U) 96 #define CORE_0_IDS_POWER_OFFSET (0x0000001CULL) 97 #define APU_PCIL_CORE_X_IDS_POWER_REG(cpu_id) (APU_PCLI + (CORE_0_IDS_POWER_OFFSET + \ 98 (APU_PCLI_CPU_STEP * (cpu_id)))) 99 #define APU_PCIL_CORE_X_IDS_POWER_MASK (0x00000001U) 100 #define CORE_PWRDN_EN_BIT_MASK (0x1U) 101 102 /******************************************************************************* 103 * memory map related constants 104 ******************************************************************************/ 105 /* IPP 1.2/SPP 0.9 mapping */ 106 #define DEVICE0_BASE U(0xE8000000) /* psx, crl, iou */ 107 #define DEVICE0_SIZE U(0x08000000) 108 #define DEVICE1_BASE U(0xE2000000) /* gic */ 109 #define DEVICE1_SIZE U(0x00800000) 110 #define DEVICE2_BASE U(0xF1000000) /* uart, pmc_tap */ 111 #define DEVICE2_SIZE U(0x01000000) 112 #define CRF_BASE U(0xFD1A0000) 113 #define CRF_SIZE U(0x00600000) 114 #define IPI_BASE U(0xEB300000) 115 #define IPI_SIZE U(0x00100000) 116 117 /* CRL */ 118 #define VERSAL_NET_CRL U(0xEB5E0000) 119 #define VERSAL_NET_CRL_TIMESTAMP_REF_CTRL_OFFSET U(0x14C) 120 #define VERSAL_NET_CRL_RST_TIMESTAMP_OFFSET U(0x348) 121 122 #define VERSAL_NET_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT (1U << 25U) 123 124 /* IOU SCNTRS */ 125 #define IOU_SCNTRS_BASE U(0xEC920000) 126 #define IOU_SCNTRS_COUNTER_CONTROL_REG_OFFSET U(0) 127 #define IOU_SCNTRS_BASE_FREQ_OFFSET U(0x20) 128 129 #define IOU_SCNTRS_CONTROL_EN U(1) 130 131 #define APU_CLUSTER0 U(0xECC00000) 132 #define APU_RVBAR_L_0 U(0x40) 133 #define APU_RVBAR_H_0 U(0x44) 134 #define APU_CLUSTER_STEP U(0x100000) 135 136 #define SLCR_OSPI_QSPI_IOU_AXI_MUX_SEL U(0xF1060504) 137 138 /******************************************************************************* 139 * IRQ constants 140 ******************************************************************************/ 141 #define VERSAL_NET_IRQ_SEC_PHY_TIMER U(29) 142 #define ARM_IRQ_SEC_PHY_TIMER 29 143 144 /******************************************************************************* 145 * UART related constants 146 ******************************************************************************/ 147 #define VERSAL_NET_UART0_BASE U(0xF1920000) 148 #define VERSAL_NET_UART1_BASE U(0xF1930000) 149 150 #define UART_BAUDRATE 115200 151 152 #if CONSOLE_IS(pl011) || CONSOLE_IS(dtb) 153 #define UART_BASE VERSAL_NET_UART0_BASE 154 # define UART_TYPE CONSOLE_PL011 155 #elif CONSOLE_IS(pl011_1) 156 #define UART_BASE VERSAL_NET_UART1_BASE 157 # define UART_TYPE CONSOLE_PL011 158 #elif CONSOLE_IS(dcc) 159 # define UART_BASE 0x0 160 # define UART_TYPE CONSOLE_DCC 161 #elif CONSOLE_IS(none) 162 # define UART_TYPE CONSOLE_NONE 163 #else 164 # error "invalid VERSAL_NET_CONSOLE" 165 #endif 166 167 /* Runtime console */ 168 #if defined(CONSOLE_RUNTIME) 169 #if RT_CONSOLE_IS(pl011) || RT_CONSOLE_IS(dtb) 170 # define RT_UART_BASE VERSAL_NET_UART0_BASE 171 # define RT_UART_TYPE CONSOLE_PL011 172 #elif RT_CONSOLE_IS(pl011_1) 173 # define RT_UART_BASE VERSAL_NET_UART1_BASE 174 # define RT_UART_TYPE CONSOLE_PL011 175 #elif RT_CONSOLE_IS(dcc) 176 # define RT_UART_BASE 0x0 177 # define RT_UART_TYPE CONSOLE_DCC 178 #else 179 # error "invalid CONSOLE_RUNTIME" 180 #endif 181 #endif 182 183 /* Processor core device IDs */ 184 #define PM_DEV_CLUSTER0_ACPU_0 (0x1810C0AFU) 185 #define PM_DEV_CLUSTER0_ACPU_1 (0x1810C0B0U) 186 #define PM_DEV_CLUSTER0_ACPU_2 (0x1810C0B1U) 187 #define PM_DEV_CLUSTER0_ACPU_3 (0x1810C0B2U) 188 189 #define PM_DEV_CLUSTER1_ACPU_0 (0x1810C0B3U) 190 #define PM_DEV_CLUSTER1_ACPU_1 (0x1810C0B4U) 191 #define PM_DEV_CLUSTER1_ACPU_2 (0x1810C0B5U) 192 #define PM_DEV_CLUSTER1_ACPU_3 (0x1810C0B6U) 193 194 #define PM_DEV_CLUSTER2_ACPU_0 (0x1810C0B7U) 195 #define PM_DEV_CLUSTER2_ACPU_1 (0x1810C0B8U) 196 #define PM_DEV_CLUSTER2_ACPU_2 (0x1810C0B9U) 197 #define PM_DEV_CLUSTER2_ACPU_3 (0x1810C0BAU) 198 199 #define PM_DEV_CLUSTER3_ACPU_0 (0x1810C0BBU) 200 #define PM_DEV_CLUSTER3_ACPU_1 (0x1810C0BCU) 201 #define PM_DEV_CLUSTER3_ACPU_2 (0x1810C0BDU) 202 #define PM_DEV_CLUSTER3_ACPU_3 (0x1810C0BEU) 203 204 #endif /* VERSAL_NET_DEF_H */ 205