1 /* Copyright 2022 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 #pragma once 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 /**************** 31 * VPE OP Codes 32 ****************/ 33 enum VPE_CMD_OPCODE { 34 VPE_CMD_OPCODE_NOP = 0x0, 35 VPE_CMD_OPCODE_VPE_DESC = 0x1, 36 VPE_CMD_OPCODE_PLANE_CFG = 0x2, 37 VPE_CMD_OPCODE_VPEP_CFG = 0x3, 38 VPE_CMD_OPCODE_INDIRECT_BUFFER = 0x4, 39 VPE_CMD_OPCODE_FENCE = 0x5, 40 VPE_CMD_OPCODE_TRAP = 0x6, 41 VPE_CMD_OPCODE_REG_WRITE = 0x7, 42 VPE_CMD_OPCODE_POLL_REGMEM = 0x8, 43 VPE_CMD_OPCODE_COND_EXE = 0x9, 44 VPE_CMD_OPCODE_ATOMIC = 0xA, 45 VPE_CMD_OPCODE_PLANE_FILL = 0xB, 46 VPE_CMD_OPCODE_COLLABORATE_SYNC = 0xC, 47 VPE_CMD_OPCODE_TIMESTAMP = 0xD, 48 }; 49 50 /** Generic Command Header 51 * Generic Commands include: 52 * Noop, Fence, Trap, 53 * RegisterWrite, PollRegisterWriteMemory, 54 * SetLocalTimestamp, GetLocalTimestamp 55 * GetGlobalGPUTimestamp */ 56 #define VPE_HEADER_SUB_OPCODE__SHIFT 8 57 #define VPE_HEADER_SUB_OPCODE_MASK 0x0000FF00 58 #define VPE_HEADER_OPCODE__SHIFT 0 59 #define VPE_HEADER_OPCODE_MASK 0x000000FF 60 61 #define VPE_CMD_HEADER(op, subop) \ 62 (((subop << VPE_HEADER_SUB_OPCODE__SHIFT) & VPE_HEADER_SUB_OPCODE_MASK) | \ 63 ((op << VPE_HEADER_OPCODE__SHIFT) & VPE_HEADER_OPCODE_MASK)) 64 65 /************************ 66 * VPEP Config 67 ************************/ 68 enum VPE_VPEP_CFG_SUBOP { 69 VPE_VPEP_CFG_SUBOP_DIR_CFG = 0x0, 70 VPE_VPEP_CFG_SUBOP_IND_CFG = 0x1 71 }; 72 73 // Direct Config Command Header 74 #define VPE_DIR_CFG_HEADER_ARRAY_SIZE__SHIFT 16 75 #define VPE_DIR_CFG_HEADER_ARRAY_SIZE_MASK 0xFFFF0000 76 77 #define VPE_DIR_CFG_CMD_HEADER(arr_sz) \ 78 (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPEP_CFG, VPE_VPEP_CFG_SUBOP_DIR_CFG) | \ 79 (((arr_sz) << VPE_DIR_CFG_HEADER_ARRAY_SIZE__SHIFT) & VPE_DIR_CFG_HEADER_ARRAY_SIZE_MASK)) 80 #define VPE_DIR_CFG_PKT_REGISTER_OFFSET__SHIFT 2 81 #define VPE_DIR_CFG_PKT_REGISTER_OFFSET_MASK 0x000FFFFC 82 83 #define VPE_DIR_CFG_PKT_DATA_SIZE__SHIFT 20 84 #define VPE_DIR_CFG_PKT_DATA_SIZE_MASK 0xFFF00000 85 86 // InDirect Config Command Header 87 #define VPE_IND_CFG_HEADER_NUM_DST__SHIFT 28 88 #define VPE_IND_CFG_HEADER_NUM_DST_MASK 0xF0000000 89 90 #define VPE_IND_CFG_CMD_HEADER(num_dst) \ 91 (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPEP_CFG, VPE_VPEP_CFG_SUBOP_IND_CFG) | \ 92 ((((uint32_t)num_dst) << VPE_IND_CFG_HEADER_NUM_DST__SHIFT) & \ 93 VPE_IND_CFG_HEADER_NUM_DST_MASK)) 94 95 #define VPE_IND_CFG_DATA_ARRAY_SIZE__SHIFT 0 96 #define VPE_IND_CFG_DATA_ARRAY_SIZE_MASK 0x0007FFFF 97 98 #define VPE_IND_CFG_PKT_REGISTER_OFFSET__SHIFT 2 99 #define VPE_IND_CFG_PKT_REGISTER_OFFSET_MASK 0x000FFFFC 100 101 /************************** 102 * Poll Reg/Mem Sub-OpCode 103 **************************/ 104 enum VPE_POLL_REGMEM_SUBOP { 105 VPE_POLL_REGMEM_SUBOP_REGMEM = 0x0, 106 VPE_POLL_REGMEM_SUBOP_REGMEM_WRITE = 0x1 107 }; 108 109