1 /* 2 * Copyright (c) 2022-2024, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch_def.h> 11 12 #define PLAT_PRIMARY_CPU (0x0) 13 14 #define MT_GIC_BASE (0x0C000000) 15 #define MCUCFG_BASE (0x0C530000) 16 #define MCUCFG_REG_SIZE (0x10000) 17 #define IO_PHYS (0x10000000) 18 19 /* Aggregate of all devices for MMU mapping */ 20 #define MTK_DEV_RNG0_BASE (MT_GIC_BASE) 21 #define MTK_DEV_RNG0_SIZE (0x600000) 22 #define MTK_DEV_RNG1_BASE (IO_PHYS) 23 #define MTK_DEV_RNG1_SIZE (0x10000000) 24 25 #define TOPCKGEN_BASE (IO_PHYS) 26 27 /******************************************************************************* 28 * APUSYS related constants 29 ******************************************************************************/ 30 #define BCRM_FMEM_PDN_BASE (IO_PHYS + 0x00276000) 31 #define APU_MD32_SYSCTRL (IO_PHYS + 0x09001000) 32 #define APU_MD32_WDT (IO_PHYS + 0x09002000) 33 #define APU_RCX_CONFIG (IO_PHYS + 0x09020000) 34 #define APU_CTRL_DAPC_RCX_BASE (IO_PHYS + 0x09034000) 35 #define APU_NOC_DAPC_RCX_BASE (IO_PHYS + 0x09038000) 36 #define APU_REVISER (IO_PHYS + 0x0903c000) 37 #define APU_RCX_VCORE_CONFIG (IO_PHYS + 0x090e0000) 38 #define APU_MBOX0 (IO_PHYS + 0x090e1000) 39 #define APU_MBOX1 (IO_PHYS + 0x090e2000) 40 #define APU_RPCTOP (IO_PHYS + 0x090f0000) 41 #define APU_PCUTOP (IO_PHYS + 0x090f1000) 42 #define APU_AO_CTRL (IO_PHYS + 0x090f2000) 43 #define APU_PLL (IO_PHYS + 0x090f3000) 44 #define APU_ACC (IO_PHYS + 0x090f4000) 45 #define APU_SEC_CON (IO_PHYS + 0x090f5000) 46 #define APU_ARETOP_ARE0 (IO_PHYS + 0x090f6000) 47 #define APU_ARETOP_ARE1 (IO_PHYS + 0x090f7000) 48 #define APU_ARETOP_ARE2 (IO_PHYS + 0x090f8000) 49 #define APU_CTRL_DAPC_AO_BASE (IO_PHYS + 0x090fc000) 50 #define APU_ACX0_RPC_LITE (IO_PHYS + 0x09140000) 51 #define BCRM_FMEM_PDN_SIZE (0x1000) 52 53 /******************************************************************************* 54 * AUDIO related constants 55 ******************************************************************************/ 56 #define AUDIO_BASE (IO_PHYS + 0x00b10000) 57 58 /******************************************************************************* 59 * SPM related constants 60 ******************************************************************************/ 61 #define SPM_BASE (IO_PHYS + 0x00006000) 62 63 /******************************************************************************* 64 * GPIO related constants 65 ******************************************************************************/ 66 #define GPIO_BASE (IO_PHYS + 0x00005000) 67 #define RGU_BASE (IO_PHYS + 0x00007000) 68 #define DRM_BASE (IO_PHYS + 0x0000D000) 69 #define IOCFG_RM_BASE (IO_PHYS + 0x01C00000) 70 #define IOCFG_LT_BASE (IO_PHYS + 0x01E10000) 71 #define IOCFG_LM_BASE (IO_PHYS + 0x01E20000) 72 #define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000) 73 74 /******************************************************************************* 75 * UART related constants 76 ******************************************************************************/ 77 #define UART0_BASE (IO_PHYS + 0x01002000) 78 #define UART_BAUDRATE (115200) 79 80 /******************************************************************************* 81 * PMIC related constants 82 ******************************************************************************/ 83 #define PMIC_WRAP_BASE (IO_PHYS + 0x00024000) 84 85 /******************************************************************************* 86 * Infra IOMMU related constants 87 ******************************************************************************/ 88 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 89 #define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00002000) 90 #define PERICFG_AO_BASE (IO_PHYS + 0x01003000) 91 #define PERICFG_AO_REG_SIZE (0x1000) 92 93 /******************************************************************************* 94 * GIC-600 & interrupt handling related constants 95 ******************************************************************************/ 96 /* Base MTK_platform compatible GIC memory map */ 97 #define BASE_GICD_BASE (MT_GIC_BASE) 98 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 99 #define DEV_IRQ_ID 580 100 101 #define PLAT_MTK_G1S_IRQ_PROPS(grp) \ 102 INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \ 103 GIC_INTR_CFG_LEVEL) 104 105 /******************************************************************************* 106 * CIRQ related constants 107 ******************************************************************************/ 108 #define SYS_CIRQ_BASE (IO_PHYS + 0x204000) 109 #define MD_WDT_IRQ_BIT_ID (141) 110 #define CIRQ_IRQ_NUM (730) 111 #define CIRQ_REG_NUM (23) 112 #define CIRQ_SPI_START (96) 113 114 /******************************************************************************* 115 * MM IOMMU related constants 116 ******************************************************************************/ 117 #define VDO_SECURE_IOMMU_BASE (IO_PHYS + 0x0c028000 + 0x4000) 118 #define VPP_SECURE_IOMMU_BASE (IO_PHYS + 0x04018000 + 0x4000) 119 120 /******************************************************************************* 121 * SMI larb constants 122 ******************************************************************************/ 123 #define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000) 124 #define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000) 125 #define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000) 126 #define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000) 127 #define SMI_LARB_4_BASE (IO_PHYS + 0x04013000) 128 #define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000) 129 #define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000) 130 #define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000) 131 #define SMI_LARB_9_BASE (IO_PHYS + 0x05001000) 132 #define SMI_LARB_10_BASE (IO_PHYS + 0x05120000) 133 #define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000) 134 #define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000) 135 #define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000) 136 #define SMI_LARB_12_BASE (IO_PHYS + 0x05340000) 137 #define SMI_LARB_13_BASE (IO_PHYS + 0x06001000) 138 #define SMI_LARB_14_BASE (IO_PHYS + 0x06002000) 139 #define SMI_LARB_15_BASE (IO_PHYS + 0x05140000) 140 #define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000) 141 #define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000) 142 #define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000) 143 #define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000) 144 #define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000) 145 #define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000) 146 #define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000) 147 #define SMI_LARB_27_BASE (IO_PHYS + 0x07201000) 148 #define SMI_LARB_28_BASE (IO_PHYS + 0x00000000) 149 #define SMI_LARB_REG_RNG_SIZE (0x1000) 150 151 /******************************************************************************* 152 * SPM related constants 153 ******************************************************************************/ 154 #define SPM_BASE (IO_PHYS + 0x00006000) 155 156 /******************************************************************************* 157 * APMIXEDSYS related constants 158 ******************************************************************************/ 159 #define APMIXEDSYS (IO_PHYS + 0x0000C000) 160 161 /******************************************************************************* 162 * VPPSYS related constants 163 ******************************************************************************/ 164 #define VPPSYS0_BASE (IO_PHYS + 0x04000000) 165 #define VPPSYS1_BASE (IO_PHYS + 0x04f00000) 166 167 /******************************************************************************* 168 * VDOSYS related constants 169 ******************************************************************************/ 170 #define VDOSYS0_BASE (IO_PHYS + 0x0C01D000) 171 #define VDOSYS1_BASE (IO_PHYS + 0x0C100000) 172 173 /******************************************************************************* 174 * SSPM_MBOX_3 related constants 175 ******************************************************************************/ 176 #define SSPM_MBOX_3_BASE (IO_PHYS + 0x00480000) 177 178 /******************************************************************************* 179 * DP related constants 180 ******************************************************************************/ 181 #define EDP_SEC_BASE (IO_PHYS + 0x0C504000) 182 #define DP_SEC_BASE (IO_PHYS + 0x0C604000) 183 #define EDP_SEC_SIZE (0x1000) 184 #define DP_SEC_SIZE (0x1000) 185 186 /******************************************************************************* 187 * EMI MPU related constants 188 *******************************************************************************/ 189 #define EMI_MPU_BASE (IO_PHYS + 0x00226000) 190 #define SUB_EMI_MPU_BASE (IO_PHYS + 0x00225000) 191 192 /******************************************************************************* 193 * TRNG related constants 194 ******************************************************************************/ 195 #define TRNG_BASE (IO_PHYS + 0x0020F000) 196 197 /******************************************************************************* 198 * System counter frequency related constants 199 ******************************************************************************/ 200 #define SYS_COUNTER_FREQ_IN_HZ (13000000) 201 #define SYS_COUNTER_FREQ_IN_MHZ (13) 202 203 /******************************************************************************* 204 * Platform binary types for linking 205 ******************************************************************************/ 206 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 207 #define PLATFORM_LINKER_ARCH aarch64 208 209 /******************************************************************************* 210 * Generic platform constants 211 ******************************************************************************/ 212 #define PLATFORM_STACK_SIZE (0x800) 213 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 214 #define SOC_CHIP_ID U(0x8188) 215 216 /******************************************************************************* 217 * Platform memory map related constants 218 ******************************************************************************/ 219 #define TZRAM_BASE (0x54600000) 220 #define TZRAM_SIZE (0x00040000) 221 222 /******************************************************************************* 223 * BL31 specific defines. 224 ******************************************************************************/ 225 /* 226 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 227 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 228 * little space for growth. 229 */ 230 #define BL31_BASE (TZRAM_BASE + 0x1000) 231 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 232 233 /******************************************************************************* 234 * Platform specific page table and MMU setup constants 235 ******************************************************************************/ 236 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 237 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 238 #define MAX_XLAT_TABLES (16) 239 #define MAX_MMAP_REGIONS (16) 240 241 /******************************************************************************* 242 * CPU_EB TCM handling related constants 243 ******************************************************************************/ 244 #define CPU_EB_TCM_BASE (0x0C550000) 245 #define CPU_EB_TCM_SIZE (0x10000) 246 #define CPU_EB_MBOX3_OFFSET (0xFCE0) 247 248 /******************************************************************************* 249 * CPU PM definitions 250 *******************************************************************************/ 251 #define PLAT_CPU_PM_B_BUCK_ISO_ID (6) 252 #define PLAT_CPU_PM_ILDO_ID (6) 253 #define CPU_IDLE_SRAM_BASE (0x11B000) 254 #define CPU_IDLE_SRAM_SIZE (0x1000) 255 256 #endif /* PLATFORM_DEF_H */ 257