1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef V3D_COMPILER_H
25 #define V3D_COMPILER_H
26
27 #include <assert.h>
28 #include <stdio.h>
29 #include <stdlib.h>
30 #include <stdbool.h>
31 #include <stdint.h>
32 #include <string.h>
33
34 #include "util/blend.h"
35 #include "util/macros.h"
36 #include "common/v3d_debug.h"
37 #include "common/v3d_device_info.h"
38 #include "common/v3d_limits.h"
39 #include "compiler/nir/nir.h"
40 #include "util/list.h"
41 #include "util/u_math.h"
42
43 #include "qpu/qpu_instr.h"
44
45 /**
46 * Maximum number of outstanding TMU operations we can queue for execution.
47 *
48 * This is mostly limited by the size of the TMU fifos. The Input and Config
49 * fifos can stall, but we prefer that than injecting TMU flushes manually
50 * in the driver, so we can ignore these, but we can't overflow the Output fifo,
51 * which has 16 / threads per-thread entries, meaning that the maximum number
52 * of outstanding LDTMUs we can ever have is 8, for a 2-way threaded shader.
53 * This means that at most we can have 8 outstanding TMU loads, if each load
54 * is just one component.
55 *
56 * NOTE: we could actually have a larger value here because TMU stores don't
57 * consume any entries in the Output fifo (so we could have any number of
58 * outstanding stores) and the driver keeps track of used Output fifo entries
59 * and will flush if we ever needs more than 8, but since loads are much more
60 * common than stores, it is probably not worth it.
61 */
62 #define MAX_TMU_QUEUE_SIZE 8
63
64 /**
65 * Maximum offset distance in bytes between two consecutive constant UBO loads
66 * for the same UBO where we would favor updating the unifa address by emitting
67 * dummy ldunifa instructions to avoid writing the unifa register.
68 */
69 #define MAX_UNIFA_SKIP_DISTANCE 16
70
71 struct nir_builder;
72
73 struct v3d_fs_inputs {
74 /**
75 * Array of the meanings of the VPM inputs this shader needs.
76 *
77 * It doesn't include those that aren't part of the VPM, like
78 * point/line coordinates.
79 */
80 struct v3d_varying_slot *input_slots;
81 uint32_t num_inputs;
82 };
83
84 enum qfile {
85 /** An unused source or destination register. */
86 QFILE_NULL,
87
88 /** A physical register, such as the W coordinate payload. */
89 QFILE_REG,
90 /** One of the registers for fixed function interactions. */
91 QFILE_MAGIC,
92
93 /**
94 * A virtual register, that will be allocated to actual accumulator
95 * or physical registers later.
96 */
97 QFILE_TEMP,
98
99 /**
100 * Stores an immediate value in the index field that will be used
101 * directly by qpu_load_imm().
102 */
103 QFILE_LOAD_IMM,
104
105 /**
106 * Stores an immediate value in the index field that can be turned
107 * into a small immediate field by qpu_encode_small_immediate().
108 */
109 QFILE_SMALL_IMM,
110 };
111
112 /**
113 * A reference to a QPU register or a virtual temp register.
114 */
115 struct qreg {
116 enum qfile file;
117 uint32_t index;
118 };
119
vir_reg(enum qfile file,uint32_t index)120 static inline struct qreg vir_reg(enum qfile file, uint32_t index)
121 {
122 return (struct qreg){file, index};
123 }
124
vir_magic_reg(uint32_t index)125 static inline struct qreg vir_magic_reg(uint32_t index)
126 {
127 return (struct qreg){QFILE_MAGIC, index};
128 }
129
vir_nop_reg(void)130 static inline struct qreg vir_nop_reg(void)
131 {
132 return (struct qreg){QFILE_NULL, 0};
133 }
134
135 /**
136 * A reference to an actual register at the QPU level, for register
137 * allocation.
138 */
139 struct qpu_reg {
140 bool magic;
141 bool smimm;
142 int index;
143 };
144
145 struct qinst {
146 /** Entry in qblock->instructions */
147 struct list_head link;
148
149 /**
150 * The instruction being wrapped. Its condition codes, pack flags,
151 * signals, etc. will all be used, with just the register references
152 * being replaced by the contents of qinst->dst and qinst->src[].
153 */
154 struct v3d_qpu_instr qpu;
155
156 /* Pre-register-allocation references to src/dst registers */
157 struct qreg dst;
158 struct qreg src[3];
159 bool is_last_thrsw;
160
161 /* If the instruction reads a uniform (other than through src[i].file
162 * == QFILE_UNIF), that uniform's index in c->uniform_contents. ~0
163 * otherwise.
164 */
165 int uniform;
166
167 /* If this is a a TLB Z write */
168 bool is_tlb_z_write;
169
170 /* If this is a retiring TMU instruction (the last in a lookup sequence),
171 * how many ldtmu instructions are required to read the results.
172 */
173 uint32_t ldtmu_count;
174
175 /* Position of this instruction in the program. Filled in during
176 * register allocation.
177 */
178 int32_t ip;
179 };
180
181 enum quniform_contents {
182 /**
183 * Indicates that a constant 32-bit value is copied from the program's
184 * uniform contents.
185 */
186 QUNIFORM_CONSTANT,
187 /**
188 * Indicates that the program's uniform contents are used as an index
189 * into the GL uniform storage.
190 */
191 QUNIFORM_UNIFORM,
192
193 /** @{
194 * Scaling factors from clip coordinates to relative to the viewport
195 * center.
196 *
197 * This is used by the coordinate and vertex shaders to produce the
198 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
199 * point offsets from the viewport ccenter.
200 */
201 QUNIFORM_VIEWPORT_X_SCALE,
202 QUNIFORM_VIEWPORT_Y_SCALE,
203 /** @} */
204
205 QUNIFORM_VIEWPORT_Z_OFFSET,
206 QUNIFORM_VIEWPORT_Z_SCALE,
207
208 QUNIFORM_USER_CLIP_PLANE,
209
210 /**
211 * A reference to a V3D 3.x texture config parameter 0 uniform.
212 *
213 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
214 * defines texture type, miplevels, and such. It will be found as a
215 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
216 */
217 QUNIFORM_TEXTURE_CONFIG_P0_0,
218 QUNIFORM_TEXTURE_CONFIG_P0_1,
219 QUNIFORM_TEXTURE_CONFIG_P0_2,
220 QUNIFORM_TEXTURE_CONFIG_P0_3,
221 QUNIFORM_TEXTURE_CONFIG_P0_4,
222 QUNIFORM_TEXTURE_CONFIG_P0_5,
223 QUNIFORM_TEXTURE_CONFIG_P0_6,
224 QUNIFORM_TEXTURE_CONFIG_P0_7,
225 QUNIFORM_TEXTURE_CONFIG_P0_8,
226 QUNIFORM_TEXTURE_CONFIG_P0_9,
227 QUNIFORM_TEXTURE_CONFIG_P0_10,
228 QUNIFORM_TEXTURE_CONFIG_P0_11,
229 QUNIFORM_TEXTURE_CONFIG_P0_12,
230 QUNIFORM_TEXTURE_CONFIG_P0_13,
231 QUNIFORM_TEXTURE_CONFIG_P0_14,
232 QUNIFORM_TEXTURE_CONFIG_P0_15,
233 QUNIFORM_TEXTURE_CONFIG_P0_16,
234 QUNIFORM_TEXTURE_CONFIG_P0_17,
235 QUNIFORM_TEXTURE_CONFIG_P0_18,
236 QUNIFORM_TEXTURE_CONFIG_P0_19,
237 QUNIFORM_TEXTURE_CONFIG_P0_20,
238 QUNIFORM_TEXTURE_CONFIG_P0_21,
239 QUNIFORM_TEXTURE_CONFIG_P0_22,
240 QUNIFORM_TEXTURE_CONFIG_P0_23,
241 QUNIFORM_TEXTURE_CONFIG_P0_24,
242 QUNIFORM_TEXTURE_CONFIG_P0_25,
243 QUNIFORM_TEXTURE_CONFIG_P0_26,
244 QUNIFORM_TEXTURE_CONFIG_P0_27,
245 QUNIFORM_TEXTURE_CONFIG_P0_28,
246 QUNIFORM_TEXTURE_CONFIG_P0_29,
247 QUNIFORM_TEXTURE_CONFIG_P0_30,
248 QUNIFORM_TEXTURE_CONFIG_P0_31,
249 QUNIFORM_TEXTURE_CONFIG_P0_32,
250
251 /**
252 * A reference to a V3D 3.x texture config parameter 1 uniform.
253 *
254 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
255 * has the pointer to the indirect texture state. Our data[] field
256 * will have a packed p1 value, but the address field will be just
257 * which texture unit's texture should be referenced.
258 */
259 QUNIFORM_TEXTURE_CONFIG_P1,
260
261 /* A V3D 4.x texture config parameter. The high 8 bits will be
262 * which texture or sampler is being sampled, and the driver must
263 * replace the address field with the appropriate address.
264 */
265 QUNIFORM_TMU_CONFIG_P0,
266 QUNIFORM_TMU_CONFIG_P1,
267
268 QUNIFORM_IMAGE_TMU_CONFIG_P0,
269
270 QUNIFORM_TEXTURE_FIRST_LEVEL,
271
272 QUNIFORM_TEXTURE_WIDTH,
273 QUNIFORM_TEXTURE_HEIGHT,
274 QUNIFORM_TEXTURE_DEPTH,
275 QUNIFORM_TEXTURE_ARRAY_SIZE,
276 QUNIFORM_TEXTURE_LEVELS,
277 QUNIFORM_TEXTURE_SAMPLES,
278
279 QUNIFORM_UBO_ADDR,
280
281 QUNIFORM_TEXRECT_SCALE_X,
282 QUNIFORM_TEXRECT_SCALE_Y,
283
284 /* Returns the base offset of the SSBO given by the data value. */
285 QUNIFORM_SSBO_OFFSET,
286
287 /* Returns the size of the SSBO or UBO given by the data value. */
288 QUNIFORM_GET_SSBO_SIZE,
289 QUNIFORM_GET_UBO_SIZE,
290
291 /* Sizes (in pixels) of a shader image given by the data value. */
292 QUNIFORM_IMAGE_WIDTH,
293 QUNIFORM_IMAGE_HEIGHT,
294 QUNIFORM_IMAGE_DEPTH,
295 QUNIFORM_IMAGE_ARRAY_SIZE,
296
297 QUNIFORM_LINE_WIDTH,
298
299 /* The line width sent to hardware. This includes the expanded width
300 * when anti-aliasing is enabled.
301 */
302 QUNIFORM_AA_LINE_WIDTH,
303
304 /* Number of workgroups passed to glDispatchCompute in the dimension
305 * selected by the data value.
306 */
307 QUNIFORM_NUM_WORK_GROUPS,
308
309 /* Base workgroup offset passed to vkCmdDispatchBase in the dimension
310 * selected by the data value.
311 */
312 QUNIFORM_WORK_GROUP_BASE,
313
314 /* Workgroup size for variable workgroup support */
315 QUNIFORM_WORK_GROUP_SIZE,
316
317 /**
318 * Returns the the offset of the scratch buffer for register spilling.
319 */
320 QUNIFORM_SPILL_OFFSET,
321 QUNIFORM_SPILL_SIZE_PER_THREAD,
322
323 /**
324 * Returns the offset of the shared memory for compute shaders.
325 *
326 * This will be accessed using TMU general memory operations, so the
327 * L2T cache will effectively be the shared memory area.
328 */
329 QUNIFORM_SHARED_OFFSET,
330
331 /**
332 * OpenCL variable shared memory
333 *
334 * This will only be used when the shader declares variable_shared_memory.
335 */
336 QUNIFORM_SHARED_SIZE,
337
338 /**
339 * Returns the number of layers in the framebuffer.
340 *
341 * This is used to cap gl_Layer in geometry shaders to avoid
342 * out-of-bounds accesses into the tile state during binning.
343 */
344 QUNIFORM_FB_LAYERS,
345
346 /**
347 * Current value of gl_ViewIndex for Multiview rendering.
348 */
349 QUNIFORM_VIEW_INDEX,
350
351 /**
352 * Inline uniform buffers
353 */
354 QUNIFORM_INLINE_UBO_0,
355 QUNIFORM_INLINE_UBO_1,
356 QUNIFORM_INLINE_UBO_2,
357 QUNIFORM_INLINE_UBO_3,
358
359 /**
360 * Current value of DrawIndex for Multidraw
361 */
362 QUNIFORM_DRAW_ID,
363 };
364
v3d_unit_data_create(uint32_t unit,uint32_t value)365 static inline uint32_t v3d_unit_data_create(uint32_t unit, uint32_t value)
366 {
367 assert(value < (1 << 24));
368 return unit << 24 | value;
369 }
370
v3d_unit_data_get_unit(uint32_t data)371 static inline uint32_t v3d_unit_data_get_unit(uint32_t data)
372 {
373 return data >> 24;
374 }
375
v3d_unit_data_get_offset(uint32_t data)376 static inline uint32_t v3d_unit_data_get_offset(uint32_t data)
377 {
378 return data & 0xffffff;
379 }
380
381 struct v3d_varying_slot {
382 uint8_t slot_and_component;
383 };
384
385 static inline struct v3d_varying_slot
v3d_slot_from_slot_and_component(uint8_t slot,uint8_t component)386 v3d_slot_from_slot_and_component(uint8_t slot, uint8_t component)
387 {
388 assert(slot < 255 / 4);
389 return (struct v3d_varying_slot){ (slot << 2) + component };
390 }
391
v3d_slot_get_slot(struct v3d_varying_slot slot)392 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot)
393 {
394 return slot.slot_and_component >> 2;
395 }
396
v3d_slot_get_component(struct v3d_varying_slot slot)397 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot)
398 {
399 return slot.slot_and_component & 3;
400 }
401
402 struct v3d_key {
403 struct {
404 uint8_t swizzle[4];
405 } tex[V3D_MAX_TEXTURE_SAMPLERS];
406 struct {
407 uint8_t return_size;
408 uint8_t return_channels;
409 } sampler[V3D_MAX_TEXTURE_SAMPLERS];
410
411 uint8_t num_tex_used;
412 uint8_t num_samplers_used;
413 uint8_t ucp_enables;
414 bool is_last_geometry_stage;
415 bool robust_uniform_access;
416 bool robust_storage_access;
417 bool robust_image_access;
418 };
419
420 struct v3d_fs_key {
421 struct v3d_key base;
422 bool is_points;
423 bool is_lines;
424 bool line_smoothing;
425 bool point_coord_upper_left;
426 bool msaa;
427 bool sample_alpha_to_coverage;
428 bool sample_alpha_to_one;
429 bool can_earlyz_with_discard;
430 /* Mask of which color render targets are present. */
431 uint8_t cbufs;
432 uint8_t swap_color_rb;
433 /* Mask of which render targets need to be written as 32-bit floats */
434 uint8_t f32_color_rb;
435 /* Masks of which render targets need to be written as ints/uints.
436 * Used by gallium to work around lost information in TGSI.
437 */
438 uint8_t int_color_rb;
439 uint8_t uint_color_rb;
440
441 /* Color format information per render target. Only set when logic
442 * operations are enabled.
443 */
444 struct {
445 enum pipe_format format;
446 uint8_t swizzle[4];
447 } color_fmt[V3D_MAX_DRAW_BUFFERS];
448
449 enum pipe_logicop logicop_func;
450 uint32_t point_sprite_mask;
451
452 /* If the fragment shader reads gl_PrimitiveID then we have 2 scenarios:
453 *
454 * - If there is a geometry shader, then gl_PrimitiveID must be written
455 * by it and the fragment shader loads it as a regular explicit input
456 * varying. This is the only valid use case in GLES 3.1.
457 *
458 * - If there is not a geometry shader (allowed since GLES 3.2 and
459 * Vulkan 1.0), then gl_PrimitiveID must be implicitly written by
460 * hardware and is considered an implicit input varying in the
461 * fragment shader.
462 */
463 bool has_gs;
464 };
465
466 struct v3d_gs_key {
467 struct v3d_key base;
468
469 struct v3d_varying_slot used_outputs[V3D_MAX_FS_INPUTS];
470 uint8_t num_used_outputs;
471
472 bool is_coord;
473 bool per_vertex_point_size;
474 };
475
476 struct v3d_vs_key {
477 struct v3d_key base;
478
479 struct v3d_varying_slot used_outputs[V3D_MAX_ANY_STAGE_INPUTS];
480 uint8_t num_used_outputs;
481
482 /* A bit-mask indicating if we need to swap the R/B channels for
483 * vertex attributes. Since the hardware doesn't provide any
484 * means to swizzle vertex attributes we need to do it in the shader.
485 */
486 uint32_t va_swap_rb_mask;
487
488 bool is_coord;
489 bool per_vertex_point_size;
490 bool clamp_color;
491 };
492
493 /** A basic block of VIR instructions. */
494 struct qblock {
495 struct list_head link;
496
497 struct list_head instructions;
498
499 struct set *predecessors;
500 struct qblock *successors[2];
501
502 int index;
503
504 /* Instruction IPs for the first and last instruction of the block.
505 * Set by qpu_schedule.c.
506 */
507 uint32_t start_qpu_ip;
508 uint32_t end_qpu_ip;
509
510 /* Instruction IP for the branch instruction of the block. Set by
511 * qpu_schedule.c.
512 */
513 uint32_t branch_qpu_ip;
514
515 /** Offset within the uniform stream at the start of the block. */
516 uint32_t start_uniform;
517 /** Offset within the uniform stream of the branch instruction */
518 uint32_t branch_uniform;
519
520 /**
521 * Has the terminating branch of this block already been emitted
522 * by a break or continue?
523 */
524 bool branch_emitted;
525
526 /** @{ used by v3d_vir_live_variables.c */
527 BITSET_WORD *def;
528 BITSET_WORD *defin;
529 BITSET_WORD *defout;
530 BITSET_WORD *use;
531 BITSET_WORD *live_in;
532 BITSET_WORD *live_out;
533 int start_ip, end_ip;
534 /** @} */
535 };
536
537 /** Which util/list.h add mode we should use when inserting an instruction. */
538 enum vir_cursor_mode {
539 vir_cursor_add,
540 vir_cursor_addtail,
541 };
542
543 /**
544 * Tracking structure for where new instructions should be inserted. Create
545 * with one of the vir_after_inst()-style helper functions.
546 *
547 * This does not protect against removal of the block or instruction, so we
548 * have an assert in instruction removal to try to catch it.
549 */
550 struct vir_cursor {
551 enum vir_cursor_mode mode;
552 struct list_head *link;
553 };
554
555 static inline struct vir_cursor
vir_before_inst(struct qinst * inst)556 vir_before_inst(struct qinst *inst)
557 {
558 return (struct vir_cursor){ vir_cursor_addtail, &inst->link };
559 }
560
561 static inline struct vir_cursor
vir_after_inst(struct qinst * inst)562 vir_after_inst(struct qinst *inst)
563 {
564 return (struct vir_cursor){ vir_cursor_add, &inst->link };
565 }
566
567 static inline struct vir_cursor
vir_before_block(struct qblock * block)568 vir_before_block(struct qblock *block)
569 {
570 return (struct vir_cursor){ vir_cursor_add, &block->instructions };
571 }
572
573 static inline struct vir_cursor
vir_after_block(struct qblock * block)574 vir_after_block(struct qblock *block)
575 {
576 return (struct vir_cursor){ vir_cursor_addtail, &block->instructions };
577 }
578
579 enum v3d_compilation_result {
580 V3D_COMPILATION_SUCCEEDED,
581 V3D_COMPILATION_FAILED_REGISTER_ALLOCATION,
582 V3D_COMPILATION_FAILED,
583 };
584
585 /**
586 * Compiler state saved across compiler invocations, for any expensive global
587 * setup.
588 */
589 struct v3d_compiler {
590 const struct v3d_device_info *devinfo;
591 uint32_t max_inline_uniform_buffers;
592 struct ra_regs *regs;
593 struct ra_class *reg_class_any[3];
594 struct ra_class *reg_class_r5[3];
595 struct ra_class *reg_class_phys[3];
596 struct ra_class *reg_class_phys_or_acc[3];
597 };
598
599 /**
600 * This holds partially interpolated inputs as provided by hardware
601 * (The Vp = A*(x - x0) + B*(y - y0) term), as well as the C coefficient
602 * required to compute the final interpolated value.
603 */
604 struct v3d_interp_input {
605 struct qreg vp;
606 struct qreg C;
607 unsigned mode; /* interpolation mode */
608 };
609
610 struct v3d_ra_node_info {
611 struct {
612 uint32_t priority;
613 uint8_t class_bits;
614 bool is_program_end;
615 bool unused;
616
617 /* If this node may have an allocation conflict with a
618 * payload register.
619 */
620 bool payload_conflict;
621
622 /* V3D 7.x */
623 bool try_rf0;
624 } *info;
625 uint32_t alloc_count;
626 };
627
628 struct v3d_compile {
629 const struct v3d_device_info *devinfo;
630 nir_shader *s;
631 nir_function_impl *impl;
632 struct exec_list *cf_node_list;
633 const struct v3d_compiler *compiler;
634
635 void (*debug_output)(const char *msg,
636 void *debug_output_data);
637 void *debug_output_data;
638
639 /**
640 * Mapping from nir_register * or nir_def * to array of struct
641 * qreg for the values.
642 */
643 struct hash_table *def_ht;
644
645 /* For each temp, the instruction generating its value. */
646 struct qinst **defs;
647 uint32_t defs_array_size;
648
649 /* TMU pipelining tracking */
650 struct {
651 /* NIR registers that have been updated with a TMU operation
652 * that has not been flushed yet.
653 */
654 struct set *outstanding_regs;
655
656 uint32_t output_fifo_size;
657
658 struct {
659 nir_def *def;
660 uint8_t num_components;
661 uint8_t component_mask;
662 } flush[MAX_TMU_QUEUE_SIZE];
663 uint32_t flush_count;
664 uint32_t total_count;
665 } tmu;
666
667 /**
668 * Inputs to the shader, arranged by TGSI declaration order.
669 *
670 * Not all fragment shader QFILE_VARY reads are present in this array.
671 */
672 struct qreg *inputs;
673 /**
674 * Partially interpolated inputs to the shader.
675 */
676 struct v3d_interp_input *interp;
677 struct qreg *outputs;
678 bool msaa_per_sample_output;
679 struct qreg color_reads[V3D_MAX_DRAW_BUFFERS * V3D_MAX_SAMPLES * 4];
680 struct qreg sample_colors[V3D_MAX_DRAW_BUFFERS * V3D_MAX_SAMPLES * 4];
681 uint32_t inputs_array_size;
682 uint32_t outputs_array_size;
683 uint32_t uniforms_array_size;
684
685 /* Booleans for whether the corresponding QFILE_VARY[i] is
686 * flat-shaded. This includes gl_FragColor flat-shading, which is
687 * customized based on the shademodel_flat shader key.
688 */
689 uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
690
691 uint32_t noperspective_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
692
693 uint32_t centroid_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
694
695 bool uses_center_w;
696 bool writes_z;
697 bool writes_z_from_fep;
698 bool reads_z;
699 bool uses_implicit_point_line_varyings;
700
701 /* True if a fragment shader reads gl_PrimitiveID */
702 bool fs_uses_primitive_id;
703
704 /* Whether we are using the fallback scheduler. This will be set after
705 * register allocation has failed once.
706 */
707 bool fallback_scheduler;
708
709 /* Disable TMU pipelining. This may increase the chances of being able
710 * to compile shaders with high register pressure that require to emit
711 * TMU spills.
712 */
713 bool disable_tmu_pipelining;
714 bool pipelined_any_tmu;
715
716 /* Disable sorting of UBO loads with constant offset. This may
717 * increase the chances of being able to compile shaders with high
718 * register pressure.
719 */
720 bool disable_constant_ubo_load_sorting;
721 bool sorted_any_ubo_loads;
722
723 /* Moves UBO/SSBO loads right before their first user (nir_opt_move).
724 * This can reduce register pressure.
725 */
726 bool move_buffer_loads;
727
728 /* Emits ldunif for each new uniform, even if the uniform was already
729 * emitted in the same block. Useful to compile shaders with high
730 * register pressure or to disable the optimization during uniform
731 * spills.
732 */
733 bool disable_ldunif_opt;
734
735 /* Disables loop unrolling to reduce register pressure. */
736 bool disable_loop_unrolling;
737 bool unrolled_any_loops;
738
739 /* Disables nir_opt_gcm to reduce register pressure. */
740 bool disable_gcm;
741
742 /* If calling nir_opt_gcm made any progress. Used to skip new rebuilds
743 * if possible
744 */
745 bool gcm_progress;
746
747 /* Disables scheduling of general TMU loads (and unfiltered image load).
748 */
749 bool disable_general_tmu_sched;
750 bool has_general_tmu_load;
751
752 /* Minimum number of threads we are willing to use to register allocate
753 * a shader with the current compilation strategy. This only prevents
754 * us from lowering the thread count to register allocate successfully,
755 * which can be useful when we prefer doing other changes to the
756 * compilation strategy before dropping thread count.
757 */
758 uint32_t min_threads_for_reg_alloc;
759
760 /* Whether TMU spills are allowed. If this is disabled it may cause
761 * register allocation to fail. We set this to favor other compilation
762 * strategies that can reduce register pressure and hopefully reduce or
763 * eliminate TMU spills in the shader.
764 */
765 uint32_t max_tmu_spills;
766
767 uint32_t compile_strategy_idx;
768
769 /* The UBO index and block used with the last unifa load, as well as the
770 * current unifa offset *after* emitting that load. This is used to skip
771 * unifa writes (and their 3 delay slot) when the next UBO load reads
772 * right after the previous one in the same block.
773 */
774 struct qblock *current_unifa_block;
775 int32_t current_unifa_index;
776 uint32_t current_unifa_offset;
777 bool current_unifa_is_ubo;
778
779 /* State for whether we're executing on each channel currently. 0 if
780 * yes, otherwise a block number + 1 that the channel jumped to.
781 */
782 struct qreg execute;
783 bool in_control_flow;
784
785 struct qreg line_x, point_x, point_y, primitive_id;
786
787 /**
788 * Instance ID, which comes in before the vertex attribute payload if
789 * the shader record requests it.
790 */
791 struct qreg iid;
792
793 /**
794 * Base Instance ID, which comes in before the vertex attribute payload
795 * (after Instance ID) if the shader record requests it.
796 */
797 struct qreg biid;
798
799 /**
800 * Vertex ID, which comes in before the vertex attribute payload
801 * (after Base Instance) if the shader record requests it.
802 */
803 struct qreg vid;
804
805 /* Fragment shader payload regs. */
806 struct qreg payload_w, payload_w_centroid, payload_z;
807
808 struct qreg cs_payload[2];
809 struct qreg cs_shared_offset;
810 int local_invocation_index_bits;
811
812 /* Starting value of the sample mask in a fragment shader. We use
813 * this to identify lanes that have been terminated/discarded.
814 */
815 struct qreg start_msf;
816
817 /* If the shader uses subgroup functionality */
818 bool has_subgroups;
819
820 uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
821 uint32_t vpm_output_size;
822
823 /* Size in bytes of registers that have been spilled. This is how much
824 * space needs to be available in the spill BO per thread per QPU.
825 */
826 uint32_t spill_size;
827 /* Shader-db stats */
828 uint32_t spills, fills, loops;
829
830 /* Whether we are in the process of spilling registers for
831 * register allocation
832 */
833 bool spilling;
834
835 /**
836 * Register spilling's per-thread base address, shared between each
837 * spill/fill's addressing calculations (also used for scratch
838 * access).
839 */
840 struct qreg spill_base;
841
842 /* Bit vector of which temps may be spilled */
843 BITSET_WORD *spillable;
844
845 /* Used during register allocation */
846 int thread_index;
847 struct v3d_ra_node_info nodes;
848 struct ra_graph *g;
849
850 /**
851 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
852 *
853 * This includes those that aren't part of the VPM varyings, like
854 * point/line coordinates.
855 */
856 struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
857
858 /**
859 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
860 * of the output is. Used to emit from the VS in the order that the
861 * FS needs.
862 */
863 struct v3d_varying_slot *output_slots;
864
865 struct pipe_shader_state *shader_state;
866 struct v3d_key *key;
867 struct v3d_fs_key *fs_key;
868 struct v3d_gs_key *gs_key;
869 struct v3d_vs_key *vs_key;
870
871 /* Live ranges of temps. */
872 int *temp_start, *temp_end;
873 bool live_intervals_valid;
874
875 uint32_t *uniform_data;
876 enum quniform_contents *uniform_contents;
877 uint32_t uniform_array_size;
878 uint32_t num_uniforms;
879 uint32_t output_position_index;
880 nir_variable *output_color_var[V3D_MAX_DRAW_BUFFERS];
881 uint32_t output_sample_mask_index;
882
883 struct qreg undef;
884 uint32_t num_temps;
885 /* Number of temps in the program right before we spill a new temp. We
886 * use this to know which temps existed before a spill and which were
887 * added with the spill itself.
888 */
889 uint32_t spill_start_num_temps;
890
891 struct vir_cursor cursor;
892 struct list_head blocks;
893 int next_block_index;
894 struct qblock *cur_block;
895 struct qblock *loop_cont_block;
896 struct qblock *loop_break_block;
897 /**
898 * Which temp, if any, do we currently have in the flags?
899 * This is set when processing a comparison instruction, and
900 * reset to -1 by anything else that touches the flags.
901 */
902 int32_t flags_temp;
903 enum v3d_qpu_cond flags_cond;
904
905 uint64_t *qpu_insts;
906 uint32_t qpu_inst_count;
907 uint32_t qpu_inst_size;
908 uint32_t qpu_inst_stalled_count;
909 uint32_t nop_count;
910
911 /* For the FS, the number of varying inputs not counting the
912 * point/line varyings payload
913 */
914 uint32_t num_inputs;
915
916 uint32_t program_id;
917 uint32_t variant_id;
918
919 /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
920 * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
921 * limiting ourselves to the part of the physical reg space.
922 *
923 * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x. On
924 * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
925 * physical reg space in half.
926 */
927 uint8_t threads;
928 struct qinst *last_thrsw;
929 bool last_thrsw_at_top_level;
930
931 bool emitted_tlb_load;
932 bool lock_scoreboard_on_first_thrsw;
933
934 enum v3d_compilation_result compilation_result;
935
936 bool tmu_dirty_rcl;
937 bool has_global_address;
938
939 /* If we have processed a discard/terminate instruction. This may
940 * cause some lanes to be inactive even during uniform control
941 * flow.
942 */
943 bool emitted_discard;
944 };
945
946 struct v3d_uniform_list {
947 enum quniform_contents *contents;
948 uint32_t *data;
949 uint32_t count;
950 };
951
952 struct v3d_prog_data {
953 struct v3d_uniform_list uniforms;
954
955 uint32_t spill_size;
956 uint32_t tmu_spills;
957 uint32_t tmu_fills;
958 uint32_t tmu_count;
959
960 uint32_t qpu_read_stalls;
961
962 uint8_t compile_strategy_idx;
963
964 uint8_t threads;
965
966 /* For threads > 1, whether the program should be dispatched in the
967 * after-final-THRSW state.
968 */
969 bool single_seg;
970
971 bool tmu_dirty_rcl;
972
973 bool has_control_barrier;
974
975 bool has_global_address;
976 };
977
978 struct v3d_vs_prog_data {
979 struct v3d_prog_data base;
980
981 bool uses_iid, uses_biid, uses_vid;
982
983 /* Number of components read from each vertex attribute. */
984 uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
985
986 /* Total number of components read, for the shader state record. */
987 uint32_t vpm_input_size;
988
989 /* Total number of components written, for the shader state record. */
990 uint32_t vpm_output_size;
991
992 /* Set if there should be separate VPM segments for input and output.
993 * If unset, vpm_input_size will be 0.
994 */
995 bool separate_segments;
996
997 /* Value to be programmed in VCM_CACHE_SIZE. */
998 uint8_t vcm_cache_size;
999
1000 bool writes_psiz;
1001
1002 /* Maps the nir->data.location to its
1003 * nir->data.driver_location. In general we are using the
1004 * driver location as index (like vattr_sizes above), so this
1005 * map is useful when what we have is the location
1006 *
1007 * Returns -1 if the location is not used
1008 */
1009 int32_t driver_location_map[V3D_MAX_VS_INPUTS];
1010 };
1011
1012 struct v3d_gs_prog_data {
1013 struct v3d_prog_data base;
1014
1015 /* Whether the program reads gl_PrimitiveIDIn */
1016 bool uses_pid;
1017
1018 /* Number of components read from each input varying. */
1019 uint8_t input_sizes[V3D_MAX_GS_INPUTS / 4];
1020
1021 /* Number of inputs */
1022 uint8_t num_inputs;
1023 struct v3d_varying_slot input_slots[V3D_MAX_GS_INPUTS];
1024
1025 /* Total number of components written, for the shader state record. */
1026 uint32_t vpm_output_size;
1027
1028 /* Maximum SIMD dispatch width to not exceed VPM output size limits
1029 * in the geometry shader. Notice that the final dispatch width has to
1030 * be decided at draw time and could be lower based on the VPM pressure
1031 * added by other shader stages.
1032 */
1033 uint8_t simd_width;
1034
1035 /* Output primitive type */
1036 uint8_t out_prim_type;
1037
1038 /* Number of GS invocations */
1039 uint8_t num_invocations;
1040
1041 bool writes_psiz;
1042 };
1043
1044 struct v3d_fs_prog_data {
1045 struct v3d_prog_data base;
1046
1047 /* Whether the program reads gl_PrimitiveID */
1048 bool uses_pid;
1049
1050 struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
1051
1052 /* Array of flat shade flags.
1053 *
1054 * Each entry is only 24 bits (high 8 bits 0), to match the hardware
1055 * packet layout.
1056 */
1057 uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
1058
1059 uint32_t noperspective_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
1060
1061 uint32_t centroid_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
1062
1063 uint8_t num_inputs;
1064 bool writes_z;
1065 bool writes_z_from_fep;
1066 bool disable_ez;
1067 bool uses_center_w;
1068 bool uses_implicit_point_line_varyings;
1069 bool lock_scoreboard_on_first_thrsw;
1070
1071 /* If the fragment shader does anything that requires to force
1072 * per-sample MSAA, such as reading gl_SampleID.
1073 */
1074 bool force_per_sample_msaa;
1075 };
1076
1077 struct v3d_compute_prog_data {
1078 struct v3d_prog_data base;
1079 /* Size in bytes of the workgroup's shared space. */
1080 uint32_t shared_size;
1081 uint16_t local_size[3];
1082 /* If the shader uses subgroup functionality */
1083 bool has_subgroups;
1084 };
1085
1086 struct vpm_config {
1087 uint32_t As;
1088 uint32_t Vc;
1089 uint32_t Gs;
1090 uint32_t Gd;
1091 uint32_t Gv;
1092 uint32_t Ve;
1093 uint32_t gs_width;
1094 };
1095
1096 bool
1097 v3d_compute_vpm_config(struct v3d_device_info *devinfo,
1098 struct v3d_vs_prog_data *vs_bin,
1099 struct v3d_vs_prog_data *vs,
1100 struct v3d_gs_prog_data *gs_bin,
1101 struct v3d_gs_prog_data *gs,
1102 struct vpm_config *vpm_cfg_bin,
1103 struct vpm_config *vpm_cfg);
1104 void
1105 v3d_pack_unnormalized_coordinates(struct v3d_device_info *devinfo,
1106 uint32_t *p1_packed,
1107 bool unnormalized_coordinates);
1108
1109 static inline bool
vir_has_uniform(struct qinst * inst)1110 vir_has_uniform(struct qinst *inst)
1111 {
1112 return inst->uniform != ~0;
1113 }
1114
1115 const struct v3d_compiler *v3d_compiler_init(const struct v3d_device_info *devinfo,
1116 uint32_t max_inline_uniform_buffers);
1117 void v3d_compiler_free(const struct v3d_compiler *compiler);
1118 void v3d_optimize_nir(struct v3d_compile *c, struct nir_shader *s);
1119
1120 uint64_t *v3d_compile(const struct v3d_compiler *compiler,
1121 struct v3d_key *key,
1122 struct v3d_prog_data **prog_data,
1123 nir_shader *s,
1124 void (*debug_output)(const char *msg,
1125 void *debug_output_data),
1126 void *debug_output_data,
1127 int program_id, int variant_id,
1128 uint32_t *final_assembly_size);
1129
1130 uint32_t v3d_prog_data_size(gl_shader_stage stage);
1131 void v3d_nir_to_vir(struct v3d_compile *c);
1132
1133 void vir_compile_destroy(struct v3d_compile *c);
1134 const char *vir_get_stage_name(struct v3d_compile *c);
1135 struct qblock *vir_new_block(struct v3d_compile *c);
1136 void vir_set_emit_block(struct v3d_compile *c, struct qblock *block);
1137 void vir_link_blocks(struct qblock *predecessor, struct qblock *successor);
1138 struct qblock *vir_entry_block(struct v3d_compile *c);
1139 struct qblock *vir_exit_block(struct v3d_compile *c);
1140 struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst,
1141 struct qreg src0, struct qreg src1);
1142 struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst,
1143 struct qreg src0, struct qreg src1);
1144 struct qinst *vir_branch_inst(struct v3d_compile *c,
1145 enum v3d_qpu_branch_cond cond);
1146 void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst);
1147 uint32_t vir_get_uniform_index(struct v3d_compile *c,
1148 enum quniform_contents contents,
1149 uint32_t data);
1150 struct qreg vir_uniform(struct v3d_compile *c,
1151 enum quniform_contents contents,
1152 uint32_t data);
1153 void vir_schedule_instructions(struct v3d_compile *c);
1154 void v3d_setup_spill_base(struct v3d_compile *c);
1155 struct v3d_qpu_instr v3d_qpu_nop(void);
1156
1157 struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst);
1158 struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
1159 void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
1160 enum v3d_qpu_cond vir_get_cond(struct qinst *inst);
1161 void vir_set_pf(struct v3d_compile *c, struct qinst *inst, enum v3d_qpu_pf pf);
1162 void vir_set_uf(struct v3d_compile *c, struct qinst *inst, enum v3d_qpu_uf uf);
1163 void vir_set_unpack(struct qinst *inst, int src,
1164 enum v3d_qpu_input_unpack unpack);
1165 void vir_set_pack(struct qinst *inst, enum v3d_qpu_output_pack pack);
1166
1167 struct qreg vir_get_temp(struct v3d_compile *c);
1168 void vir_calculate_live_intervals(struct v3d_compile *c);
1169 int vir_get_nsrc(struct qinst *inst);
1170 bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst);
1171 bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op);
1172 bool vir_get_mul_op(struct qinst *inst, enum v3d_qpu_mul_op *op);
1173 bool vir_is_raw_mov(struct qinst *inst);
1174 bool vir_is_tex(const struct v3d_device_info *devinfo, struct qinst *inst);
1175 bool vir_is_add(struct qinst *inst);
1176 bool vir_is_mul(struct qinst *inst);
1177 bool vir_writes_r4_implicitly(const struct v3d_device_info *devinfo, struct qinst *inst);
1178 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
1179 uint8_t vir_channels_written(struct qinst *inst);
1180 struct qreg ntq_get_src(struct v3d_compile *c, nir_src src, int i);
1181 void ntq_store_def(struct v3d_compile *c, nir_def *def, int chan,
1182 struct qreg result);
1183 bool ntq_tmu_fifo_overflow(struct v3d_compile *c, uint32_t components);
1184 void ntq_add_pending_tmu_flush(struct v3d_compile *c, nir_def *def,
1185 uint32_t component_mask);
1186 void ntq_flush_tmu(struct v3d_compile *c);
1187 void vir_emit_thrsw(struct v3d_compile *c);
1188
1189 void vir_dump(struct v3d_compile *c);
1190 void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
1191 void vir_dump_uniform(enum quniform_contents contents, uint32_t data);
1192
1193 void vir_validate(struct v3d_compile *c);
1194
1195 void vir_optimize(struct v3d_compile *c);
1196 bool vir_opt_algebraic(struct v3d_compile *c);
1197 bool vir_opt_constant_folding(struct v3d_compile *c);
1198 bool vir_opt_copy_propagate(struct v3d_compile *c);
1199 bool vir_opt_dead_code(struct v3d_compile *c);
1200 bool vir_opt_peephole_sf(struct v3d_compile *c);
1201 bool vir_opt_redundant_flags(struct v3d_compile *c);
1202 bool vir_opt_small_immediates(struct v3d_compile *c);
1203 bool vir_opt_vpm(struct v3d_compile *c);
1204 bool vir_opt_constant_alu(struct v3d_compile *c);
1205 bool v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
1206 bool v3d_nir_lower_line_smooth(nir_shader *shader);
1207 bool v3d_nir_lower_logic_ops(nir_shader *s, struct v3d_compile *c);
1208 bool v3d_nir_lower_scratch(nir_shader *s);
1209 bool v3d_nir_lower_txf_ms(nir_shader *s);
1210 bool v3d_nir_lower_image_load_store(nir_shader *s, struct v3d_compile *c);
1211 bool v3d_nir_lower_global_2x32(nir_shader *s);
1212 bool v3d_nir_lower_load_store_bitsize(nir_shader *s);
1213 bool v3d_nir_lower_algebraic(struct nir_shader *shader, const struct v3d_compile *c);
1214
1215 void v3d_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
1216 void v3d_vir_emit_image_load_store(struct v3d_compile *c,
1217 nir_intrinsic_instr *instr);
1218
1219 void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
1220 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
1221 void qpu_validate(struct v3d_compile *c);
1222 struct qpu_reg *v3d_register_allocate(struct v3d_compile *c);
1223 bool vir_init_reg_sets(struct v3d_compiler *compiler);
1224
1225 int v3d_shaderdb_dump(struct v3d_compile *c, char **shaderdb_str);
1226
1227 bool v3d_gl_format_is_return_32(enum pipe_format format);
1228
1229 uint32_t
1230 v3d_get_op_for_atomic_add(nir_intrinsic_instr *instr, unsigned src);
1231
1232 static inline bool
quniform_contents_is_texture_p0(enum quniform_contents contents)1233 quniform_contents_is_texture_p0(enum quniform_contents contents)
1234 {
1235 return (contents >= QUNIFORM_TEXTURE_CONFIG_P0_0 &&
1236 contents < (QUNIFORM_TEXTURE_CONFIG_P0_0 +
1237 V3D_MAX_TEXTURE_SAMPLERS));
1238 }
1239
1240 static inline bool
vir_in_nonuniform_control_flow(struct v3d_compile * c)1241 vir_in_nonuniform_control_flow(struct v3d_compile *c)
1242 {
1243 return c->execute.file != QFILE_NULL;
1244 }
1245
1246 static inline struct qreg
vir_uniform_ui(struct v3d_compile * c,uint32_t ui)1247 vir_uniform_ui(struct v3d_compile *c, uint32_t ui)
1248 {
1249 return vir_uniform(c, QUNIFORM_CONSTANT, ui);
1250 }
1251
1252 static inline struct qreg
vir_uniform_f(struct v3d_compile * c,float f)1253 vir_uniform_f(struct v3d_compile *c, float f)
1254 {
1255 return vir_uniform(c, QUNIFORM_CONSTANT, fui(f));
1256 }
1257
1258 #define VIR_ALU0(name, vir_inst, op) \
1259 static inline struct qreg \
1260 vir_##name(struct v3d_compile *c) \
1261 { \
1262 return vir_emit_def(c, vir_inst(op, c->undef, \
1263 c->undef, c->undef)); \
1264 } \
1265 static inline struct qinst * \
1266 vir_##name##_dest(struct v3d_compile *c, struct qreg dest) \
1267 { \
1268 return vir_emit_nondef(c, vir_inst(op, dest, \
1269 c->undef, c->undef)); \
1270 }
1271
1272 #define VIR_ALU1(name, vir_inst, op) \
1273 static inline struct qreg \
1274 vir_##name(struct v3d_compile *c, struct qreg a) \
1275 { \
1276 return vir_emit_def(c, vir_inst(op, c->undef, \
1277 a, c->undef)); \
1278 } \
1279 static inline struct qinst * \
1280 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
1281 struct qreg a) \
1282 { \
1283 return vir_emit_nondef(c, vir_inst(op, dest, a, \
1284 c->undef)); \
1285 }
1286
1287 #define VIR_ALU2(name, vir_inst, op) \
1288 static inline struct qreg \
1289 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
1290 { \
1291 return vir_emit_def(c, vir_inst(op, c->undef, a, b)); \
1292 } \
1293 static inline struct qinst * \
1294 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
1295 struct qreg a, struct qreg b) \
1296 { \
1297 return vir_emit_nondef(c, vir_inst(op, dest, a, b)); \
1298 }
1299
1300 #define VIR_NODST_0(name, vir_inst, op) \
1301 static inline struct qinst * \
1302 vir_##name(struct v3d_compile *c) \
1303 { \
1304 return vir_emit_nondef(c, vir_inst(op, c->undef, \
1305 c->undef, c->undef)); \
1306 }
1307
1308 #define VIR_NODST_1(name, vir_inst, op) \
1309 static inline struct qinst * \
1310 vir_##name(struct v3d_compile *c, struct qreg a) \
1311 { \
1312 return vir_emit_nondef(c, vir_inst(op, c->undef, \
1313 a, c->undef)); \
1314 }
1315
1316 #define VIR_NODST_2(name, vir_inst, op) \
1317 static inline struct qinst * \
1318 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
1319 { \
1320 return vir_emit_nondef(c, vir_inst(op, c->undef, \
1321 a, b)); \
1322 }
1323
1324 #define VIR_SFU(name) \
1325 static inline struct qreg \
1326 vir_##name(struct v3d_compile *c, struct qreg a) \
1327 { \
1328 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name, \
1329 c->undef, \
1330 a, c->undef)); \
1331 } \
1332 static inline struct qinst * \
1333 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
1334 struct qreg a) \
1335 { \
1336 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
1337 dest, \
1338 a, c->undef)); \
1339 }
1340
1341 #define VIR_SFU2(name) \
1342 static inline struct qreg \
1343 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
1344 { \
1345 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name, \
1346 c->undef, \
1347 a, b)); \
1348 } \
1349 static inline struct qinst * \
1350 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
1351 struct qreg a, struct qreg b) \
1352 { \
1353 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
1354 dest, \
1355 a, b)); \
1356 }
1357
1358 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
1359 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
1360 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
1361 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
1362 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
1363 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
1364 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
1365 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
1366 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
1367 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
1368 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
1369
1370 VIR_A_ALU2(FADD)
VIR_A_ALU2(VFPACK)1371 VIR_A_ALU2(VFPACK)
1372 VIR_A_ALU2(FSUB)
1373 VIR_A_ALU2(FMIN)
1374 VIR_A_ALU2(FMAX)
1375
1376 VIR_A_ALU2(ADD)
1377 VIR_A_ALU2(SUB)
1378 VIR_A_ALU2(SHL)
1379 VIR_A_ALU2(SHR)
1380 VIR_A_ALU2(ASR)
1381 VIR_A_ALU2(ROR)
1382 VIR_A_ALU2(MIN)
1383 VIR_A_ALU2(MAX)
1384 VIR_A_ALU2(UMIN)
1385 VIR_A_ALU2(UMAX)
1386 VIR_A_ALU2(AND)
1387 VIR_A_ALU2(OR)
1388 VIR_A_ALU2(XOR)
1389 VIR_A_ALU2(VADD)
1390 VIR_A_ALU2(VSUB)
1391 VIR_A_NODST_2(STVPMV)
1392 VIR_A_NODST_2(STVPMD)
1393 VIR_A_ALU1(NOT)
1394 VIR_A_ALU1(NEG)
1395 VIR_A_ALU1(FLAPUSH)
1396 VIR_A_ALU1(FLBPUSH)
1397 VIR_A_ALU1(FLPOP)
1398 VIR_A_ALU0(FLAFIRST)
1399 VIR_A_ALU0(FLNAFIRST)
1400 VIR_A_ALU1(SETMSF)
1401 VIR_A_ALU1(SETREVF)
1402 VIR_A_ALU0(TIDX)
1403 VIR_A_ALU0(EIDX)
1404 VIR_A_ALU1(LDVPMV_IN)
1405 VIR_A_ALU1(LDVPMV_OUT)
1406 VIR_A_ALU1(LDVPMD_IN)
1407 VIR_A_ALU1(LDVPMD_OUT)
1408 VIR_A_ALU2(LDVPMG_IN)
1409 VIR_A_ALU2(LDVPMG_OUT)
1410 VIR_A_ALU0(TMUWT)
1411
1412 VIR_A_ALU0(IID)
1413 VIR_A_ALU0(FXCD)
1414 VIR_A_ALU0(XCD)
1415 VIR_A_ALU0(FYCD)
1416 VIR_A_ALU0(YCD)
1417 VIR_A_ALU0(MSF)
1418 VIR_A_ALU0(REVF)
1419 VIR_A_ALU0(BARRIERID)
1420 VIR_A_ALU0(SAMPID)
1421 VIR_A_NODST_1(VPMSETUP)
1422 VIR_A_NODST_0(VPMWT)
1423 VIR_A_ALU2(FCMP)
1424 VIR_A_ALU2(VFMAX)
1425
1426 VIR_A_ALU1(FROUND)
1427 VIR_A_ALU1(FTOIN)
1428 VIR_A_ALU1(FTRUNC)
1429 VIR_A_ALU1(FTOIZ)
1430 VIR_A_ALU1(FFLOOR)
1431 VIR_A_ALU1(FTOUZ)
1432 VIR_A_ALU1(FCEIL)
1433 VIR_A_ALU1(FTOC)
1434
1435 VIR_A_ALU1(FDX)
1436 VIR_A_ALU1(FDY)
1437
1438 VIR_A_ALU1(ITOF)
1439 VIR_A_ALU1(CLZ)
1440 VIR_A_ALU1(UTOF)
1441
1442 VIR_M_ALU2(UMUL24)
1443 VIR_M_ALU2(FMUL)
1444 VIR_M_ALU2(SMUL24)
1445 VIR_M_NODST_2(MULTOP)
1446
1447 VIR_M_ALU1(MOV)
1448 VIR_M_ALU1(FMOV)
1449
1450 VIR_SFU(RECIP)
1451 VIR_SFU(RSQRT)
1452 VIR_SFU(EXP)
1453 VIR_SFU(LOG)
1454 VIR_SFU(SIN)
1455 VIR_SFU(RSQRT2)
1456
1457 VIR_SFU(BALLOT)
1458 VIR_SFU(BCASTF)
1459 VIR_SFU(ALLEQ)
1460 VIR_SFU(ALLFEQ)
1461 VIR_SFU2(ROTQ)
1462 VIR_SFU2(ROT)
1463 VIR_SFU2(SHUFFLE)
1464
1465 VIR_A_ALU2(VPACK)
1466 VIR_A_ALU2(V8PACK)
1467 VIR_A_ALU2(V10PACK)
1468 VIR_A_ALU2(V11FPACK)
1469
1470 VIR_M_ALU1(FTOUNORM16)
1471 VIR_M_ALU1(FTOSNORM16)
1472
1473 VIR_M_ALU1(VFTOUNORM8)
1474 VIR_M_ALU1(VFTOSNORM8)
1475
1476 VIR_M_ALU1(VFTOUNORM10LO)
1477 VIR_M_ALU1(VFTOUNORM10HI)
1478
1479 static inline struct qinst *
1480 vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
1481 struct qreg dest, struct qreg src)
1482 {
1483 struct qinst *mov = vir_MOV_dest(c, dest, src);
1484 vir_set_cond(mov, cond);
1485 return mov;
1486 }
1487
1488 static inline struct qreg
vir_SEL(struct v3d_compile * c,enum v3d_qpu_cond cond,struct qreg src0,struct qreg src1)1489 vir_SEL(struct v3d_compile *c, enum v3d_qpu_cond cond,
1490 struct qreg src0, struct qreg src1)
1491 {
1492 struct qreg t = vir_get_temp(c);
1493 vir_MOV_dest(c, t, src1);
1494 vir_MOV_cond(c, cond, t, src0);
1495 return t;
1496 }
1497
1498 static inline struct qinst *
vir_NOP(struct v3d_compile * c)1499 vir_NOP(struct v3d_compile *c)
1500 {
1501 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_NOP,
1502 c->undef, c->undef, c->undef));
1503 }
1504
1505 static inline struct qreg
vir_LDTMU(struct v3d_compile * c)1506 vir_LDTMU(struct v3d_compile *c)
1507 {
1508 struct qinst *ldtmu = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1509 c->undef, c->undef);
1510 ldtmu->qpu.sig.ldtmu = true;
1511
1512 return vir_emit_def(c, ldtmu);
1513 }
1514
1515 static inline struct qreg
vir_UMUL(struct v3d_compile * c,struct qreg src0,struct qreg src1)1516 vir_UMUL(struct v3d_compile *c, struct qreg src0, struct qreg src1)
1517 {
1518 vir_MULTOP(c, src0, src1);
1519 return vir_UMUL24(c, src0, src1);
1520 }
1521
1522 static inline struct qreg
vir_TLBU_COLOR_READ(struct v3d_compile * c,uint32_t config)1523 vir_TLBU_COLOR_READ(struct v3d_compile *c, uint32_t config)
1524 {
1525 assert((config & 0xffffff00) == 0xffffff00);
1526
1527 struct qinst *ldtlb = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1528 c->undef, c->undef);
1529 ldtlb->qpu.sig.ldtlbu = true;
1530 ldtlb->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT, config);
1531 return vir_emit_def(c, ldtlb);
1532 }
1533
1534 static inline struct qreg
vir_TLB_COLOR_READ(struct v3d_compile * c)1535 vir_TLB_COLOR_READ(struct v3d_compile *c)
1536 {
1537 struct qinst *ldtlb = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1538 c->undef, c->undef);
1539 ldtlb->qpu.sig.ldtlb = true;
1540 return vir_emit_def(c, ldtlb);
1541 }
1542
1543 static inline struct qinst *
vir_BRANCH(struct v3d_compile * c,enum v3d_qpu_branch_cond cond)1544 vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_branch_cond cond)
1545 {
1546 /* The actual uniform_data value will be set at scheduling time */
1547 return vir_emit_nondef(c, vir_branch_inst(c, cond));
1548 }
1549
1550 struct v3d_double_buffer_score {
1551 uint32_t geom;
1552 uint32_t render;
1553 };
1554
1555 void
1556 v3d_update_double_buffer_score(uint32_t vertex_count,
1557 uint32_t vs_qpu_size,
1558 uint32_t fs_qpu_size,
1559 struct v3d_prog_data *vs,
1560 struct v3d_prog_data *fs,
1561 struct v3d_double_buffer_score *score);
1562
1563 static inline bool
v3d_double_buffer_score_ok(struct v3d_double_buffer_score * score)1564 v3d_double_buffer_score_ok(struct v3d_double_buffer_score *score)
1565 {
1566 /* Double buffer decreases tile size, which increases
1567 * VS invocations so too much geometry is not good.
1568 */
1569 if (score->geom > 200000)
1570 return false;
1571
1572 /* We want enough rendering work to be able to hide
1573 * latency from tile stores.
1574 */
1575 if (score->render < 200)
1576 return false;
1577 return true;
1578 }
1579
1580 #define vir_for_each_block(block, c) \
1581 list_for_each_entry(struct qblock, block, &c->blocks, link)
1582
1583 #define vir_for_each_block_rev(block, c) \
1584 list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
1585
1586 /* Loop over the non-NULL members of the successors array. */
1587 #define vir_for_each_successor(succ, block) \
1588 for (struct qblock *succ = block->successors[0]; \
1589 succ != NULL; \
1590 succ = (succ == block->successors[1] ? NULL : \
1591 block->successors[1]))
1592
1593 #define vir_for_each_inst(inst, block) \
1594 list_for_each_entry(struct qinst, inst, &block->instructions, link)
1595
1596 #define vir_for_each_inst_rev(inst, block) \
1597 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
1598
1599 #define vir_for_each_inst_safe(inst, block) \
1600 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
1601
1602 #define vir_for_each_inst_inorder(inst, c) \
1603 vir_for_each_block(_block, c) \
1604 vir_for_each_inst(inst, _block)
1605
1606 #define vir_for_each_inst_inorder_safe(inst, c) \
1607 vir_for_each_block(_block, c) \
1608 vir_for_each_inst_safe(inst, _block)
1609
1610 #endif /* V3D_COMPILER_H */
1611