1 /* 2 * Copyright 2022-2023 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #ifndef PLATFORM_DEF_H 7 #define PLATFORM_DEF_H 8 9 #include <lib/utils_def.h> 10 #include <lib/xlat_tables/xlat_tables_v2.h> 11 12 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 13 #define PLATFORM_LINKER_ARCH aarch64 14 15 #define PLATFORM_STACK_SIZE 0xB00 16 #define CACHE_WRITEBACK_GRANULE 64 17 18 #define PLAT_PRIMARY_CPU U(0x0) 19 #define PLATFORM_MAX_CPU_PER_CLUSTER U(2) 20 #define PLATFORM_CLUSTER_COUNT U(1) 21 #define PLATFORM_CLUSTER0_CORE_COUNT U(2) 22 #define PLATFORM_CORE_COUNT U(2) 23 24 #define IMX_PWR_LVL0 MPIDR_AFFLVL0 25 26 #define PWR_DOMAIN_AT_MAX_LVL U(1) 27 #define PLAT_MAX_PWR_LVL U(2) 28 #define PLAT_MAX_OFF_STATE U(4) 29 #define PLAT_MAX_RET_STATE U(2) 30 31 #define BL31_BASE U(0x204E0000) 32 #define BL31_LIMIT U(0x20520000) 33 34 #define OCRAM_BASE U(0x20480000) 35 #define OCRAM_SIZE U(0xA0000) 36 37 /* non-secure uboot base */ 38 /* TODO */ 39 #define PLAT_NS_IMAGE_OFFSET U(0x80200000) 40 #define BL32_FDT_OVERLAY_ADDR (PLAT_NS_IMAGE_OFFSET + 0x3000000) 41 42 /* GICv4 base address */ 43 #define PLAT_GICD_BASE U(0x48000000) 44 #define PLAT_GICR_BASE U(0x48040000) 45 46 #define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32) 47 #define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32) 48 49 #define MAX_XLAT_TABLES 8 50 #define MAX_MMAP_REGIONS 16 51 52 #define IMX_LPUART_BASE U(0x44380000) 53 #define IMX_BOOT_UART_CLK_IN_HZ U(24000000) /* Select 24MHz oscillator */ 54 #define IMX_CONSOLE_BAUDRATE 115200 55 56 #define AIPSx_SIZE U(0x800000) 57 #define AIPS1_BASE U(0x44000000) 58 #define AIPS2_BASE U(0x42000000) 59 #define AIPS3_BASE U(0x42800000) 60 #define AIPS4_BASE U(0x49000000) 61 #define GPIO1_BASE U(0x47400000) 62 #define GPIO2_BASE U(0x43810000) 63 #define GPIO3_BASE U(0x43820000) 64 #define GPIO4_BASE U(0x43830000) 65 66 #define TRDC_A_BASE U(0x44270000) 67 #define TRDC_W_BASE U(0x42460000) 68 #define TRDC_M_BASE U(0x42810000) 69 #define TRDC_N_BASE U(0x49010000) 70 #define TRDC_x_SISE U(0x20000) 71 72 #define WDOG3_BASE U(0x42490000) 73 #define WDOG_CS U(0x0) 74 #define WDOG_CS_ULK BIT(11) 75 #define WDOG_CNT U(0x4) 76 #define WDOG_TOVAL U(0x8) 77 78 #define BBNSM_BASE U(0x44440000) 79 #define BBNSM_CTRL U(0x8) 80 #define BBNSM_DP_EN BIT(24) 81 #define BBNSM_TOSP BIT(25) 82 83 #define SRC_BASE U(0x44460000) 84 #define GPC_BASE U(0x44470000) 85 #define BLK_CTRL_S_BASE U(0x444F0000) 86 #define S400_MU_BASE U(0x47520000) 87 88 /* system memory map define */ 89 #define AIPS2_MAP MAP_REGION_FLAT(AIPS2_BASE, AIPSx_SIZE, MT_DEVICE | MT_RW | MT_NS) 90 #define AIPS1_MAP MAP_REGION_FLAT(AIPS1_BASE, AIPSx_SIZE, MT_DEVICE | MT_RW) 91 #define AIPS4_MAP MAP_REGION_FLAT(AIPS4_BASE, AIPSx_SIZE, MT_DEVICE | MT_RW | MT_NS) 92 #define GIC_MAP MAP_REGION_FLAT(PLAT_GICD_BASE, 0x200000, MT_DEVICE | MT_RW) 93 #define TRDC_A_MAP MAP_REGION_FLAT(TRDC_A_BASE, TRDC_x_SISE, MT_DEVICE | MT_RW) 94 #define TRDC_W_MAP MAP_REGION_FLAT(TRDC_W_BASE, TRDC_x_SISE, MT_DEVICE | MT_RW) 95 #define TRDC_M_MAP MAP_REGION_FLAT(TRDC_M_BASE, TRDC_x_SISE, MT_DEVICE | MT_RW) 96 #define TRDC_N_MAP MAP_REGION_FLAT(TRDC_N_BASE, TRDC_x_SISE, MT_DEVICE | MT_RW) 97 98 #define COUNTER_FREQUENCY 24000000 99 100 #endif /* platform_def.h */ 101