1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2024 Advanced Micro Devices, Inc. All rights reserved. 5 * SPDX-License-Identifier: MIT 6 * 7 ***********************************************************************************************************************/ 8 9 /** 10 **************************************************************************************************** 11 * @file addrlib.h 12 * @brief Contains the Addr::Lib base class definition. 13 **************************************************************************************************** 14 */ 15 16 #ifndef __ADDR_LIB_H__ 17 #define __ADDR_LIB_H__ 18 19 #include "addrinterface.h" 20 #include "addrtypes.h" 21 #include "addrobject.h" 22 #include "addrelemlib.h" 23 24 #include "amdgpu_asic_addr.h" 25 26 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND 27 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A 28 #endif 29 30 #ifndef CIASICIDGFXENGINE_ARCTICISLAND 31 #define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D 32 #endif 33 34 namespace Addr 35 { 36 37 /** 38 **************************************************************************************************** 39 * @brief Neutral enums that define pipeinterleave 40 **************************************************************************************************** 41 */ 42 enum PipeInterleave 43 { 44 ADDR_PIPEINTERLEAVE_256B = 256, 45 ADDR_PIPEINTERLEAVE_512B = 512, 46 ADDR_PIPEINTERLEAVE_1KB = 1024, 47 ADDR_PIPEINTERLEAVE_2KB = 2048, 48 }; 49 50 /** 51 **************************************************************************************************** 52 * @brief Neutral enums that define DRAM row size 53 **************************************************************************************************** 54 */ 55 enum RowSize 56 { 57 ADDR_ROWSIZE_1KB = 1024, 58 ADDR_ROWSIZE_2KB = 2048, 59 ADDR_ROWSIZE_4KB = 4096, 60 ADDR_ROWSIZE_8KB = 8192, 61 }; 62 63 /** 64 **************************************************************************************************** 65 * @brief Neutral enums that define bank interleave 66 **************************************************************************************************** 67 */ 68 enum BankInterleave 69 { 70 ADDR_BANKINTERLEAVE_1 = 1, 71 ADDR_BANKINTERLEAVE_2 = 2, 72 ADDR_BANKINTERLEAVE_4 = 4, 73 ADDR_BANKINTERLEAVE_8 = 8, 74 }; 75 76 /** 77 **************************************************************************************************** 78 * @brief Neutral enums that define shader engine tile size 79 **************************************************************************************************** 80 */ 81 enum ShaderEngineTileSize 82 { 83 ADDR_SE_TILESIZE_16 = 16, 84 ADDR_SE_TILESIZE_32 = 32, 85 }; 86 87 /** 88 **************************************************************************************************** 89 * @brief Neutral enums that define bank swap size 90 **************************************************************************************************** 91 */ 92 enum BankSwapSize 93 { 94 ADDR_BANKSWAP_128B = 128, 95 ADDR_BANKSWAP_256B = 256, 96 ADDR_BANKSWAP_512B = 512, 97 ADDR_BANKSWAP_1KB = 1024, 98 }; 99 100 /** 101 **************************************************************************************************** 102 * @brief Enums that define max compressed fragments config 103 **************************************************************************************************** 104 */ 105 enum NumMaxCompressedFragmentsConfig 106 { 107 ADDR_CONFIG_1_MAX_COMPRESSED_FRAGMENTS = 0x00000000, 108 ADDR_CONFIG_2_MAX_COMPRESSED_FRAGMENTS = 0x00000001, 109 ADDR_CONFIG_4_MAX_COMPRESSED_FRAGMENTS = 0x00000002, 110 ADDR_CONFIG_8_MAX_COMPRESSED_FRAGMENTS = 0x00000003, 111 }; 112 113 /** 114 **************************************************************************************************** 115 * @brief Enums that define num pipes config 116 **************************************************************************************************** 117 */ 118 enum NumPipesConfig 119 { 120 ADDR_CONFIG_1_PIPE = 0x00000000, 121 ADDR_CONFIG_2_PIPE = 0x00000001, 122 ADDR_CONFIG_4_PIPE = 0x00000002, 123 ADDR_CONFIG_8_PIPE = 0x00000003, 124 ADDR_CONFIG_16_PIPE = 0x00000004, 125 ADDR_CONFIG_32_PIPE = 0x00000005, 126 ADDR_CONFIG_64_PIPE = 0x00000006, 127 }; 128 129 /** 130 **************************************************************************************************** 131 * @brief Enums that define num banks config 132 **************************************************************************************************** 133 */ 134 enum NumBanksConfig 135 { 136 ADDR_CONFIG_1_BANK = 0x00000000, 137 ADDR_CONFIG_2_BANK = 0x00000001, 138 ADDR_CONFIG_4_BANK = 0x00000002, 139 ADDR_CONFIG_8_BANK = 0x00000003, 140 ADDR_CONFIG_16_BANK = 0x00000004, 141 }; 142 143 /** 144 **************************************************************************************************** 145 * @brief Enums that define num rb per shader engine config 146 **************************************************************************************************** 147 */ 148 enum NumRbPerShaderEngineConfig 149 { 150 ADDR_CONFIG_1_RB_PER_SHADER_ENGINE = 0x00000000, 151 ADDR_CONFIG_2_RB_PER_SHADER_ENGINE = 0x00000001, 152 ADDR_CONFIG_4_RB_PER_SHADER_ENGINE = 0x00000002, 153 }; 154 155 /** 156 **************************************************************************************************** 157 * @brief Enums that define num shader engines config 158 **************************************************************************************************** 159 */ 160 enum NumShaderEnginesConfig 161 { 162 ADDR_CONFIG_1_SHADER_ENGINE = 0x00000000, 163 ADDR_CONFIG_2_SHADER_ENGINE = 0x00000001, 164 ADDR_CONFIG_4_SHADER_ENGINE = 0x00000002, 165 ADDR_CONFIG_8_SHADER_ENGINE = 0x00000003, 166 }; 167 168 /** 169 **************************************************************************************************** 170 * @brief Enums that define pipe interleave size config 171 **************************************************************************************************** 172 */ 173 enum PipeInterleaveSizeConfig 174 { 175 ADDR_CONFIG_PIPE_INTERLEAVE_256B = 0x00000000, 176 ADDR_CONFIG_PIPE_INTERLEAVE_512B = 0x00000001, 177 ADDR_CONFIG_PIPE_INTERLEAVE_1KB = 0x00000002, 178 ADDR_CONFIG_PIPE_INTERLEAVE_2KB = 0x00000003, 179 }; 180 181 /** 182 **************************************************************************************************** 183 * @brief Enums that define row size config 184 **************************************************************************************************** 185 */ 186 enum RowSizeConfig 187 { 188 ADDR_CONFIG_1KB_ROW = 0x00000000, 189 ADDR_CONFIG_2KB_ROW = 0x00000001, 190 ADDR_CONFIG_4KB_ROW = 0x00000002, 191 }; 192 193 /** 194 **************************************************************************************************** 195 * @brief Enums that define bank interleave size config 196 **************************************************************************************************** 197 */ 198 enum BankInterleaveSizeConfig 199 { 200 ADDR_CONFIG_BANK_INTERLEAVE_1 = 0x00000000, 201 ADDR_CONFIG_BANK_INTERLEAVE_2 = 0x00000001, 202 ADDR_CONFIG_BANK_INTERLEAVE_4 = 0x00000002, 203 ADDR_CONFIG_BANK_INTERLEAVE_8 = 0x00000003, 204 }; 205 206 /** 207 **************************************************************************************************** 208 * @brief Enums that define engine tile size config 209 **************************************************************************************************** 210 */ 211 enum ShaderEngineTileSizeConfig 212 { 213 ADDR_CONFIG_SE_TILE_16 = 0x00000000, 214 ADDR_CONFIG_SE_TILE_32 = 0x00000001, 215 }; 216 217 /** 218 ************************************************************************************************************************ 219 * @brief Bit setting for swizzle pattern 220 ************************************************************************************************************************ 221 */ 222 union ADDR_BIT_SETTING 223 { 224 struct 225 { 226 UINT_16 x; 227 UINT_16 y; 228 UINT_16 z; 229 UINT_16 s; 230 }; 231 UINT_64 value; 232 }; 233 234 /** 235 ************************************************************************************************************************ 236 * InitBit 237 * 238 * @brief 239 * Initialize bit setting value via a return value 240 ************************************************************************************************************************ 241 */ 242 #define InitBit(c, index) (1ull << ((c << 4) + index)) 243 244 const UINT_64 X0 = InitBit(0, 0); 245 const UINT_64 X1 = InitBit(0, 1); 246 const UINT_64 X2 = InitBit(0, 2); 247 const UINT_64 X3 = InitBit(0, 3); 248 const UINT_64 X4 = InitBit(0, 4); 249 const UINT_64 X5 = InitBit(0, 5); 250 const UINT_64 X6 = InitBit(0, 6); 251 const UINT_64 X7 = InitBit(0, 7); 252 const UINT_64 X8 = InitBit(0, 8); 253 const UINT_64 X9 = InitBit(0, 9); 254 const UINT_64 X10 = InitBit(0, 10); 255 const UINT_64 X11 = InitBit(0, 11); 256 257 const UINT_64 Y0 = InitBit(1, 0); 258 const UINT_64 Y1 = InitBit(1, 1); 259 const UINT_64 Y2 = InitBit(1, 2); 260 const UINT_64 Y3 = InitBit(1, 3); 261 const UINT_64 Y4 = InitBit(1, 4); 262 const UINT_64 Y5 = InitBit(1, 5); 263 const UINT_64 Y6 = InitBit(1, 6); 264 const UINT_64 Y7 = InitBit(1, 7); 265 const UINT_64 Y8 = InitBit(1, 8); 266 const UINT_64 Y9 = InitBit(1, 9); 267 const UINT_64 Y10 = InitBit(1, 10); 268 const UINT_64 Y11 = InitBit(1, 11); 269 270 const UINT_64 Z0 = InitBit(2, 0); 271 const UINT_64 Z1 = InitBit(2, 1); 272 const UINT_64 Z2 = InitBit(2, 2); 273 const UINT_64 Z3 = InitBit(2, 3); 274 const UINT_64 Z4 = InitBit(2, 4); 275 const UINT_64 Z5 = InitBit(2, 5); 276 const UINT_64 Z6 = InitBit(2, 6); 277 const UINT_64 Z7 = InitBit(2, 7); 278 const UINT_64 Z8 = InitBit(2, 8); 279 280 const UINT_64 S0 = InitBit(3, 0); 281 const UINT_64 S1 = InitBit(3, 1); 282 const UINT_64 S2 = InitBit(3, 2); 283 284 /** 285 **************************************************************************************************** 286 * @brief This class contains asic independent address lib functionalities 287 **************************************************************************************************** 288 */ 289 class Lib : public Object 290 { 291 public: 292 virtual ~Lib(); 293 294 static ADDR_E_RETURNCODE Create( 295 const ADDR_CREATE_INPUT* pCreateInfo, ADDR_CREATE_OUTPUT* pCreateOut); 296 297 /// Pair of Create Destroy()298 VOID Destroy() 299 { 300 delete this; 301 } 302 303 static Lib* GetLib(ADDR_HANDLE hLib); 304 305 /// Returns which version of addrlib functions should be used. 306 virtual UINT_32 GetInterfaceVersion() const = 0; 307 308 /// Returns AddrLib version (from compiled binary instead include file) GetVersion()309 UINT_32 GetVersion() 310 { 311 return m_version; 312 } 313 314 /// Returns asic chip family name defined by AddrLib GetChipFamily()315 ChipFamily GetChipFamily() const 316 { 317 return m_chipFamily; 318 } 319 320 ADDR_E_RETURNCODE Flt32ToDepthPixel( 321 const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn, 322 ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut) const; 323 324 ADDR_E_RETURNCODE Flt32ToColorPixel( 325 const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn, 326 ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut) const; 327 328 BOOL_32 GetExportNorm(const ELEM_GETEXPORTNORM_INPUT* pIn) const; 329 330 ADDR_E_RETURNCODE GetMaxAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const; 331 332 ADDR_E_RETURNCODE GetMaxMetaAlignments(ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut) const; 333 334 UINT_32 GetBpe(AddrFormat format) const; 335 336 337 static UINT_32 ComputeOffsetFromSwizzlePattern( 338 const UINT_64* pPattern, 339 UINT_32 numBits, 340 UINT_32 x, 341 UINT_32 y, 342 UINT_32 z, 343 UINT_32 s); 344 345 protected: 346 Lib(); // Constructor is protected 347 Lib(const Client* pClient); 348 349 /// Pure virtual function to get max base alignments 350 virtual UINT_32 HwlComputeMaxBaseAlignments() const = 0; 351 352 /// Gets maximum alignements for metadata HwlComputeMaxMetaBaseAlignments()353 virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const 354 { 355 ADDR_NOT_IMPLEMENTED(); 356 357 return 0; 358 } 359 ValidBaseAlignments(UINT_32 alignment)360 VOID ValidBaseAlignments(UINT_32 alignment) const 361 { 362 #if DEBUG 363 ADDR_ASSERT(alignment <= m_maxBaseAlign); 364 #endif 365 } 366 ValidMetaBaseAlignments(UINT_32 metaAlignment)367 VOID ValidMetaBaseAlignments(UINT_32 metaAlignment) const 368 { 369 #if DEBUG 370 ADDR_ASSERT(metaAlignment <= m_maxMetaBaseAlign); 371 #endif 372 } 373 IsTex1d(AddrResourceType resourceType)374 static BOOL_32 IsTex1d(AddrResourceType resourceType) 375 { 376 return (resourceType == ADDR_RSRC_TEX_1D); 377 } 378 IsTex2d(AddrResourceType resourceType)379 static BOOL_32 IsTex2d(AddrResourceType resourceType) 380 { 381 return (resourceType == ADDR_RSRC_TEX_2D); 382 } 383 IsTex3d(AddrResourceType resourceType)384 static BOOL_32 IsTex3d(AddrResourceType resourceType) 385 { 386 return (resourceType == ADDR_RSRC_TEX_3D); 387 } 388 389 // 390 // Initialization 391 // 392 /// Pure Virtual function for Hwl computing internal global parameters from h/w registers 393 virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn) = 0; 394 395 /// Pure Virtual function for Hwl converting chip family 396 virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision) = 0; 397 398 /// Get equation table pointer and number of equations HwlGetEquationTableInfo(const ADDR_EQUATION ** ppEquationTable)399 virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const 400 { 401 *ppEquationTable = NULL; 402 403 return 0; 404 } 405 406 // 407 // Misc helper 408 // 409 static UINT_32 Bits2Number(UINT_32 bitNum, ...); 410 GetNumFragments(UINT_32 numSamples,UINT_32 numFrags)411 static UINT_32 GetNumFragments(UINT_32 numSamples, UINT_32 numFrags) 412 { 413 return (numFrags != 0) ? numFrags : Max(1u, numSamples); 414 } 415 416 /// Returns pointer of ElemLib GetElemLib()417 ElemLib* GetElemLib() const 418 { 419 return m_pElemLib; 420 } 421 422 /// Returns fillSizeFields flag GetFillSizeFieldsFlags()423 UINT_32 GetFillSizeFieldsFlags() const 424 { 425 return m_configFlags.fillSizeFields; 426 } 427 428 private: 429 // Disallow the copy constructor 430 Lib(const Lib& a); 431 432 // Disallow the assignment operator 433 Lib& operator=(const Lib& a); 434 435 VOID SetChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision); 436 437 VOID SetMinPitchAlignPixels(UINT_32 minPitchAlignPixels); 438 439 VOID SetMaxAlignments(); 440 441 protected: 442 ChipFamily m_chipFamily; ///< Chip family translated from the one in atiid.h 443 444 UINT_32 m_chipRevision; ///< Revision id from xxx_id.h 445 446 UINT_32 m_version; ///< Current version 447 448 // 449 // Global parameters 450 // 451 ConfigFlags m_configFlags; ///< Global configuration flags. Note this is setup by 452 /// AddrLib instead of Client except forceLinearAligned 453 454 UINT_32 m_pipes; ///< Number of pipes 455 UINT_32 m_banks; ///< Number of banks 456 /// For r800 this is MC_ARB_RAMCFG.NOOFBANK 457 /// Keep it here to do default parameter calculation 458 459 UINT_32 m_pipeInterleaveBytes; 460 ///< Specifies the size of contiguous address space 461 /// within each tiling pipe when making linear 462 /// accesses. (Formerly Group Size) 463 464 UINT_32 m_rowSize; ///< DRAM row size, in bytes 465 466 UINT_32 m_minPitchAlignPixels; ///< Minimum pitch alignment in pixels 467 UINT_32 m_maxSamples; ///< Max numSamples 468 469 UINT_32 m_maxBaseAlign; ///< Max base alignment for data surface 470 UINT_32 m_maxMetaBaseAlign; ///< Max base alignment for metadata 471 472 private: 473 ElemLib* m_pElemLib; ///< Element Lib pointer 474 }; 475 476 Lib* SiHwlInit (const Client* pClient); 477 Lib* CiHwlInit (const Client* pClient); 478 Lib* Gfx9HwlInit (const Client* pClient); 479 Lib* Gfx10HwlInit(const Client* pClient); 480 Lib* Gfx11HwlInit(const Client* pClient); 481 Lib* Gfx12HwlInit(const Client* pClient); 482 } // Addr 483 484 #endif 485