| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FixupSetCC.cpp | 105 Register ZeroReg = MRI->createVirtualRegister(RC); in runOnMachineFunction() local
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| D | X86FlagsCopyLowering.cpp | 1054 Register ZeroReg = MRI->createVirtualRegister(&X86::GR32RegClass); in rewriteSetCarryExtended() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| D | X86FixupSetCC.cpp | 114 Register ZeroReg = MRI->createVirtualRegister(RC); in runOnMachineFunction() local
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| /external/llvm/lib/Target/X86/ |
| D | X86FixupSetCC.cpp | 163 unsigned ZeroReg = MRI->createVirtualRegister(RC); in runOnMachineFunction() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 2851 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine()
2880 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL()
3438 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
3482 unsigned SubOpc, ZeroReg; in genAlternativeCodeSequence() local
3530 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
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| D | AArch64ExpandPseudoInsts.cpp | 599 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, in expandCMP_SWAP()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 2480 unsigned Opcode, unsigned ZeroReg, in copyGPRRegTuple()
3669 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine()
3698 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL()
3760 MachineCombinerPattern Pattern) { in getMaddPatterns()
4414 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
4458 unsigned SubOpc, ZeroReg; in genAlternativeCodeSequence() local
4506 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
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| D | AArch64ExpandPseudoInsts.cpp | 176 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, in expandCMP_SWAP()
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 3454 unsigned Opcode, unsigned ZeroReg, in copyGPRRegTuple()
4899 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine()
4932 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL()
5074 MachineCombinerPattern Pattern) { in getMaddPatterns()
5932 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
5994 unsigned SubOpc, ZeroReg; in genAlternativeCodeSequence() local
6042 unsigned BitSize, OrrOpc, ZeroReg; in genAlternativeCodeSequence() local
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| D | AArch64ExpandPseudoInsts.cpp | 190 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, in expandCMP_SWAP()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 83 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
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| D | MipsAsmPrinter.cpp | 122 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in emitPseudoIndirectBranch() local
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| D | MipsSEISelDAGToDAG.cpp | 89 unsigned DstReg = 0, ZeroReg = 0; in replaceUsesWithZeroReg() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 87 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
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| D | MipsAsmPrinter.cpp | 144 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in emitPseudoIndirectBranch() local
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| D | MipsSEISelDAGToDAG.cpp | 85 unsigned DstReg = 0, ZeroReg = 0; in replaceUsesWithZeroReg() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | InstructionSelectorImpl.h | 798 int64_t ZeroReg = MatchTable[CurrentIdx++]; in executeMatchTable() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 87 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
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| D | MipsAsmPrinter.cpp | 140 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in emitPseudoIndirectBranch() local
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| D | MipsSEISelDAGToDAG.cpp | 85 unsigned DstReg = 0, ZeroReg = 0; in replaceUsesWithZeroReg() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | InstructionSelectorImpl.h | 892 int64_t ZeroReg = MatchTable[CurrentIdx++]; in executeMatchTable() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 900 SDValue ZeroReg = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8); in LowerINLINEASM() local
1872 Register ZeroReg = MRI.createVirtualRegister(&AVR::GPR8RegClass); in insertMultibyteShift() local
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| /external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 550 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectCmp() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 552 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectCmp() local
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 1263 unsigned ZeroReg; in FoldImmediate() local
|