1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 /* 4 * This file is created based on MT8186 Functional Specification 5 * Chapter number: 3.5 6 */ 7 8 #ifndef SOC_MEDIATEK_MT8186_SPM_H 9 #define SOC_MEDIATEK_MT8186_SPM_H 10 11 #include <device/mmio.h> 12 #include <soc/addressmap.h> 13 #include <soc/mtcmos.h> 14 #include <soc/spm_common.h> 15 #include <types.h> 16 17 #define SPM_INIT_DONE_US 20 18 19 #define CLK_SCP_CFG_0 (IO_PHYS + 0x200) 20 #define CLK_SCP_CFG_1 (IO_PHYS + 0x210) 21 #define INFRA_AO_RES_CTRL_MASK (INFRACFG_AO_BASE + 0xB8) 22 23 #define AP_PLL_CON3 (APMIXED_BASE + 0xC) 24 #define AP_PLL_CON4 (APMIXED_BASE + 0x10) 25 26 /* MD32PCM setting for SPM code fetch */ 27 #define MD32PCM_CFGREG_SW_RSTN_RUN 1 28 #define MD32PCM_DMA0_CON_VAL 0x0003820E 29 #define MD32PCM_DMA0_START_VAL 0x00008000 30 31 /* SPM */ 32 #define BCLK_CG_EN_LSB BIT(0) 33 #define PCM_CK_EN_LSB BIT(2) 34 #define PCM_SW_RESET_LSB BIT(15) 35 #define RG_AHBMIF_APBEN_LSB BIT(3) 36 #define REG_MD32_APB_INTERNAL_EN_LSB BIT(14) 37 #define PCM_RF_SYNC_R7 BIT(23) 38 #define REG_DDREN_DBC_EN_LSB BIT(16) 39 40 DEFINE_BIT(MD32PCM_CFGREG_SW_RSTN_RESET, 0) 41 DEFINE_BIT(REG_SYSCLK1_SRC_MD2_SRCCLKENA, 28) 42 DEFINE_BIT(SPM_ACK_CHK_3_CON_CLR_ALL, 1) 43 DEFINE_BIT(SPM_ACK_CHK_3_CON_EN_0, 4) 44 DEFINE_BIT(SPM_ACK_CHK_3_CON_EN_1, 8) 45 DEFINE_BIT(SPM_ACK_CHK_3_CON_HW_MODE_TRIG_0, 9) 46 DEFINE_BIT(SPM_ACK_CHK_3_CON_HW_MODE_TRIG_1, 10) 47 DEFINE_BIT(INFRA_AO_RES_CTRL_MASK_EMI_IDLE, 18) 48 DEFINE_BIT(INFRA_AO_RES_CTRL_MASK_MPU_IDLE, 15) 49 DEFINE_BIT(SPM_DVFS_FORCE_ENABLE_LSB, 2) 50 DEFINE_BIT(SPM_DVFSRC_ENABLE_LSB, 4) 51 DEFINE_BIT(SYS_TIMER_START_EN_LSB, 0) 52 53 #define SPM_PROJECT_CODE 0xB16 54 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) 55 #define POWER_ON_VAL1_DEF 0x80015860 56 #define SPM_WAKEUP_EVENT_MASK_DEF 0xEFFFFFFF 57 #define DDREN_DBC_EN_VAL 0x154 58 #define ARMPLL_CLK_SEL_DEF 0x3FF 59 #define SPM_RESOURCE_ACK_CON0_DEF 0x00000000 60 #define SPM_RESOURCE_ACK_CON1_DEF 0x00000000 61 #define SPM_RESOURCE_ACK_CON2_DEF 0xCCCC4E4E 62 #define SPM_RESOURCE_ACK_CON3_DEF 0x00000000 63 #define APMIX_CON3_DEF 0xFFFF7770 64 #define APMIX_CON4_DEF 0xFFFAA007 65 #define SCP_CFG0_DEF 0x3FF 66 #define SCP_CFG1_DEF 0x3 67 #define SPM_DVFS_LEVEL_DEF 0x00000001 68 #define SPM_DVS_DFS_LEVEL_DEF 0x00010001 69 #define SPM_ACK_CHK_3_SEL_HW_S1 0x0035009F 70 #define SPM_ACK_CHK_3_HW_S1_CNT 1 71 #define SPM_SYSCLK_SETTLE 0x60FE /* 1685us */ 72 #define SPM_WAKEUP_EVENT_MASK_BIT0 1 73 #define RG_PCM_TIMER_EN_LSB BIT(5) 74 #define RG_PCM_WDT_WAKE_LSB BIT(9) 75 #define PCM_RF_SYNC_R0 BIT(16) 76 #define REG_SPM_EVENT_COUNTER_CLR_LSB BIT(6) 77 #define R12_CSYSPWREQ_B BIT(24) 78 #define SPM_BUS_PROTECT_MASK_B_DEF 0xFFFFFFFF 79 #define SPM_BUS_PROTECT2_MASK_B_DEF 0xFFFFFFFF 80 81 #define SPM_FLAG_DISABLE_VCORE_DVS BIT(3) 82 #define SPM_FLAG_DISABLE_VCORE_DFS BIT(4) 83 #define SPM_FLAG_RUN_COMMON_SCENARIO BIT(10) 84 85 /* PCM_WDT_VAL */ 86 #define PCM_WDT_TIMEOUT (30 * 32768) /* 30s */ 87 /* PCM_TIMER_VAL */ 88 #define PCM_TIMER_MAX (0xffffffff - PCM_WDT_TIMEOUT) 89 90 /* SPM_IRQ_MASK */ 91 #define ISRM_TWAM BIT(2) 92 #define ISRM_PCM_RETURN BIT(3) 93 #define ISRM_RET_IRQ0 BIT(8) 94 #define ISRM_RET_IRQ1 BIT(9) 95 #define ISRM_RET_IRQ2 BIT(10) 96 #define ISRM_RET_IRQ3 BIT(11) 97 #define ISRM_RET_IRQ4 BIT(12) 98 #define ISRM_RET_IRQ5 BIT(13) 99 #define ISRM_RET_IRQ6 BIT(14) 100 #define ISRM_RET_IRQ7 BIT(15) 101 #define ISRM_RET_IRQ8 BIT(16) 102 #define ISRM_RET_IRQ9 BIT(17) 103 #define ISRM_RET_IRQ_AUX (ISRM_RET_IRQ9 | ISRM_RET_IRQ8 | ISRM_RET_IRQ7 | \ 104 ISRM_RET_IRQ6 | ISRM_RET_IRQ5 | ISRM_RET_IRQ4 | \ 105 ISRM_RET_IRQ3 | ISRM_RET_IRQ2 | ISRM_RET_IRQ1) 106 #define ISRM_ALL_EXC_TWAM ISRM_RET_IRQ_AUX 107 #define ISRM_ALL (ISRM_ALL_EXC_TWAM | ISRM_TWAM) 108 109 /* SPM_IRQ_STA */ 110 #define ISRS_TWAM BIT(2) 111 #define ISRS_PCM_RETURN BIT(3) 112 #define ISRC_TWAM ISRS_TWAM 113 #define ISRC_ALL_EXC_TWAM ISRS_PCM_RETURN 114 #define ISRC_ALL (ISRC_ALL_EXC_TWAM | ISRC_TWAM) 115 116 /* SPM_SWINT */ 117 #define PCM_SW_INT0 BIT(0) 118 #define PCM_SW_INT1 BIT(1) 119 #define PCM_SW_INT2 BIT(2) 120 #define PCM_SW_INT3 BIT(3) 121 #define PCM_SW_INT4 BIT(4) 122 #define PCM_SW_INT5 BIT(5) 123 #define PCM_SW_INT6 BIT(6) 124 #define PCM_SW_INT7 BIT(7) 125 #define PCM_SW_INT8 BIT(8) 126 #define PCM_SW_INT9 BIT(9) 127 #define PCM_SW_INT_ALL (PCM_SW_INT9 | PCM_SW_INT8 | PCM_SW_INT7 | \ 128 PCM_SW_INT6 | PCM_SW_INT5 | PCM_SW_INT4 | \ 129 PCM_SW_INT3 | PCM_SW_INT2 | PCM_SW_INT1 | \ 130 PCM_SW_INT0) 131 132 struct mtk_spm_regs { 133 uint32_t poweron_config_set; 134 uint32_t spm_power_on_val0; 135 uint32_t spm_power_on_val1; 136 uint32_t spm_clk_con; 137 uint32_t spm_clk_settle; 138 uint32_t spm_ap_standby_con; 139 uint32_t pcm_con0; 140 uint32_t pcm_con1; 141 uint32_t spm_power_on_val2; 142 uint32_t spm_power_on_val3; 143 uint32_t pcm_reg_data_ini; 144 uint32_t pcm_pwr_io_en; 145 uint32_t pcm_timer_val; 146 uint32_t pcm_wdt_val; 147 uint8_t reserved0[8]; 148 uint32_t spm_sw_rst_con; 149 uint32_t spm_sw_rst_con_set; 150 uint32_t spm_sw_rst_con_clr; 151 uint32_t spm_src6_mask; 152 uint8_t reserved1[52]; 153 uint32_t md32_clk_con; 154 uint32_t spm_sram_rsv_con; 155 uint32_t spm_swint; 156 uint32_t spm_swint_set; 157 uint32_t spm_swint_clr; 158 uint32_t spm_scp_mailbox; 159 uint32_t scp_spm_mailbox; 160 uint32_t spm_wakeup_event_sens; 161 uint32_t spm_wakeup_event_clear; 162 uint8_t reserved2[4]; 163 uint32_t spm_scp_irq; 164 uint32_t spm_cpu_wakeup_event; 165 uint32_t spm_irq_mask; 166 uint32_t spm_src_req; 167 uint32_t spm_src_mask; 168 uint32_t spm_src2_mask; 169 uint32_t spm_src3_mask; 170 uint32_t spm_src4_mask; 171 uint32_t spm_src5_mask; 172 uint32_t spm_wakeup_event_mask; 173 uint32_t spm_wakeup_event_ext_mask; 174 uint32_t spm_src7_mask; 175 uint32_t scp_clk_con; 176 uint32_t pcm_debug_con; 177 uint8_t reserved3[4]; 178 uint32_t ddren_dbc_con; 179 uint32_t spm_resource_ack_con4; 180 uint32_t spm_resource_ack_con0; 181 uint32_t spm_resource_ack_con1; 182 uint32_t spm_resource_ack_con2; 183 uint32_t spm_resource_ack_con3; 184 uint32_t pcm_reg0_data; 185 uint32_t pcm_reg2_data; 186 uint32_t pcm_reg6_data; 187 uint32_t pcm_reg7_data; 188 uint32_t pcm_reg13_data; 189 uint32_t src_req_sta_0; 190 uint32_t src_req_sta_1; 191 uint32_t src_req_sta_2; 192 uint32_t pcm_timer_out; 193 uint32_t pcm_wdt_out; 194 uint32_t spm_irq_sta; 195 uint32_t src_req_sta_4; 196 uint32_t md32pcm_wakeup_sta; 197 uint32_t md32pcm_event_sta; 198 uint32_t spm_wakeup_sta; 199 uint32_t spm_wakeup_ext_sta; 200 uint32_t spm_wakeup_misc; 201 uint32_t mm_dvfs_halt; 202 uint8_t reserved4[8]; 203 uint32_t bus_protect_rdy; 204 uint32_t bus_protect1_rdy; 205 uint32_t bus_protect2_rdy; 206 uint32_t bus_protect3_rdy; 207 uint32_t subsys_idle_sta; 208 uint32_t pcm_sta; 209 uint32_t src_req_sta_3; 210 uint32_t pwr_status; 211 uint32_t pwr_status_2nd; 212 uint32_t cpu_pwr_status; 213 uint32_t other_pwr_status; 214 uint32_t spm_vtcxo_event_count_sta; 215 uint32_t spm_infra_event_count_sta; 216 uint32_t spm_vrf18_event_count_sta; 217 uint32_t spm_apsrc_event_count_sta; 218 uint32_t spm_ddren_event_count_sta; 219 uint32_t md32pcm_sta; 220 uint32_t md32pcm_pc; 221 uint8_t reserved5[12]; 222 uint32_t dvfsrc_event_sta; 223 uint32_t bus_protect4_rdy; 224 uint32_t bus_protect5_rdy; 225 uint32_t bus_protect6_rdy; 226 uint32_t bus_protect7_rdy; 227 uint32_t bus_protect8_rdy; 228 uint8_t reserved6[20]; 229 uint32_t spm_twam_last_sta0; 230 uint32_t spm_twam_last_sta1; 231 uint32_t spm_twam_last_sta2; 232 uint32_t spm_twam_last_sta3; 233 uint32_t spm_twam_curr_sta0; 234 uint32_t spm_twam_curr_sta1; 235 uint32_t spm_twam_curr_sta2; 236 uint32_t spm_twam_curr_sta3; 237 uint32_t spm_twam_timer_out; 238 uint32_t spm_cg_check_sta; 239 uint32_t spm_dvfs_sta; 240 uint32_t spm_dvfs_opp_sta; 241 uint32_t spm_mcusys_pwr_con; 242 uint32_t spm_cputop_pwr_con; 243 uint32_t spm_cpu0_pwr_con; 244 uint32_t spm_cpu1_pwr_con; 245 uint32_t spm_cpu2_pwr_con; 246 uint32_t spm_cpu3_pwr_con; 247 uint32_t spm_cpu4_pwr_con; 248 uint32_t spm_cpu5_pwr_con; 249 uint32_t spm_cpu6_pwr_con; 250 uint32_t spm_cpu7_pwr_con; 251 uint8_t reserved7[4]; 252 uint32_t armpll_clk_con; 253 uint32_t mcusys_idle_sta; 254 uint32_t gic_wakeup_sta; 255 uint32_t cpu_spare_con; 256 uint32_t cpu_spare_con_set; 257 uint32_t cpu_spare_con_clr; 258 uint32_t armpll_clk_sel; 259 uint32_t ext_int_wakeup_req; 260 uint32_t ext_int_wakeup_req_set; 261 uint32_t ext_int_wakeup_req_clr; 262 uint8_t reserved8[12]; 263 uint32_t cpu_irq_mask; 264 uint32_t cpu_irq_mask_set; 265 uint32_t cpu_irq_mask_clr; 266 uint8_t reserved9[20]; 267 uint32_t cpu_wfi_en; 268 uint32_t cpu_wfi_en_set; 269 uint32_t cpu_wfi_en_clr; 270 uint8_t reserved10[20]; 271 uint32_t root_cputop_addr; 272 uint32_t root_core_addr; 273 uint8_t reserved11[40]; 274 uint32_t spm2sw_mailbox_0; 275 uint32_t spm2sw_mailbox_1; 276 uint32_t spm2sw_mailbox_2; 277 uint32_t spm2sw_mailbox_3; 278 uint32_t sw2spm_wakeup; 279 uint32_t sw2spm_wakeup_set; 280 uint32_t sw2spm_wakeup_clr; 281 uint32_t sw2spm_mailbox_0; 282 uint32_t sw2spm_mailbox_1; 283 uint32_t sw2spm_mailbox_2; 284 uint32_t sw2spm_mailbox_3; 285 uint32_t sw2spm_cfg; 286 uint32_t md1_pwr_con; 287 uint32_t conn_pwr_con; 288 uint32_t mfg0_pwr_con; 289 uint32_t mfg1_pwr_con; 290 uint32_t mfg2_pwr_con; 291 uint32_t mfg3_pwr_con; 292 uint32_t mfg4_pwr_con; 293 uint32_t mfg5_pwr_con; 294 uint32_t mfg6_pwr_con; 295 uint32_t ifr_pwr_con; 296 uint32_t ifr_sub_pwr_con; 297 uint32_t dpy_pwr_con; 298 uint32_t dramc_md32_pwr_con; 299 uint32_t isp_pwr_con; 300 uint32_t isp2_pwr_con; 301 uint32_t ipe_pwr_con; 302 uint32_t vde_pwr_con; 303 uint32_t vde2_pwr_con; 304 uint32_t ven_pwr_con; 305 uint32_t ven_core1_pwr_con; 306 uint32_t mdp_pwr_con; 307 uint32_t dis_pwr_con; 308 uint32_t audio_pwr_con; 309 uint32_t cam_pwr_con; 310 uint32_t cam_rawa_pwr_con; 311 uint32_t cam_rawb_pwr_con; 312 uint32_t cam_rawc_pwr_con; 313 uint32_t sysram_con; 314 uint32_t sysrom_con; 315 uint32_t sspm_sram_con; 316 uint32_t scp_sram_con; 317 uint32_t dpy_shu_sram_con; 318 uint32_t ufs_sram_con; 319 uint32_t devapc_ifr_sram_con; 320 uint32_t devapc_subifr_sram_con; 321 uint32_t devapc_acp_sram_con; 322 uint32_t usb_sram_con; 323 uint32_t dummy_sram_con; 324 uint32_t md_ext_buck_iso_con; 325 uint32_t ext_buck_iso; 326 uint32_t dxcc_sram_con; 327 uint32_t msdc_pwr_con; 328 uint32_t debugtop_sram_con; 329 uint32_t dp_tx_pwr_con; 330 uint32_t dpmaif_sram_con; 331 uint32_t dpy_shu2_sram_con; 332 uint32_t dramc_mcu2_sram_con; 333 uint32_t dramc_mcu_sram_con; 334 uint32_t mcupm_pwr_con; 335 uint32_t dpy2_pwr_con; 336 uint32_t spm_sram_con; 337 uint8_t reserved12[4]; 338 uint32_t peri_pwr_con; 339 uint32_t nna0_pwr_con; 340 uint32_t nna1_pwr_con; 341 uint32_t nna2_pwr_con; 342 uint32_t nna_pwr_con; 343 uint32_t adsp_pwr_con; 344 uint32_t dpy_sram_con; 345 uint32_t nna3_pwr_con; 346 uint8_t reserved13[8]; 347 uint32_t wpe_pwr_con; 348 uint8_t reserved14[4]; 349 uint32_t spm_mem_ck_sel; 350 uint32_t spm_bus_protect_mask_b; 351 uint32_t spm_bus_protect1_mask_b; 352 uint32_t spm_bus_protect2_mask_b; 353 uint32_t spm_bus_protect3_mask_b; 354 uint32_t spm_bus_protect4_mask_b; 355 uint32_t spm_emi_bw_mode; 356 uint32_t ap2md_peer_wakeup; 357 uint32_t ulposc_con; 358 uint32_t spm2mm_con; 359 uint32_t spm_bus_protect5_mask_b; 360 uint32_t spm2mcupm_con; 361 uint32_t ap_mdsrc_req; 362 uint32_t spm2emi_enter_ulpm; 363 uint32_t spm2md_dvfs_con; 364 uint32_t md2spm_dvfs_con; 365 uint32_t spm_bus_protect6_mask_b; 366 uint32_t spm_bus_protect7_mask_b; 367 uint32_t spm_bus_protect8_mask_b; 368 uint32_t spm_pll_con; 369 uint32_t rc_spm_ctrl; 370 uint32_t spm_dram_mcu_sw_con_0; 371 uint32_t spm_dram_mcu_sw_con_1; 372 uint32_t spm_dram_mcu_sw_con_2; 373 uint32_t spm_dram_mcu_sw_con_3; 374 uint32_t spm_dram_mcu_sw_con_4; 375 uint32_t spm_dram_mcu_sta_0; 376 uint32_t spm_dram_mcu_sta_1; 377 uint32_t spm_dram_mcu_sta_2; 378 uint32_t spm_dram_mcu_sw_sel_0; 379 uint32_t relay_dvfs_level; 380 uint8_t reserved15[4]; 381 uint32_t dramc_dpy_clk_sw_con_0; 382 uint32_t dramc_dpy_clk_sw_con_1; 383 uint32_t dramc_dpy_clk_sw_con_2; 384 uint32_t dramc_dpy_clk_sw_con_3; 385 uint32_t dramc_dpy_clk_sw_sel_0; 386 uint32_t dramc_dpy_clk_sw_sel_1; 387 uint32_t dramc_dpy_clk_sw_sel_2; 388 uint32_t dramc_dpy_clk_sw_sel_3; 389 uint32_t dramc_dpy_clk_spm_con; 390 uint32_t spm_dvfs_level; 391 uint32_t spm_cirq_con; 392 uint32_t spm_dvfs_misc; 393 uint8_t reserved16[4]; 394 uint32_t rg_module_sw_cg_0_mask_req_0; 395 uint32_t rg_module_sw_cg_0_mask_req_1; 396 uint32_t rg_module_sw_cg_0_mask_req_2; 397 uint32_t rg_module_sw_cg_1_mask_req_0; 398 uint32_t rg_module_sw_cg_1_mask_req_1; 399 uint32_t rg_module_sw_cg_1_mask_req_2; 400 uint32_t rg_module_sw_cg_2_mask_req_0; 401 uint32_t rg_module_sw_cg_2_mask_req_1; 402 uint32_t rg_module_sw_cg_2_mask_req_2; 403 uint32_t rg_module_sw_cg_3_mask_req_0; 404 uint32_t rg_module_sw_cg_3_mask_req_1; 405 uint32_t rg_module_sw_cg_3_mask_req_2; 406 uint32_t pwr_status_mask_req_0; 407 uint32_t pwr_status_mask_req_1; 408 uint32_t pwr_status_mask_req_2; 409 uint32_t spm_cg_check_con; 410 uint32_t spm_src_rdy_sta; 411 uint32_t spm_dvs_dfs_level; 412 uint32_t spm_force_dvfs; 413 uint8_t reserved17[256]; 414 uint32_t spm_sw_flag_0; 415 uint32_t spm_sw_debug_0; 416 uint32_t spm_sw_flag_1; 417 uint32_t spm_sw_debug_1; 418 uint32_t spm_sw_rsv_0; 419 uint32_t spm_sw_rsv_1; 420 uint32_t spm_sw_rsv_2; 421 uint32_t spm_sw_rsv_3; 422 uint32_t spm_sw_rsv_4; 423 uint32_t spm_sw_rsv_5; 424 uint32_t spm_sw_rsv_6; 425 uint32_t spm_sw_rsv_7; 426 uint32_t spm_sw_rsv_8; 427 uint32_t spm_bk_wake_event; 428 uint32_t spm_bk_vtcxo_dur; 429 uint32_t spm_bk_wake_misc; 430 uint32_t spm_bk_pcm_timer; 431 uint8_t reserved18[12]; 432 uint32_t spm_rsv_con_0; 433 uint32_t spm_rsv_con_1; 434 uint32_t spm_rsv_sta_0; 435 uint32_t spm_rsv_sta_1; 436 uint32_t spm_spare_con; 437 uint32_t spm_spare_con_set; 438 uint32_t spm_spare_con_clr; 439 uint32_t spm_cross_wake_m00_req; 440 uint32_t spm_cross_wake_m01_req; 441 uint32_t spm_cross_wake_m02_req; 442 uint32_t spm_cross_wake_m03_req; 443 uint32_t scp_vcore_level; 444 uint32_t sc_mm_ck_sel_con; 445 uint32_t spare_ack_mask; 446 uint32_t spm_spare_function; 447 uint32_t spm_dv_con_0; 448 uint32_t spm_dv_con_1; 449 uint32_t spm_dv_sta; 450 uint32_t conn_xowcn_debug_en; 451 uint32_t spm_sema_m0; 452 uint32_t spm_sema_m1; 453 uint32_t spm_sema_m2; 454 uint32_t spm_sema_m3; 455 uint32_t spm_sema_m4; 456 uint32_t spm_sema_m5; 457 uint32_t spm_sema_m6; 458 uint32_t spm_sema_m7; 459 uint32_t spm2adsp_mailbox; 460 uint32_t adsp2spm_mailbox; 461 uint32_t spm_adsp_irq; 462 uint32_t spm_md32_irq; 463 uint32_t spm2pmcu_mailbox_0; 464 uint32_t spm2pmcu_mailbox_1; 465 uint32_t spm2pmcu_mailbox_2; 466 uint32_t spm2pmcu_mailbox_3; 467 uint32_t pmcu2spm_mailbox_0; 468 uint32_t pmcu2spm_mailbox_1; 469 uint32_t pmcu2spm_mailbox_2; 470 uint32_t pmcu2spm_mailbox_3; 471 uint32_t ufs_psri_sw; 472 uint32_t ufs_psri_sw_set; 473 uint32_t ufs_psri_sw_clr; 474 uint32_t spm_ap_sema; 475 uint32_t spm_spm_sema; 476 uint32_t spm_dvfs_con; 477 uint32_t spm_dvfs_con_sta; 478 uint32_t spm_pmic_spmi_con; 479 uint8_t reserved19[4]; 480 uint32_t spm_dvfs_cmd0; 481 uint32_t spm_dvfs_cmd1; 482 uint32_t spm_dvfs_cmd2; 483 uint32_t spm_dvfs_cmd3; 484 uint32_t spm_dvfs_cmd4; 485 uint32_t spm_dvfs_cmd5; 486 uint32_t spm_dvfs_cmd6; 487 uint32_t spm_dvfs_cmd7; 488 uint32_t spm_dvfs_cmd8; 489 uint32_t spm_dvfs_cmd9; 490 uint32_t spm_dvfs_cmd10; 491 uint32_t spm_dvfs_cmd11; 492 uint32_t spm_dvfs_cmd12; 493 uint32_t spm_dvfs_cmd13; 494 uint32_t spm_dvfs_cmd14; 495 uint32_t spm_dvfs_cmd15; 496 uint32_t spm_dvfs_cmd16; 497 uint32_t spm_dvfs_cmd17; 498 uint32_t spm_dvfs_cmd18; 499 uint32_t spm_dvfs_cmd19; 500 uint32_t spm_dvfs_cmd20; 501 uint32_t spm_dvfs_cmd21; 502 uint32_t spm_dvfs_cmd22; 503 uint32_t spm_dvfs_cmd23; 504 uint32_t sys_timer_value_l; 505 uint32_t sys_timer_value_h; 506 uint32_t sys_timer_start_l; 507 uint32_t sys_timer_start_h; 508 uint32_t sys_timer_latch_l_00; 509 uint32_t sys_timer_latch_h_00; 510 uint32_t sys_timer_latch_l_01; 511 uint32_t sys_timer_latch_h_01; 512 uint32_t sys_timer_latch_l_02; 513 uint32_t sys_timer_latch_h_02; 514 uint32_t sys_timer_latch_l_03; 515 uint32_t sys_timer_latch_h_03; 516 uint32_t sys_timer_latch_l_04; 517 uint32_t sys_timer_latch_h_04; 518 uint32_t sys_timer_latch_l_05; 519 uint32_t sys_timer_latch_h_05; 520 uint32_t sys_timer_latch_l_06; 521 uint32_t sys_timer_latch_h_06; 522 uint32_t sys_timer_latch_l_07; 523 uint32_t sys_timer_latch_h_07; 524 uint32_t sys_timer_latch_l_08; 525 uint32_t sys_timer_latch_h_08; 526 uint32_t sys_timer_latch_l_09; 527 uint32_t sys_timer_latch_h_09; 528 uint32_t sys_timer_latch_l_10; 529 uint32_t sys_timer_latch_h_10; 530 uint32_t sys_timer_latch_l_11; 531 uint32_t sys_timer_latch_h_11; 532 uint32_t sys_timer_latch_l_12; 533 uint32_t sys_timer_latch_h_12; 534 uint32_t sys_timer_latch_l_13; 535 uint32_t sys_timer_latch_h_13; 536 uint32_t sys_timer_latch_l_14; 537 uint32_t sys_timer_latch_h_14; 538 uint32_t sys_timer_latch_l_15; 539 uint32_t sys_timer_latch_h_15; 540 uint32_t pcm_wdt_latch_0; 541 uint32_t pcm_wdt_latch_1; 542 uint32_t pcm_wdt_latch_2; 543 uint32_t pcm_wdt_latch_3; 544 uint32_t pcm_wdt_latch_4; 545 uint32_t pcm_wdt_latch_5; 546 uint32_t pcm_wdt_latch_6; 547 uint32_t pcm_wdt_latch_7; 548 uint32_t pcm_wdt_latch_8; 549 uint32_t pcm_wdt_latch_9; 550 uint32_t pcm_wdt_latch_10; 551 uint32_t pcm_wdt_latch_11; 552 uint32_t pcm_wdt_latch_12; 553 uint32_t pcm_wdt_latch_13; 554 uint32_t pcm_wdt_latch_14; 555 uint32_t pcm_wdt_latch_15; 556 uint32_t pcm_wdt_latch_16; 557 uint32_t pcm_wdt_latch_17; 558 uint32_t pcm_wdt_latch_18; 559 uint32_t pcm_wdt_latch_spare_0; 560 uint32_t pcm_wdt_latch_spare_1; 561 uint32_t pcm_wdt_latch_spare_2; 562 uint8_t reserved20[24]; 563 uint32_t pcm_wdt_latch_conn_0; 564 uint32_t pcm_wdt_latch_conn_1; 565 uint32_t pcm_wdt_latch_conn_2; 566 uint8_t reserved21[36]; 567 uint32_t dramc_gating_err_latch_ch0_0; 568 uint32_t dramc_gating_err_latch_ch0_1; 569 uint32_t dramc_gating_err_latch_ch0_2; 570 uint32_t dramc_gating_err_latch_ch0_3; 571 uint32_t dramc_gating_err_latch_ch0_4; 572 uint32_t dramc_gating_err_latch_ch0_5; 573 uint32_t dramc_gating_err_latch_ch0_6; 574 uint8_t reserved22[56]; 575 uint32_t dramc_gating_err_latch_spare_0; 576 uint8_t reserved23[8]; 577 uint32_t spm_ack_chk_con_0; 578 uint32_t spm_ack_chk_pc_0; 579 uint32_t spm_ack_chk_sel_0; 580 uint32_t spm_ack_chk_timer_0; 581 uint32_t spm_ack_chk_sta_0; 582 uint32_t spm_ack_chk_swint_0; 583 uint32_t spm_ack_chk_con_1; 584 uint32_t spm_ack_chk_pc_1; 585 uint32_t spm_ack_chk_sel_1; 586 uint32_t spm_ack_chk_timer_1; 587 uint32_t spm_ack_chk_sta_1; 588 uint32_t spm_ack_chk_swint_1; 589 uint32_t spm_ack_chk_con_2; 590 uint32_t spm_ack_chk_pc_2; 591 uint32_t spm_ack_chk_sel_2; 592 uint32_t spm_ack_chk_timer_2; 593 uint32_t spm_ack_chk_sta_2; 594 uint32_t spm_ack_chk_swint_2; 595 uint32_t spm_ack_chk_con_3; 596 uint32_t spm_ack_chk_pc_3; 597 uint32_t spm_ack_chk_sel_3; 598 uint32_t spm_ack_chk_timer_3; 599 uint32_t spm_ack_chk_sta_3; 600 uint32_t spm_ack_chk_swint_3; 601 uint32_t spm_counter_0; 602 uint32_t spm_counter_1; 603 uint32_t spm_counter_2; 604 uint32_t sys_timer_con; 605 uint32_t spm_twam_con; 606 uint32_t spm_twam_window_len; 607 uint32_t spm_twam_idle_sel; 608 uint32_t spm_twam_event_clear; 609 uint32_t opp0_table; 610 uint32_t opp1_table; 611 uint32_t opp2_table; 612 uint32_t opp3_table; 613 uint32_t opp4_table; 614 uint32_t opp5_table; 615 uint32_t opp6_table; 616 uint32_t opp7_table; 617 uint32_t opp8_table; 618 uint32_t opp9_table; 619 uint32_t opp10_table; 620 uint32_t opp11_table; 621 uint32_t opp12_table; 622 uint32_t opp13_table; 623 uint32_t opp14_table; 624 uint32_t opp15_table; 625 uint32_t opp16_table; 626 uint32_t opp17_table; 627 uint32_t shu0_array; 628 uint32_t shu1_array; 629 uint32_t shu2_array; 630 uint32_t shu3_array; 631 uint32_t shu4_array; 632 uint32_t shu5_array; 633 uint32_t shu6_array; 634 uint32_t shu7_array; 635 uint32_t shu8_array; 636 uint32_t shu9_array; 637 uint32_t ssusb_top_pwr_con; 638 uint32_t ssusb_top_p1_pwr_con; 639 uint32_t adsp_infra_pwr_con; 640 uint32_t adsp_ao_pwr_con; 641 uint32_t md32pcm_cfgreg_sw_rstn; 642 uint8_t reserved_6a04[0x200 - 4]; 643 uint32_t md32pcm_dma0_src; 644 uint32_t md32pcm_dma0_dst; 645 uint32_t md32pcm_dma0_wppt; 646 uint32_t md32pcm_dma0_wpto; 647 uint32_t md32pcm_dma0_count; 648 uint32_t md32pcm_dma0_con; 649 uint32_t md32pcm_dma0_start; 650 uint8_t reserved_6c1c[8]; 651 uint32_t md32pcm_dma0_rlct; 652 }; 653 654 struct pwr_ctrl { 655 /* For SPM */ 656 uint32_t pcm_flags; 657 uint32_t pcm_flags_cust; 658 uint32_t pcm_flags_cust_set; 659 uint32_t pcm_flags_cust_clr; 660 uint32_t pcm_flags1; 661 uint32_t pcm_flags1_cust; 662 uint32_t pcm_flags1_cust_set; 663 uint32_t pcm_flags1_cust_clr; 664 uint32_t timer_val; 665 uint32_t timer_val_cust; 666 uint32_t timer_val_ramp_en; 667 uint32_t timer_val_ramp_en_sec; 668 uint32_t wake_src; 669 uint32_t wake_src_cust; 670 uint32_t wakelock_timer_val; 671 uint8_t wdt_disable; 672 /* Auto-gen Start */ 673 674 /* SPM_AP_STANDBY_CON */ 675 uint8_t reg_wfi_op; 676 uint8_t reg_wfi_type; 677 uint8_t reg_mp0_cputop_idle_mask; 678 uint8_t reg_mp1_cputop_idle_mask; 679 uint8_t reg_mcusys_idle_mask; 680 uint8_t reg_md_apsrc_1_sel; 681 uint8_t reg_md_apsrc_0_sel; 682 uint8_t reg_conn_apsrc_sel; 683 684 /* SPM_SRC6_MASK */ 685 uint32_t reg_ccif_event_infra_req_mask_b; 686 uint32_t reg_ccif_event_apsrc_req_mask_b; 687 688 /* SPM_SRC_REQ */ 689 uint8_t reg_spm_apsrc_req; 690 uint8_t reg_spm_f26m_req; 691 uint8_t reg_spm_infra_req; 692 uint8_t reg_spm_vrf18_req; 693 uint8_t reg_spm_ddren_req; 694 uint8_t reg_spm_dvfs_req; 695 uint8_t reg_spm_sw_mailbox_req; 696 uint8_t reg_spm_sspm_mailbox_req; 697 uint8_t reg_spm_adsp_mailbox_req; 698 uint8_t reg_spm_scp_mailbox_req; 699 700 /* SPM_SRC_MASK */ 701 uint8_t reg_md_0_srcclkena_mask_b; 702 uint8_t reg_md_0_infra_req_mask_b; 703 uint8_t reg_md_0_apsrc_req_mask_b; 704 uint8_t reg_md_0_vrf18_req_mask_b; 705 uint8_t reg_md_0_ddren_req_mask_b; 706 uint8_t reg_md_1_srcclkena_mask_b; 707 uint8_t reg_md_1_infra_req_mask_b; 708 uint8_t reg_md_1_apsrc_req_mask_b; 709 uint8_t reg_md_1_vrf18_req_mask_b; 710 uint8_t reg_md_1_ddren_req_mask_b; 711 uint8_t reg_conn_srcclkena_mask_b; 712 uint8_t reg_conn_srcclkenb_mask_b; 713 uint8_t reg_conn_infra_req_mask_b; 714 uint8_t reg_conn_apsrc_req_mask_b; 715 uint8_t reg_conn_vrf18_req_mask_b; 716 uint8_t reg_conn_ddren_req_mask_b; 717 uint8_t reg_conn_vfe28_mask_b; 718 uint8_t reg_srcclkeni_srcclkena_mask_b; 719 uint8_t reg_srcclkeni_infra_req_mask_b; 720 uint8_t reg_infrasys_apsrc_req_mask_b; 721 uint8_t reg_infrasys_ddren_req_mask_b; 722 uint8_t reg_sspm_srcclkena_mask_b; 723 uint8_t reg_sspm_infra_req_mask_b; 724 uint8_t reg_sspm_apsrc_req_mask_b; 725 uint8_t reg_sspm_vrf18_req_mask_b; 726 uint8_t reg_sspm_ddren_req_mask_b; 727 728 /* SPM_SRC2_MASK */ 729 uint8_t reg_scp_srcclkena_mask_b; 730 uint8_t reg_scp_infra_req_mask_b; 731 uint8_t reg_scp_apsrc_req_mask_b; 732 uint8_t reg_scp_vrf18_req_mask_b; 733 uint8_t reg_scp_ddren_req_mask_b; 734 uint8_t reg_audio_dsp_srcclkena_mask_b; 735 uint8_t reg_audio_dsp_infra_req_mask_b; 736 uint8_t reg_audio_dsp_apsrc_req_mask_b; 737 uint8_t reg_audio_dsp_vrf18_req_mask_b; 738 uint8_t reg_audio_dsp_ddren_req_mask_b; 739 uint8_t reg_ufs_srcclkena_mask_b; 740 uint8_t reg_ufs_infra_req_mask_b; 741 uint8_t reg_ufs_apsrc_req_mask_b; 742 uint8_t reg_ufs_vrf18_req_mask_b; 743 uint8_t reg_ufs_ddren_req_mask_b; 744 uint8_t reg_disp0_apsrc_req_mask_b; 745 uint8_t reg_disp0_ddren_req_mask_b; 746 uint8_t reg_disp1_apsrc_req_mask_b; 747 uint8_t reg_disp1_ddren_req_mask_b; 748 uint8_t reg_gce_infra_req_mask_b; 749 uint8_t reg_gce_apsrc_req_mask_b; 750 uint8_t reg_gce_vrf18_req_mask_b; 751 uint8_t reg_gce_ddren_req_mask_b; 752 uint8_t reg_apu_srcclkena_mask_b; 753 uint8_t reg_apu_infra_req_mask_b; 754 uint8_t reg_apu_apsrc_req_mask_b; 755 uint8_t reg_apu_vrf18_req_mask_b; 756 uint8_t reg_apu_ddren_req_mask_b; 757 uint8_t reg_cg_check_srcclkena_mask_b; 758 uint8_t reg_cg_check_apsrc_req_mask_b; 759 uint8_t reg_cg_check_vrf18_req_mask_b; 760 uint8_t reg_cg_check_ddren_req_mask_b; 761 762 /* SPM_SRC3_MASK */ 763 uint8_t reg_dvfsrc_event_trigger_mask_b; 764 uint8_t reg_sw2spm_wakeup_mask_b; 765 uint8_t reg_adsp2spm_wakeup_mask_b; 766 uint8_t reg_sspm2spm_wakeup_mask_b; 767 uint8_t reg_scp2spm_wakeup_mask_b; 768 uint8_t reg_csyspwrup_ack_mask; 769 uint8_t reg_spm_reserved_srcclkena_mask_b; 770 uint8_t reg_spm_reserved_infra_req_mask_b; 771 uint8_t reg_spm_reserved_apsrc_req_mask_b; 772 uint8_t reg_spm_reserved_vrf18_req_mask_b; 773 uint8_t reg_spm_reserved_ddren_req_mask_b; 774 uint8_t reg_mcupm_srcclkena_mask_b; 775 uint8_t reg_mcupm_infra_req_mask_b; 776 uint8_t reg_mcupm_apsrc_req_mask_b; 777 uint8_t reg_mcupm_vrf18_req_mask_b; 778 uint8_t reg_mcupm_ddren_req_mask_b; 779 uint8_t reg_msdc0_srcclkena_mask_b; 780 uint8_t reg_msdc0_infra_req_mask_b; 781 uint8_t reg_msdc0_apsrc_req_mask_b; 782 uint8_t reg_msdc0_vrf18_req_mask_b; 783 uint8_t reg_msdc0_ddren_req_mask_b; 784 uint8_t reg_msdc1_srcclkena_mask_b; 785 uint8_t reg_msdc1_infra_req_mask_b; 786 uint8_t reg_msdc1_apsrc_req_mask_b; 787 uint8_t reg_msdc1_vrf18_req_mask_b; 788 uint8_t reg_msdc1_ddren_req_mask_b; 789 790 /* SPM_SRC4_MASK */ 791 uint32_t reg_ccif_event_srcclkena_mask_b; 792 uint8_t reg_bak_psri_srcclkena_mask_b; 793 uint8_t reg_bak_psri_infra_req_mask_b; 794 uint8_t reg_bak_psri_apsrc_req_mask_b; 795 uint8_t reg_bak_psri_vrf18_req_mask_b; 796 uint8_t reg_bak_psri_ddren_req_mask_b; 797 uint8_t reg_dramc_md32_infra_req_mask_b; 798 uint8_t reg_dramc_md32_vrf18_req_mask_b; 799 uint8_t reg_conn_srcclkenb2pwrap_mask_b; 800 uint8_t reg_dramc_md32_apsrc_req_mask_b; 801 802 /* SPM_SRC5_MASK */ 803 uint32_t reg_mcusys_merge_apsrc_req_mask_b; 804 uint32_t reg_mcusys_merge_ddren_req_mask_b; 805 uint8_t reg_afe_srcclkena_mask_b; 806 uint8_t reg_afe_infra_req_mask_b; 807 uint8_t reg_afe_apsrc_req_mask_b; 808 uint8_t reg_afe_vrf18_req_mask_b; 809 uint8_t reg_afe_ddren_req_mask_b; 810 uint8_t reg_msdc2_srcclkena_mask_b; 811 uint8_t reg_msdc2_infra_req_mask_b; 812 uint8_t reg_msdc2_apsrc_req_mask_b; 813 uint8_t reg_msdc2_vrf18_req_mask_b; 814 uint8_t reg_msdc2_ddren_req_mask_b; 815 816 /* SPM_WAKEUP_EVENT_MASK */ 817 uint32_t reg_wakeup_event_mask; 818 819 /* SPM_WAKEUP_EVENT_EXT_MASK */ 820 uint32_t reg_ext_wakeup_event_mask; 821 822 /* SPM_SRC7_MASK */ 823 uint8_t reg_pcie_srcclkena_mask_b; 824 uint8_t reg_pcie_infra_req_mask_b; 825 uint8_t reg_pcie_apsrc_req_mask_b; 826 uint8_t reg_pcie_vrf18_req_mask_b; 827 uint8_t reg_pcie_ddren_req_mask_b; 828 uint8_t reg_dpmaif_srcclkena_mask_b; 829 uint8_t reg_dpmaif_infra_req_mask_b; 830 uint8_t reg_dpmaif_apsrc_req_mask_b; 831 uint8_t reg_dpmaif_vrf18_req_mask_b; 832 uint8_t reg_dpmaif_ddren_req_mask_b; 833 834 /* Auto-gen End */ 835 }; 836 837 check_member(mtk_spm_regs, poweron_config_set, 0x0); 838 check_member(mtk_spm_regs, dis_pwr_con, 0x354); 839 check_member(mtk_spm_regs, nna_pwr_con, 0x3E0); 840 check_member(mtk_spm_regs, ap_mdsrc_req, 0x430); 841 check_member(mtk_spm_regs, ssusb_top_pwr_con, 0x9F0); 842 check_member(mtk_spm_regs, ssusb_top_p1_pwr_con, 0x9F4); 843 check_member(mtk_spm_regs, adsp_infra_pwr_con, 0x9F8); 844 check_member(mtk_spm_regs, adsp_ao_pwr_con, 0x9FC); 845 check_member(mtk_spm_regs, md32pcm_cfgreg_sw_rstn, 0xA00); 846 check_member(mtk_spm_regs, md32pcm_dma0_src, 0xC00); 847 check_member(mtk_spm_regs, md32pcm_dma0_dst, 0xC04); 848 check_member(mtk_spm_regs, md32pcm_dma0_wppt, 0xC08); 849 check_member(mtk_spm_regs, md32pcm_dma0_wpto, 0xC0C); 850 check_member(mtk_spm_regs, md32pcm_dma0_count, 0xC10); 851 check_member(mtk_spm_regs, md32pcm_dma0_con, 0xC14); 852 check_member(mtk_spm_regs, md32pcm_dma0_start, 0xC18); 853 check_member(mtk_spm_regs, md32pcm_dma0_rlct, 0xC24); 854 855 static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE; 856 857 static const struct power_domain_data disp[] = { 858 { 859 .pwr_con = &mtk_spm->dis_pwr_con, 860 .pwr_sta_mask = 0x1 << 21, 861 .sram_pdn_mask = 0x1 << 8, 862 .sram_ack_mask = 0x1 << 12, 863 }, 864 }; 865 866 /* without audio mtcmos control in MT8186 */ 867 static const struct power_domain_data audio[] = { 868 }; 869 870 static const struct power_domain_data adsp[] = { 871 { 872 .pwr_con = &mtk_spm->adsp_ao_pwr_con, 873 .pwr_sta_mask = 0x1 << 17, 874 }, 875 { 876 .pwr_con = &mtk_spm->adsp_infra_pwr_con, 877 .pwr_sta_mask = 0x1 << 10, 878 }, 879 { 880 .pwr_con = &mtk_spm->adsp_pwr_con, 881 .pwr_sta_mask = 0x1 << 31, 882 .sram_pdn_mask = 0x1 << 8, 883 .sram_ack_mask = 0x1 << 12, 884 .caps = SCPD_SRAM_ISO, 885 }, 886 }; 887 888 #endif /* SOC_MEDIATEK_MT8186_SPM_H */ 889