1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_MEDIATEK_MT8173_PLL_H 4 #define SOC_MEDIATEK_MT8173_PLL_H 5 6 #include <soc/emi.h> 7 #include <soc/pll_common.h> 8 9 struct mtk_topckgen_regs { 10 u32 clk_mode; 11 u32 dcm_cfg; 12 u32 reserved1[6]; 13 u32 tst_sel_0; /* 0x020 */ 14 u32 tst_sel_1; 15 u32 tst_sel_2; 16 u32 reserved2[5]; 17 u32 clk_cfg_0; /* 0x040 */ 18 u32 clk_cfg_0_set; 19 u32 clk_cfg_0_clr; 20 u32 reserved3[1]; 21 u32 clk_cfg_1; /* 0x050 */ 22 u32 clk_cfg_1_set; 23 u32 clk_cfg_1_clr; 24 u32 reserved4[1]; 25 u32 clk_cfg_2; /* 0x060 */ 26 u32 clk_cfg_2_set; 27 u32 clk_cfg_2_clr; 28 u32 reserved5[1]; 29 u32 clk_cfg_3; /* 0x070 */ 30 u32 clk_cfg_3_set; 31 u32 clk_cfg_3_clr; 32 u32 reserved6[1]; 33 u32 clk_cfg_4; /* 0x080 */ 34 u32 clk_cfg_4_set; 35 u32 clk_cfg_4_clr; 36 u32 reserved7[1]; 37 u32 clk_cfg_5; /* 0x090 */ 38 u32 clk_cfg_5_set; 39 u32 clk_cfg_5_clr; 40 u32 reserved8[1]; 41 u32 clk_cfg_6; /* 0x0a0 */ 42 u32 clk_cfg_6_set; 43 u32 clk_cfg_6_clr; 44 u32 reserved9[1]; 45 u32 clk_cfg_7; /* 0x0b0 */ 46 u32 clk_cfg_7_set; 47 u32 clk_cfg_7_clr; 48 u32 reserved10[1]; 49 u32 clk_cfg_12; /* 0x0c0 */ 50 u32 clk_cfg_12_set; 51 u32 clk_cfg_12_clr; 52 u32 reserved11[1]; 53 u32 clk_cfg_13; /* 0x0d0 */ 54 u32 clk_cfg_13_set; 55 u32 clk_cfg_13_clr; 56 u32 reserved12[9]; 57 u32 clk_cfg_8; /* 0x100 */ 58 u32 clk_cfg_9; 59 u32 clk_cfg_10; 60 u32 clk_cfg_11; 61 u32 reserved13[4]; 62 u32 clk_auddiv_0; /* 0x120 */ 63 u32 clk_auddiv_1; 64 u32 clk_auddiv_2; 65 u32 clk_auddiv_3; 66 u32 clk_mjcdiv_0; 67 u32 reserved14[51]; 68 u32 clk_scp_cfg_0; /* 0x200 */ 69 u32 clk_scp_cfg_1; 70 u32 reserved15[2]; 71 u32 clk_misc_cfg_0; /* 0x210 */ 72 u32 clk_misc_cfg_1; 73 u32 clk_misc_cfg_2; 74 u32 reserved16[1]; 75 u32 clk26cali_0; /* 0x220 */ 76 u32 clk26cali_1; 77 u32 clk26cali_2; 78 u32 cksta_reg; 79 u32 test_mode_cfg; 80 u32 reserved17[53]; 81 u32 mbist_cfg_0; /* 0x308 */ 82 u32 mbist_cfg_1; 83 u32 reset_deglitch_key; 84 u32 mbist_cfg_3; /* 0x314 */ 85 }; 86 87 check_member(mtk_topckgen_regs, clk_cfg_0, 0x40); 88 check_member(mtk_topckgen_regs, clk_cfg_8, 0x100); 89 check_member(mtk_topckgen_regs, clk_scp_cfg_0, 0x200); 90 check_member(mtk_topckgen_regs, mbist_cfg_3, 0x314); 91 92 struct mtk_apmixed_regs { 93 u32 ap_pll_con0; 94 u32 reserved1[1]; 95 u32 ap_pll_con2; /* 0x008 */ 96 u32 ap_pll_con3; 97 u32 ap_pll_con4; 98 u32 ap_pll_con5; 99 u32 ap_pll_con6; 100 u32 ap_pll_con7; 101 u32 clksq_stb_con0; 102 u32 pll_pwr_con0; 103 u32 pll_pwr_con1; 104 u32 pll_iso_con0; 105 u32 pll_iso_con1; 106 u32 pll_stb_con0; 107 u32 div_stb_con0; 108 u32 pll_chg_con0; 109 u32 pll_test_con0; 110 u32 pll_test_con1; /* 0x044 */ 111 u32 reserved2[110]; 112 u32 armca15pll_con0; /* 0x200 */ 113 u32 armca15pll_con1; 114 u32 armca15pll_con2; 115 u32 armca15pll_pwr_con0; 116 u32 armca7pll_con0; 117 u32 armca7pll_con1; 118 u32 armca7pll_con2; 119 u32 armca7pll_pwr_con0; 120 u32 mainpll_con0; 121 u32 mainpll_con1; 122 u32 mainpll_con2; 123 u32 mainpll_pwr_con0; 124 u32 univpll_con0; 125 u32 univpll_con1; 126 u32 univpll_con2; 127 u32 univpll_pwr_con0; 128 u32 mmpll_con0; 129 u32 mmpll_con1; 130 u32 mmpll_con2; 131 u32 mmpll_pwr_con0; 132 u32 msdcpll_con0; 133 u32 msdcpll_con1; 134 u32 msdcpll_con2; 135 u32 msdcpll_pwr_con0; 136 u32 vencpll_con0; 137 u32 vencpll_con1; 138 u32 vencpll_con2; 139 u32 vencpll_pwr_con0; 140 u32 tvdpll_con0; 141 u32 tvdpll_con1; 142 u32 tvdpll_con2; 143 u32 tvdpll_pwr_con0; 144 u32 mpll_con0; 145 u32 mpll_con1; 146 u32 mpll_con2; 147 u32 mpll_pwr_con0; 148 u32 vcodecpll_con0; 149 u32 vcodecpll_con1; 150 u32 vcodecpll_con2; 151 u32 vcodecpll_pwr_con0; 152 u32 apll1_con0; 153 u32 apll1_con1; 154 u32 apll1_con2; 155 u32 apll1_con3; 156 u32 apll1_pwr_con0; 157 u32 apll2_con0; 158 u32 apll2_con1; 159 u32 apll2_con2; 160 u32 apll2_con3; 161 u32 apll2_pwr_con0; 162 u32 reserved3[2]; 163 u32 lvdspll_con0; /* 0x2d0 */ 164 u32 lvdspll_con1; 165 u32 lvdspll_con2; 166 u32 lvdspll_pwr_con0; 167 u32 lvdspll_ssc_con0; 168 u32 lvdspll_ssc_con1; 169 u32 lvdspll_ssc_con2; 170 u32 reserved4[1]; 171 u32 msdcpll2_con0; /* 0x2f0 */ 172 u32 msdcpll2_con1; 173 u32 msdcpll2_con2; 174 u32 msdcpll2_pwr_con0; /* 0x2fc */ 175 }; 176 177 check_member(mtk_apmixed_regs, ap_pll_con2, 0x8); 178 check_member(mtk_apmixed_regs, armca15pll_con0, 0x200); 179 check_member(mtk_apmixed_regs, msdcpll2_pwr_con0, 0x2fc); 180 181 enum { 182 PLL_PWR_ON_DELAY = 5, 183 PLL_ISO_DELAY = 0, 184 PLL_EN_DELAY = 40, 185 }; 186 187 enum { 188 PCW_INTEGER_BITS = 7, 189 }; 190 191 /* PLL rate */ 192 enum { 193 ARMCA15PLL_HZ = 851500 * KHz, 194 ARMCA7PLL_HZ = 1105 * MHz, 195 MAINPLL_HZ = 1092 * MHz, 196 UNIVPLL_HZ = 1248 * MHz, 197 MMPLL_HZ = 455 * MHz, 198 MSDCPLL_HZ = 800 * MHz, 199 VENCPLL_HZ = 660 * MHz, 200 TVDPLL_HZ = 1782 * MHz, 201 MPLL_HZ = 1456 * MHz, 202 VCODECPLL_HZ = 1104 * MHz, 203 LVDSPLL_HZ = 150 * MHz, 204 MSDCPLL2_HZ = 800 * MHz, 205 APLL1_HZ = 180633600, 206 APLL2_HZ = 196608 * KHz, 207 }; 208 209 /* top_div rate */ 210 enum { 211 AD_HDMITX_CLK_HZ = TVDPLL_HZ / 12, 212 AD_LVDSPLL_CK_HZ = LVDSPLL_HZ, 213 APLL1_CK_HZ = APLL1_HZ, 214 APLL2_CK_HZ = APLL2_HZ, 215 CLK26M_HZ = 26 * MHz, 216 CLKRTC_EXT_HZ = 32 * KHz, 217 MMPLL_CK_HZ = MMPLL_HZ, 218 MSDCPLL_D4_HZ = MSDCPLL_HZ / 4, 219 SYSPLL1_D2_HZ = MAINPLL_HZ / 4, 220 SYSPLL1_D4_HZ = MAINPLL_HZ / 8, 221 SYSPLL2_D2_HZ = MAINPLL_HZ / 6, 222 SYSPLL3_D2_HZ = MAINPLL_HZ / 10, 223 SYSPLL3_D4_HZ = MAINPLL_HZ / 20, 224 SYSPLL_D2_HZ = MAINPLL_HZ / 2, 225 TVDPLL_D2_HZ = TVDPLL_HZ / 2, 226 UNIVPLL1_D2_HZ = UNIVPLL_HZ / 4, 227 UNIVPLL1_D8_HZ = UNIVPLL_HZ / 16, 228 UNIVPLL2_D2_HZ = UNIVPLL_HZ / 6, 229 UNIVPLL2_D4_HZ = UNIVPLL_HZ / 12, 230 UNIVPLL3_D2_HZ = UNIVPLL_HZ / 10, 231 UNIVPLL_D52_HZ = UNIVPLL_HZ / 52, 232 VCODECPLL_CK_HZ = VCODECPLL_HZ / 3, 233 VENCPLL_D2_HZ = VENCPLL_HZ / 2, 234 }; 235 236 /* top_mux rate */ 237 enum { 238 AXI_HZ = UNIVPLL2_D2_HZ, 239 MEM_HZ = CLK26M_HZ, 240 DDRPHYCFG_HZ = CLK26M_HZ, 241 MM_HZ = VENCPLL_D2_HZ, 242 PWM_HZ = CLK26M_HZ, 243 VDEC_HZ = VCODECPLL_CK_HZ, 244 VENC_HZ = VCODECPLL_CK_HZ, 245 MFG_HZ = MMPLL_CK_HZ, 246 CAMTG_HZ = CLK26M_HZ, 247 UART_HZ = CLK26M_HZ, 248 SPI_HZ = SYSPLL3_D2_HZ, 249 USB20_HZ = UNIVPLL1_D8_HZ, 250 MSDC30_2_HZ = MSDCPLL_D4_HZ, 251 MSDC30_3_HZ = MSDCPLL_D4_HZ, 252 AUDIO_HZ = CLK26M_HZ, 253 AUD_INTBUS_HZ = SYSPLL1_D4_HZ, 254 PMICSPI_HZ = CLK26M_HZ, 255 SCP_HZ = SYSPLL1_D2_HZ, 256 ATB_HZ = CLK26M_HZ, 257 VENC_LT_HZ = UNIVPLL1_D2_HZ, 258 DPI0_HZ = TVDPLL_D2_HZ, 259 IRDA_HZ = UNIVPLL2_D4_HZ, 260 CCI400_HZ = SYSPLL_D2_HZ, 261 AUD_1_HZ = APLL1_CK_HZ, 262 AUD_2_HZ = APLL2_CK_HZ, 263 MEM_MFG_IN_HZ = MMPLL_CK_HZ, 264 AXI_MFG_IN_HZ = AXI_HZ, 265 SCAM_HZ = SYSPLL3_D2_HZ, 266 SPINFI_IFR_HZ = CLK26M_HZ, 267 HDMI_HZ = AD_HDMITX_CLK_HZ, 268 DPILVDS_HZ = AD_LVDSPLL_CK_HZ, 269 MSDC50_2_H_HZ = SYSPLL2_D2_HZ, 270 HDCP_HZ = SYSPLL3_D4_HZ, 271 HDCP_24M_HZ = UNIVPLL_D52_HZ, 272 RTC_HZ = CLKRTC_EXT_HZ, 273 USB30_HZ = UNIVPLL3_D2_HZ, 274 MSDC50_0_H_HZ = SYSPLL2_D2_HZ, 275 MSDC50_0_HZ = MSDCPLL_D4_HZ, 276 MSDC30_1_HZ = MSDCPLL_D4_HZ, 277 }; 278 279 void mt_pll_post_init(void); 280 void mt_pll_set_aud_div(u32 rate); 281 void mt_pll_enable_ssusb_clk(void); 282 void mt_mem_pll_set_clk_cfg(void); 283 void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params); 284 void mt_mem_pll_config_post(void); 285 void mt_mem_pll_mux(void); 286 287 #endif /* SOC_MEDIATEK_MT8173_PLL_H */ 288