1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 /*
4 * A generic pre-ram driver for Aspeed variant Super I/O chips.
5 *
6 * The following is derived directly from the vendor Aspeed's data-sheets:
7 *
8 * To toggle between `configuration mode` and `normal operation mode` as to
9 * manipulation the various LDN's in Aspeed Super I/O's we are required to
10 * pass magic numbers `passwords keys`.
11 *
12 * ASPEED_ENTRY_KEY := enable configuration : 0xA5 (twice!)
13 * ASPEED_EXIT_KEY := disable configuration : 0xAA
14 *
15 * To modify a LDN's configuration register, we use the index port to select
16 * the index of the LDN and then writing to the data port to alter the
17 * parameters. A default index, data port pair is 0x4E, 0x4F respectively, a
18 * user modified pair is 0x2E, 0x2F respectively.
19 *
20 */
21
22 #include <arch/io.h>
23 #include <delay.h>
24 #include <device/pnp_def.h>
25 #include <device/pnp_ops.h>
26 #include <stdint.h>
27 #include "aspeed.h"
28
29 /* Enable configuration: pass entry key '0xA5' into index port dev. */
pnp_enter_conf_state(pnp_devfn_t dev)30 void pnp_enter_conf_state(pnp_devfn_t dev)
31 {
32 u16 port = dev >> 8;
33 outb(ASPEED_ENTRY_KEY, port);
34 outb(ASPEED_ENTRY_KEY, port);
35 }
36
37 /* Disable configuration: pass exit key '0xAA' into index port dev. */
pnp_exit_conf_state(pnp_devfn_t dev)38 void pnp_exit_conf_state(pnp_devfn_t dev)
39 {
40 u16 port = dev >> 8;
41 outb(ASPEED_EXIT_KEY, port);
42 }
43
44 /* Bring up early serial debugging output before the RAM is initialized. */
aspeed_enable_serial(pnp_devfn_t dev,u16 iobase)45 void aspeed_enable_serial(pnp_devfn_t dev, u16 iobase)
46 {
47 pnp_enter_conf_state(dev);
48 pnp_set_logical_device(dev);
49 pnp_set_enable(dev, 0);
50 pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
51 pnp_set_enable(dev, 1);
52 pnp_exit_conf_state(dev);
53
54 if (CONFIG(SUPERIO_ASPEED_USE_UART_DELAY_WORKAROUND))
55 mdelay(500);
56 }
57