1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 #include <soc/addressmap.h> 3 #include <types.h> 4 5 #ifndef __SOC_QUALCOMM_QCS405_CLOCK_H__ 6 #define __SOC_QUALCOMM_QCS405_CLOCK_H__ 7 8 #define BLSP1_AHB_CLK_ENA 10 9 #define BLSP2_AHB_CLK_ENA 20 10 #define SRC_XO_19_2MHZ 0 11 #define SRC_GPLL0_MAIN_800MHZ 1 12 13 /** 14 * USB BCR registers 15 */ 16 #define GCC_USB_HS_PHY_CFG_AHB_BCR 0x180000C 17 #define GCC_USB_HS_BCR 0x1841000 18 #define GCC_USB_30_BCR 0x1839000 19 #define GCC_USB2A_PHY_BCR 0x180000C 20 #define GCC_USB2_HS_PHY_ONLY_BCR 0x1841034 21 #define GCC_QUSB2_PHY_BCR 0x184103C 22 23 struct qcs405_rcg { 24 u32 cmd; 25 u32 cfg; 26 }; 27 28 struct qcs405_clock { 29 struct qcs405_rcg rcg; 30 uint32_t m; 31 uint32_t n; 32 uint32_t d_2; 33 }; 34 35 struct qcs405_bcr { 36 uint32_t bcr; 37 }; 38 39 struct qcs405_gpll { 40 u32 mode; 41 u32 l_val; 42 u32 gpll_alpha_val; 43 u32 gpll_alpha_val_u; 44 u32 user_ctl; 45 u32 user_ctl_u; 46 u32 config_ctl; 47 u32 test_ctl; 48 u32 test_ctl_u; 49 }; 50 51 struct qcs405_gcc { 52 u8 _res0[0x1000 - 0x0]; 53 u32 blsp1_bcr; 54 u32 blsp1_sleep_cbcr; 55 u32 blsp1_ahb_cbcr; 56 struct qcs405_rcg gcc_blsp_uart_sim_rcg; 57 u8 _res1[0x2000 - 0x1014]; 58 u32 blsp1_qup1_bcr; 59 u32 blsp1_qup1_spi_apps_cbcr; 60 u32 blsp1_qup1_i2c_apps_cbcr; 61 struct qcs405_clock blsp1_qup1_i2c_clk; 62 u8 _res2[0x2024 - 0x2020]; 63 struct qcs405_clock blsp1_qup1_spi_clk; 64 u8 _res3[0x3008-0x2038]; 65 u32 blsp1_qup2_bcr; 66 u32 blsp1_qup2_spi_apps_cbcr; 67 u8 _res4[0x3014 - 0x3010]; 68 struct qcs405_clock blsp1_qup2_spi_clk; 69 u32 blsp1_uart2_bcr; 70 u32 blsp1_uart2_apps_cbcr; 71 u32 blsp1_uart2_sim_cbcr; 72 struct qcs405_clock blsp1_uart2_apps_clk; 73 u8 _res5[0x4018 - 0x3048]; 74 u32 blsp1_qup3_bcr; 75 u32 blsp1_qup3_spi_apps_cbcr; 76 u8 _res6[0x4024 - 0x4020]; 77 struct qcs405_clock blsp1_qup3_spi_clk; 78 u8 _res7[0x5018 - 0x4038]; 79 u32 blsp1_qup4_bcr; 80 u32 blsp1_qup4_spi_apps_cbcr; 81 u8 _res8[0x5024 - 0x5020]; 82 struct qcs405_clock blsp1_qup4_spi_clk; 83 u8 _res9[0x6020 - 0x5038]; 84 u32 blsp1_qup0_bcr; 85 u32 blsp1_qup0_spi_apps_cbcr; 86 u8 _res10[0x6034 - 0x6028]; 87 struct qcs405_clock blsp1_qup0_spi_clk; 88 u8 _res11[0xB000 - 0x6048]; 89 u32 blsp2_bcr; 90 u32 blsp2_sleep_cbcr; 91 u32 blsp2_ahb_cbcr; 92 u8 _res12[0xC000 - 0xB00C]; 93 u32 blsp2_qup0_bcr; 94 u32 blsp2_qup0_spi_apps_cbcr; 95 u8 _res13[0xC024 - 0xC008]; 96 struct qcs405_clock blsp2_qup0_spi_clk; 97 u8 _res14[0x21000 - 0xC038]; 98 struct qcs405_gpll gpll0; 99 u8 _res15[0x45004 - 0x21024]; 100 u32 gcc_apcs_clock_branch_en_vote; 101 }; 102 103 struct mdss_clock_config { 104 const char *clk_name; 105 struct qcs405_clock *rcgr; 106 uint32_t *cbcr; 107 }; 108 109 enum clk_ctl_gpll_user_ctl { 110 CLK_CTL_GPLL_PLLOUT_LV_EARLY_BMSK = 0x8, 111 CLK_CTL_GPLL_PLLOUT_AUX2_BMSK = 0x4, 112 CLK_CTL_GPLL_PLLOUT_AUX_BMSK = 0x2, 113 CLK_CTL_GPLL_PLLOUT_MAIN_BMSK = 0x1, 114 CLK_CTL_GPLL_PLLOUT_LV_EARLY_SHFT = 3, 115 CLK_CTL_GPLL_PLLOUT_AUX2_SHFT = 2, 116 CLK_CTL_GPLL_PLLOUT_AUX_SHFT = 1, 117 CLK_CTL_GPLL_PLLOUT_MAIN_SHFT = 0, 118 }; 119 120 enum clk_ctl_cfg_rcgr { 121 CLK_CTL_CFG_MODE_BMSK = 0x3000, 122 CLK_CTL_CFG_MODE_SHFT = 12, 123 CLK_CTL_CFG_SRC_SEL_BMSK = 0x700, 124 CLK_CTL_CFG_SRC_SEL_SHFT = 8, 125 CLK_CTL_CFG_SRC_DIV_BMSK = 0x1F, 126 CLK_CTL_CFG_SRC_DIV_SHFT = 0 127 }; 128 129 enum clk_ctl_cmd_rcgr { 130 CLK_CTL_CMD_ROOT_OFF_BMSK = 0x80000000, 131 CLK_CTL_CMD_ROOT_OFF_SHFT = 31, 132 CLK_CTL_CMD_ROOT_EN_BMSK = 0x2, 133 CLK_CTL_CMD_ROOT_EN_SHFT = 1, 134 CLK_CTL_CMD_UPDATE_BMSK = 0x1, 135 CLK_CTL_CMD_UPDATE_SHFT = 0 136 }; 137 138 enum clk_ctl_cbcr { 139 CLK_CTL_CBC_CLK_OFF_BMSK = 0x80000000, 140 CLK_CTL_CBC_CLK_OFF_SHFT = 31, 141 CLK_CTL_CBC_CLK_EN_BMSK = 0x1, 142 CLK_CTL_CBC_CLK_EN_SHFT = 0 143 }; 144 145 enum clk_ctl_rcg_mnd { 146 CLK_CTL_RCG_MND_BMSK = 0xFFFF, 147 CLK_CTL_RCG_MND_SHFT = 0, 148 }; 149 150 enum clk_ctl_bcr { 151 CLK_CTL_BCR_BLK_ARES_BMSK = 0x1, 152 CLK_CTL_BCR_BLK_ARES_SHFT = 0, 153 }; 154 155 struct clock_config { 156 uint32_t hz; 157 uint32_t hw_ctl; 158 uint32_t src; 159 uint32_t div; 160 uint32_t m; 161 uint32_t n; 162 uint32_t d_2; 163 }; 164 165 static struct qcs405_gcc *const gcc = (void *)GCC_BASE; 166 167 void clock_init(void); 168 void clock_reset_aop(void); 169 int clock_configure_qspi(uint32_t hz); 170 int clock_reset_bcr(void *bcr_addr, bool reset); 171 void clock_configure_uart(uint32_t hz); 172 void clock_configure_i2c(uint32_t hz); 173 void clock_configure_spi(int blsp, int qup, uint32_t hz); 174 void clock_enable_uart(void); 175 void clock_disable_uart(void); 176 void clock_enable_spi(int blsp, int qup); 177 void clock_disable_spi(int blsp, int qup); 178 void clock_enable_i2c(void); 179 void clock_disable_i2c(void); 180 181 #endif // __SOC_QUALCOMM_QCS405_CLOCK_H__ 182