1 /*
2 * Copyright © 2015-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "brw_compiler.h"
25 #include "brw_eu.h"
26 #include "brw_nir.h"
27 #include "brw_private.h"
28 #include "dev/intel_debug.h"
29 #include "compiler/nir/nir.h"
30 #include "util/u_debug.h"
31
32 const struct nir_shader_compiler_options brw_scalar_nir_options = {
33 .avoid_ternary_with_two_constants = true,
34 .compact_arrays = true,
35 .discard_is_demote = true,
36 .divergence_analysis_options =
37 (nir_divergence_single_patch_per_tcs_subgroup |
38 nir_divergence_single_patch_per_tes_subgroup |
39 nir_divergence_shader_record_ptr_uniform),
40 .force_indirect_unrolling = nir_var_function_temp,
41 .has_bfe = true,
42 .has_bfi = true,
43 .has_bfm = true,
44 .has_pack_32_4x8 = true,
45 .has_uclz = true,
46 .lower_base_vertex = true,
47 .lower_bitfield_extract = true,
48 .lower_bitfield_insert = true,
49 .lower_device_index_to_zero = true,
50 .lower_fdiv = true,
51 .lower_fisnormal = true,
52 .lower_flrp16 = true,
53 .lower_flrp64 = true,
54 .lower_fmod = true,
55 .lower_hadd64 = true,
56 .lower_insert_byte = true,
57 .lower_insert_word = true,
58 .lower_isign = true,
59 .lower_ldexp = true,
60 .lower_pack_half_2x16 = true,
61 .lower_pack_snorm_2x16 = true,
62 .lower_pack_snorm_4x8 = true,
63 .lower_pack_unorm_2x16 = true,
64 .lower_pack_unorm_4x8 = true,
65 .lower_scmp = true,
66 .lower_to_scalar = true,
67 .lower_uadd_carry = true,
68 .lower_ufind_msb = true,
69 .lower_uniforms_to_ubo = true,
70 .lower_unpack_half_2x16 = true,
71 .lower_unpack_snorm_2x16 = true,
72 .lower_unpack_snorm_4x8 = true,
73 .lower_unpack_unorm_2x16 = true,
74 .lower_unpack_unorm_4x8 = true,
75 .lower_usub_borrow = true,
76 .max_unroll_iterations = 32,
77 .support_16bit_alu = true,
78 .vectorize_io = true,
79 .vectorize_tess_levels = true,
80 .vertex_id_zero_based = true,
81 .scalarize_ddx = true,
82 .support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
83 .support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
84 .per_view_unique_driver_locations = true,
85 .compact_view_index = true,
86 };
87
88 struct brw_compiler *
brw_compiler_create(void * mem_ctx,const struct intel_device_info * devinfo)89 brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
90 {
91 struct brw_compiler *compiler = rzalloc(mem_ctx, struct brw_compiler);
92 assert(devinfo->ver >= 9);
93
94 compiler->devinfo = devinfo;
95
96 brw_init_isa_info(&compiler->isa, devinfo);
97
98 brw_fs_alloc_reg_sets(compiler);
99
100 compiler->precise_trig = debug_get_bool_option("INTEL_PRECISE_TRIG", false);
101
102 compiler->use_tcs_multi_patch = devinfo->ver >= 12;
103
104 compiler->indirect_ubos_use_sampler = devinfo->ver < 12;
105
106 compiler->lower_dpas = devinfo->verx10 < 125 ||
107 intel_device_info_is_mtl(devinfo) ||
108 (intel_device_info_is_arl(devinfo) &&
109 devinfo->platform != INTEL_PLATFORM_ARL_H) ||
110 debug_get_bool_option("INTEL_LOWER_DPAS", false);
111
112 nir_lower_int64_options int64_options =
113 nir_lower_imul64 |
114 nir_lower_isign64 |
115 nir_lower_divmod64 |
116 nir_lower_imul_high64 |
117 nir_lower_find_lsb64 |
118 nir_lower_ufind_msb64 |
119 nir_lower_bit_count64 |
120 nir_lower_iadd3_64;
121 nir_lower_doubles_options fp64_options =
122 nir_lower_drcp |
123 nir_lower_dsqrt |
124 nir_lower_drsq |
125 nir_lower_dsign |
126 nir_lower_dtrunc |
127 nir_lower_dfloor |
128 nir_lower_dceil |
129 nir_lower_dfract |
130 nir_lower_dround_even |
131 nir_lower_dmod |
132 nir_lower_dsub |
133 nir_lower_ddiv;
134
135 if (!devinfo->has_64bit_float || INTEL_DEBUG(DEBUG_SOFT64))
136 fp64_options |= nir_lower_fp64_full_software;
137 if (!devinfo->has_64bit_int)
138 int64_options |= (nir_lower_int64_options)~0;
139
140 /* The Bspec's section titled "Instruction_multiply[DevBDW+]" claims that
141 * destination type can be Quadword and source type Doubleword for Gfx8 and
142 * Gfx9. So, lower 64 bit multiply instruction on rest of the platforms.
143 */
144 if (devinfo->ver > 9)
145 int64_options |= nir_lower_imul_2x32_64;
146
147 if (devinfo->ver >= 20)
148 int64_options |= (nir_lower_icmp64 | nir_lower_minmax64 |
149 nir_lower_logic64 | nir_lower_ufind_msb64 |
150 nir_lower_bit_count64 |
151 nir_lower_bcsel64 |
152 nir_lower_extract64 | nir_lower_scan_reduce_bitwise64 |
153 nir_lower_scan_reduce_iadd64 | nir_lower_subgroup_shuffle64 |
154 nir_lower_iadd_sat64 | nir_lower_uadd_sat64);
155
156 /* We want the GLSL compiler to emit code that uses condition codes */
157 for (int i = 0; i < MESA_ALL_SHADER_STAGES; i++) {
158 struct nir_shader_compiler_options *nir_options =
159 rzalloc(compiler, struct nir_shader_compiler_options);
160 *nir_options = brw_scalar_nir_options;
161 int64_options |= nir_lower_usub_sat64;
162
163 /* Gfx11 loses LRP. */
164 nir_options->lower_flrp32 = devinfo->ver >= 11;
165
166 nir_options->lower_fpow = devinfo->ver >= 12;
167
168 nir_options->has_rotate16 = devinfo->ver >= 11;
169 nir_options->has_rotate32 = devinfo->ver >= 11;
170 nir_options->has_iadd3 = devinfo->verx10 >= 125;
171
172 nir_options->has_sdot_4x8 = devinfo->ver >= 12;
173 nir_options->has_udot_4x8 = devinfo->ver >= 12;
174 nir_options->has_sudot_4x8 = devinfo->ver >= 12;
175 nir_options->has_sdot_4x8_sat = devinfo->ver >= 12;
176 nir_options->has_udot_4x8_sat = devinfo->ver >= 12;
177 nir_options->has_sudot_4x8_sat = devinfo->ver >= 12;
178
179 nir_options->lower_int64_options = int64_options;
180 nir_options->lower_doubles_options = fp64_options;
181
182 nir_options->unify_interfaces = i < MESA_SHADER_FRAGMENT;
183
184 nir_options->force_indirect_unrolling |=
185 brw_nir_no_indirect_mask(compiler, i);
186
187 if (compiler->use_tcs_multi_patch) {
188 /* TCS MULTI_PATCH mode has multiple patches per subgroup */
189 nir_options->divergence_analysis_options &=
190 ~nir_divergence_single_patch_per_tcs_subgroup;
191 }
192
193 if (devinfo->ver < 12)
194 nir_options->divergence_analysis_options |=
195 nir_divergence_single_prim_per_subgroup;
196
197 compiler->nir_options[i] = nir_options;
198 }
199
200 compiler->mesh.mue_header_packing =
201 (unsigned)debug_get_num_option("INTEL_MESH_HEADER_PACKING", 3);
202 compiler->mesh.mue_compaction =
203 debug_get_bool_option("INTEL_MESH_COMPACTION", true);
204
205 return compiler;
206 }
207
208 static void
insert_u64_bit(uint64_t * val,bool add)209 insert_u64_bit(uint64_t *val, bool add)
210 {
211 *val = (*val << 1) | !!add;
212 }
213
214 uint64_t
brw_get_compiler_config_value(const struct brw_compiler * compiler)215 brw_get_compiler_config_value(const struct brw_compiler *compiler)
216 {
217 uint64_t config = 0;
218 unsigned bits = 0;
219
220 insert_u64_bit(&config, compiler->precise_trig);
221 bits++;
222 insert_u64_bit(&config, compiler->lower_dpas);
223 bits++;
224 insert_u64_bit(&config, compiler->mesh.mue_compaction);
225 bits++;
226
227 uint64_t mask = DEBUG_DISK_CACHE_MASK;
228 bits += util_bitcount64(mask);
229
230 u_foreach_bit64(bit, mask)
231 insert_u64_bit(&config, INTEL_DEBUG(1ULL << bit));
232
233 mask = SIMD_DISK_CACHE_MASK;
234 bits += util_bitcount64(mask);
235
236 u_foreach_bit64(bit, mask)
237 insert_u64_bit(&config, (intel_simd & (1ULL << bit)) != 0);
238
239 mask = 3;
240 bits += util_bitcount64(mask);
241
242 u_foreach_bit64(bit, mask)
243 insert_u64_bit(&config, (compiler->mesh.mue_header_packing & (1ULL << bit)) != 0);
244
245 assert(bits <= util_bitcount64(UINT64_MAX));
246
247 return config;
248 }
249
250 void
brw_device_sha1(char * hex,const struct intel_device_info * devinfo)251 brw_device_sha1(char *hex,
252 const struct intel_device_info *devinfo) {
253 struct mesa_sha1 ctx;
254 _mesa_sha1_init(&ctx);
255 brw_device_sha1_update(&ctx, devinfo);
256 unsigned char result[20];
257 _mesa_sha1_final(&ctx, result);
258 _mesa_sha1_format(hex, result);
259 }
260
261 unsigned
brw_prog_data_size(gl_shader_stage stage)262 brw_prog_data_size(gl_shader_stage stage)
263 {
264 static const size_t stage_sizes[] = {
265 [MESA_SHADER_VERTEX] = sizeof(struct brw_vs_prog_data),
266 [MESA_SHADER_TESS_CTRL] = sizeof(struct brw_tcs_prog_data),
267 [MESA_SHADER_TESS_EVAL] = sizeof(struct brw_tes_prog_data),
268 [MESA_SHADER_GEOMETRY] = sizeof(struct brw_gs_prog_data),
269 [MESA_SHADER_FRAGMENT] = sizeof(struct brw_wm_prog_data),
270 [MESA_SHADER_COMPUTE] = sizeof(struct brw_cs_prog_data),
271 [MESA_SHADER_TASK] = sizeof(struct brw_task_prog_data),
272 [MESA_SHADER_MESH] = sizeof(struct brw_mesh_prog_data),
273 [MESA_SHADER_RAYGEN] = sizeof(struct brw_bs_prog_data),
274 [MESA_SHADER_ANY_HIT] = sizeof(struct brw_bs_prog_data),
275 [MESA_SHADER_CLOSEST_HIT] = sizeof(struct brw_bs_prog_data),
276 [MESA_SHADER_MISS] = sizeof(struct brw_bs_prog_data),
277 [MESA_SHADER_INTERSECTION] = sizeof(struct brw_bs_prog_data),
278 [MESA_SHADER_CALLABLE] = sizeof(struct brw_bs_prog_data),
279 [MESA_SHADER_KERNEL] = sizeof(struct brw_cs_prog_data),
280 };
281 assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
282 return stage_sizes[stage];
283 }
284
285 unsigned
brw_prog_key_size(gl_shader_stage stage)286 brw_prog_key_size(gl_shader_stage stage)
287 {
288 static const size_t stage_sizes[] = {
289 [MESA_SHADER_VERTEX] = sizeof(struct brw_vs_prog_key),
290 [MESA_SHADER_TESS_CTRL] = sizeof(struct brw_tcs_prog_key),
291 [MESA_SHADER_TESS_EVAL] = sizeof(struct brw_tes_prog_key),
292 [MESA_SHADER_GEOMETRY] = sizeof(struct brw_gs_prog_key),
293 [MESA_SHADER_FRAGMENT] = sizeof(struct brw_wm_prog_key),
294 [MESA_SHADER_COMPUTE] = sizeof(struct brw_cs_prog_key),
295 [MESA_SHADER_TASK] = sizeof(struct brw_task_prog_key),
296 [MESA_SHADER_MESH] = sizeof(struct brw_mesh_prog_key),
297 [MESA_SHADER_RAYGEN] = sizeof(struct brw_bs_prog_key),
298 [MESA_SHADER_ANY_HIT] = sizeof(struct brw_bs_prog_key),
299 [MESA_SHADER_CLOSEST_HIT] = sizeof(struct brw_bs_prog_key),
300 [MESA_SHADER_MISS] = sizeof(struct brw_bs_prog_key),
301 [MESA_SHADER_INTERSECTION] = sizeof(struct brw_bs_prog_key),
302 [MESA_SHADER_CALLABLE] = sizeof(struct brw_bs_prog_key),
303 [MESA_SHADER_KERNEL] = sizeof(struct brw_cs_prog_key),
304 };
305 assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
306 return stage_sizes[stage];
307 }
308
309 void
brw_write_shader_relocs(const struct brw_isa_info * isa,void * program,const struct brw_stage_prog_data * prog_data,struct brw_shader_reloc_value * values,unsigned num_values)310 brw_write_shader_relocs(const struct brw_isa_info *isa,
311 void *program,
312 const struct brw_stage_prog_data *prog_data,
313 struct brw_shader_reloc_value *values,
314 unsigned num_values)
315 {
316 for (unsigned i = 0; i < prog_data->num_relocs; i++) {
317 assert(prog_data->relocs[i].offset % 8 == 0);
318 void *dst = program + prog_data->relocs[i].offset;
319 for (unsigned j = 0; j < num_values; j++) {
320 if (prog_data->relocs[i].id == values[j].id) {
321 uint32_t value = values[j].value + prog_data->relocs[i].delta;
322 switch (prog_data->relocs[i].type) {
323 case BRW_SHADER_RELOC_TYPE_U32:
324 *(uint32_t *)dst = value;
325 break;
326 case BRW_SHADER_RELOC_TYPE_MOV_IMM:
327 brw_update_reloc_imm(isa, dst, value);
328 break;
329 default:
330 unreachable("Invalid relocation type");
331 }
332 break;
333 }
334 }
335 }
336 }
337
338 void
brw_stage_prog_data_add_printf(struct brw_stage_prog_data * prog_data,void * mem_ctx,const u_printf_info * print)339 brw_stage_prog_data_add_printf(struct brw_stage_prog_data *prog_data,
340 void *mem_ctx,
341 const u_printf_info *print)
342 {
343 prog_data->printf_info_count++;
344 prog_data->printf_info = reralloc(mem_ctx, prog_data->printf_info,
345 u_printf_info,
346 prog_data->printf_info_count);
347
348 prog_data->printf_info[prog_data->printf_info_count - 1] = *print;
349 if (print->string_size > 0) {
350 prog_data->printf_info[prog_data->printf_info_count - 1].strings =
351 ralloc_size(mem_ctx, print->string_size);
352 memcpy(prog_data->printf_info[prog_data->printf_info_count - 1].strings,
353 print->strings, print->string_size);
354 }
355 if (print->num_args > 0) {
356 prog_data->printf_info[prog_data->printf_info_count - 1].arg_sizes =
357 ralloc_array(mem_ctx, __typeof__(*print->arg_sizes), print->num_args);
358 memcpy(prog_data->printf_info[prog_data->printf_info_count - 1].arg_sizes,
359 print->arg_sizes, sizeof(print->arg_sizes[0]) *print->num_args);
360 }
361 }
362