1/* 2 * Copyright (c) 2017-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cortex_a75.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13.global check_erratum_cortex_a75_764081 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20workaround_reset_start cortex_a75, ERRATUM(764081), ERRATA_A75_764081 21 sysreg_bit_set sctlr_el3, SCTLR_IESB_BIT 22workaround_reset_end cortex_a75, ERRATUM(764081) 23 24check_erratum_ls cortex_a75, ERRATUM(764081), CPU_REV(0, 0) 25 26workaround_reset_start cortex_a75, ERRATUM(790748), ERRATA_A75_790748 27 sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, (1 << 13) 28workaround_reset_end cortex_a75, ERRATUM(790748) 29 30check_erratum_ls cortex_a75, ERRATUM(790748), CPU_REV(0, 0) 31 32/* ERRATA_DSU_798953 : 33 * The errata is defined in dsu_helpers.S but applies to cortex_a75 34 * as well. Henceforth creating symbolic names to the already existing errata 35 * workaround functions to get them registered under the Errata Framework. 36 */ 37.equ check_erratum_cortex_a75_798953, check_errata_dsu_798953 38.equ erratum_cortex_a75_798953_wa, errata_dsu_798953_wa 39add_erratum_entry cortex_a75, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET 40 41/* ERRATA_DSU_936184 : 42 * The errata is defined in dsu_helpers.S but applies to cortex_a75 43 * as well. Henceforth creating symbolic names to the already existing errata 44 * workaround functions to get them registered under the Errata Framework. 45 */ 46.equ check_erratum_cortex_a75_936184, check_errata_dsu_936184 47.equ erratum_cortex_a75_936184_wa, errata_dsu_936184_wa 48add_erratum_entry cortex_a75, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET 49 50workaround_reset_start cortex_a75, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 51#if IMAGE_BL31 52 override_vector_table wa_cve_2017_5715_bpiall_vbar 53#endif /* IMAGE_BL31 */ 54workaround_reset_end cortex_a75, CVE(2017, 5715) 55 56check_erratum_custom_start cortex_a75, CVE(2017, 5715) 57 cpu_check_csv2 x0, 1f 58#if WORKAROUND_CVE_2017_5715 59 mov x0, #ERRATA_APPLIES 60#else 61 mov x0, #ERRATA_MISSING 62#endif 63 ret 641: 65 mov x0, #ERRATA_NOT_APPLIES 66 ret 67check_erratum_custom_end cortex_a75, CVE(2017, 5715) 68 69workaround_reset_start cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 70 sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE 71workaround_reset_end cortex_a75, CVE(2018, 3639) 72 73check_erratum_chosen cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 74 75workaround_reset_start cortex_a75, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 76#if IMAGE_BL31 77 /* Skip installing vector table again if already done for CVE(2017, 5715) */ 78 adr x0, wa_cve_2017_5715_bpiall_vbar 79 mrs x1, vbar_el3 80 cmp x0, x1 81 b.eq 1f 82 msr vbar_el3, x0 831: 84#endif /* IMAGE_BL31 */ 85workaround_reset_end cortex_a75, CVE(2022, 23960) 86 87check_erratum_custom_start cortex_a75, CVE(2022, 23960) 88#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 89 cpu_check_csv2 x0, 1f 90 mov x0, #ERRATA_APPLIES 91 ret 921: 93# if WORKAROUND_CVE_2022_23960 94 mov x0, #ERRATA_APPLIES 95# else 96 mov x0, #ERRATA_MISSING 97# endif /* WORKAROUND_CVE_2022_23960 */ 98 ret 99#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ 100 mov x0, #ERRATA_MISSING 101 ret 102check_erratum_custom_end cortex_a75, CVE(2022, 23960) 103 104 /* ------------------------------------------------- 105 * The CPU Ops reset function for Cortex-A75. 106 * ------------------------------------------------- 107 */ 108 109cpu_reset_func_start cortex_a75 110#if ENABLE_FEAT_AMU 111 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 112 sysreg_bit_set actlr_el3, CORTEX_A75_ACTLR_AMEN_BIT 113 isb 114 115 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 116 sysreg_bit_set actlr_el2, CORTEX_A75_ACTLR_AMEN_BIT 117 isb 118 119 /* Enable group0 counters */ 120 mov x0, #CORTEX_A75_AMU_GROUP0_MASK 121 msr CPUAMCNTENSET_EL0, x0 122 isb 123 124 /* Enable group1 counters */ 125 mov x0, #CORTEX_A75_AMU_GROUP1_MASK 126 msr CPUAMCNTENSET_EL0, x0 127 /* isb included in cpu_reset_func_end macro */ 128#endif 129cpu_reset_func_end cortex_a75 130 131func check_smccc_arch_workaround_3 132 mov x0, #ERRATA_APPLIES 133 ret 134endfunc check_smccc_arch_workaround_3 135 136 /* --------------------------------------------- 137 * HW will do the cache maintenance while powering down 138 * --------------------------------------------- 139 */ 140func cortex_a75_core_pwr_dwn 141 /* --------------------------------------------- 142 * Enable CPU power down bit in power control register 143 * --------------------------------------------- 144 */ 145 sysreg_bit_set CORTEX_A75_CPUPWRCTLR_EL1, \ 146 CORTEX_A75_CORE_PWRDN_EN_MASK 147 isb 148 ret 149endfunc cortex_a75_core_pwr_dwn 150 151 /* --------------------------------------------- 152 * This function provides cortex_a75 specific 153 * register information for crash reporting. 154 * It needs to return with x6 pointing to 155 * a list of register names in ascii and 156 * x8 - x15 having values of registers to be 157 * reported. 158 * --------------------------------------------- 159 */ 160.section .rodata.cortex_a75_regs, "aS" 161cortex_a75_regs: /* The ascii list of register names to be reported */ 162 .asciz "cpuectlr_el1", "" 163 164func cortex_a75_cpu_reg_dump 165 adr x6, cortex_a75_regs 166 mrs x8, CORTEX_A75_CPUECTLR_EL1 167 ret 168endfunc cortex_a75_cpu_reg_dump 169 170declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \ 171 cortex_a75_reset_func, \ 172 check_erratum_cortex_a75_5715, \ 173 CPU_NO_EXTRA2_FUNC, \ 174 check_smccc_arch_workaround_3, \ 175 cortex_a75_core_pwr_dwn 176