1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_ROCKCHIP_RK3399_SDRAM_H__ 4 #define __SOC_ROCKCHIP_RK3399_SDRAM_H__ 5 6 #include <types.h> 7 8 enum { 9 DDR3 = 3, 10 LPDDR2 = 5, 11 LPDDR3 = 6, 12 LPDDR4 = 7, 13 UNUSED = 0xFF 14 }; 15 16 struct rk3399_ddr_pctl_regs { 17 u32 denali_ctl[332]; 18 }; 19 20 struct rk3399_ddr_publ_regs { 21 u32 denali_phy[959]; 22 }; 23 24 struct rk3399_ddr_pi_regs { 25 u32 denali_pi[200]; 26 }; 27 union noc_ddrtiminga0 { 28 u32 d32; 29 struct { 30 unsigned int acttoact : 6; 31 unsigned int reserved0 : 2; 32 unsigned int rdtomiss : 6; 33 unsigned int reserved1 : 2; 34 unsigned int wrtomiss : 6; 35 unsigned int reserved2 : 2; 36 unsigned int readlatency : 8; 37 } b; 38 }; 39 40 union noc_ddrtimingb0 { 41 u32 d32; 42 struct { 43 unsigned int rdtowr : 5; 44 unsigned int reserved0 : 3; 45 unsigned int wrtord : 5; 46 unsigned int reserved1 : 3; 47 unsigned int rrd : 4; 48 unsigned int reserved2 : 4; 49 unsigned int faw : 6; 50 unsigned int reserved3 : 2; 51 } b; 52 }; 53 54 union noc_ddrtimingc0 { 55 u32 d32; 56 struct { 57 unsigned int burstpenalty : 4; 58 unsigned int reserved0 : 4; 59 unsigned int wrtomwr : 6; 60 unsigned int reserved1 : 18; 61 } b; 62 }; 63 64 union noc_devtodev0 { 65 u32 d32; 66 struct { 67 unsigned int busrdtord : 3; 68 unsigned int reserved0 : 1; 69 unsigned int busrdtowr : 3; 70 unsigned int reserved1 : 1; 71 unsigned int buswrtord : 3; 72 unsigned int reserved2 : 1; 73 unsigned int buswrtowr : 3; 74 unsigned int reserved3 : 17; 75 } b; 76 }; 77 78 union noc_ddrmode { 79 u32 d32; 80 struct { 81 unsigned int autoprecharge : 1; 82 unsigned int bypassfiltering : 1; 83 unsigned int fawbank : 1; 84 unsigned int burstsize : 2; 85 unsigned int mwrsize : 2; 86 unsigned int reserved2 : 1; 87 unsigned int forceorder : 8; 88 unsigned int forceorderstate : 8; 89 unsigned int reserved3 : 8; 90 } b; 91 }; 92 93 struct rk3399_msch_regs { 94 u32 coreid; 95 u32 revisionid; 96 u32 ddrconf; 97 u32 ddrsize; 98 union noc_ddrtiminga0 ddrtiminga0; 99 union noc_ddrtimingb0 ddrtimingb0; 100 union noc_ddrtimingc0 ddrtimingc0; 101 union noc_devtodev0 devtodev0; 102 u32 reserved0[(0x110-0x20)/4]; 103 union noc_ddrmode ddrmode; 104 u32 reserved1[(0x1000-0x114)/4]; 105 u32 agingx0; 106 }; 107 108 struct rk3399_msch_timings { 109 union noc_ddrtiminga0 ddrtiminga0; 110 union noc_ddrtimingb0 ddrtimingb0; 111 union noc_ddrtimingc0 ddrtimingc0; 112 union noc_devtodev0 devtodev0; 113 union noc_ddrmode ddrmode; 114 u32 agingx0; 115 }; 116 117 struct rk3399_ddr_cic_regs { 118 u32 cic_ctrl0; 119 u32 cic_ctrl1; 120 u32 cic_idle_th; 121 u32 cic_cg_wait_th; 122 u32 cic_status0; 123 u32 cic_status1; 124 u32 cic_ctrl2; 125 u32 cic_ctrl3; 126 u32 cic_ctrl4; 127 }; 128 129 /* DENALI_CTL_00 */ 130 #define START (1) 131 132 /* DENALI_CTL_68 */ 133 #define PWRUP_SREFRESH_EXIT (1 << 16) 134 135 /* DENALI_CTL_274 */ 136 #define MEM_RST_VALID (1) 137 138 struct rk3399_sdram_channel { 139 unsigned char rank; 140 /* col = 0, means this channel is invalid */ 141 unsigned char col; 142 /* 3:8bank, 2:4bank */ 143 unsigned char bk; 144 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ 145 unsigned char bw; 146 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ 147 unsigned char dbw; 148 /* row_3_4 = 1: 6Gb or 12Gb die 149 * row_3_4 = 0: normal die, power of 2 150 */ 151 unsigned char row_3_4; 152 unsigned char cs0_row; 153 unsigned char cs1_row; 154 unsigned int ddrconfig; 155 struct rk3399_msch_timings noc_timings; 156 }; 157 158 struct rk3399_sdram_params { 159 struct rk3399_sdram_channel ch[2]; 160 unsigned int ddr_freq; 161 unsigned char dramtype; 162 unsigned char num_channels; 163 unsigned char stride; 164 unsigned char odt; 165 /* align 8 byte */ 166 struct rk3399_ddr_pctl_regs pctl_regs; 167 /* align 8 byte */ 168 struct rk3399_ddr_pi_regs pi_regs; 169 /* align 8 byte */ 170 struct rk3399_ddr_publ_regs phy_regs; 171 /* used for align 8byte for next struct */ 172 unsigned int align_8; 173 }; 174 175 #define PI_CA_TRAINING (1 << 0) 176 #define PI_WRITE_LEVELING (1 << 1) 177 #define PI_READ_GATE_TRAINING (1 << 2) 178 #define PI_READ_LEVELING (1 << 3) 179 #define PI_WDQ_LEVELING (1 << 4) 180 #define PI_FULL_TRAINING (0xff) 181 182 void sdram_init(const struct rk3399_sdram_params *sdram_params); 183 u32 sdram_get_ram_code(void); 184 const struct rk3399_sdram_params *get_sdram_config(void); 185 size_t sdram_size_mb(void); 186 187 #endif 188