1 /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2 3 #ifndef __MT8188_SOC_PMIF_H__ 4 #define __MT8188_SOC_PMIF_H__ 5 6 #include <device/mmio.h> 7 #include <soc/pmif_common.h> 8 #include <types.h> 9 10 /* indicate which number SW channel start, by project */ 11 #define PMIF_SPMI_SW_CHAN BIT(6) 12 #define PMIF_SPMI_INF 0x5E7 13 14 struct mtk_pmif_regs { 15 u32 init_done; 16 u32 reserved1[5]; 17 u32 inf_busy_sta; 18 u32 other_busy_sta_0; 19 u32 other_busy_sta_1; 20 u32 inf_en; 21 u32 other_inf_en; 22 u32 inf_cmd_per_0; 23 u32 inf_cmd_per_1; 24 u32 inf_cmd_per_2; 25 u32 inf_cmd_per_3; 26 u32 inf_max_bytecnt_per_0; 27 u32 inf_max_bytecnt_per_1; 28 u32 inf_max_bytecnt_per_2; 29 u32 inf_max_bytecnt_per_3; 30 u32 staupd_ctrl; 31 u32 reserved2[48]; 32 u32 int_gps_auxadc_cmd_addr; 33 u32 int_gps_auxadc_cmd; 34 u32 int_gps_auxadc_rdata_addr; 35 u32 reserved3[13]; 36 u32 arb_en; 37 u32 reserved4[34]; 38 u32 lat_cnter_ctrl; 39 u32 lat_cnter_en; 40 u32 lat_limit_loading; 41 u32 lat_limit_0; 42 u32 lat_limit_1; 43 u32 lat_limit_2; 44 u32 lat_limit_3; 45 u32 lat_limit_4; 46 u32 lat_limit_5; 47 u32 lat_limit_6; 48 u32 lat_limit_7; 49 u32 lat_limit_8; 50 u32 lat_limit_9; 51 u32 reserved5[99]; 52 u32 crc_ctrl; 53 u32 crc_sta; 54 u32 sig_mode; 55 u32 pmic_sig_addr; 56 u32 pmic_sig_val; 57 u32 reserved6[2]; 58 u32 cmdissue_en; 59 u32 reserved7[10]; 60 u32 timer_ctrl; 61 u32 timer_sta; 62 u32 sleep_protection_ctrl; 63 u32 reserved8[6]; 64 u32 spi_mode_ctrl; 65 u32 reserved9[2]; 66 u32 pmic_eint_sta_addr; 67 u32 reserved10[2]; 68 u32 irq_event_en_0; 69 u32 irq_flag_raw_0; 70 u32 irq_flag_0; 71 u32 irq_clr_0; 72 u32 reserved11[244]; 73 u32 swinf_0_acc; 74 u32 swinf_0_wdata_31_0; 75 u32 swinf_0_wdata_63_32; 76 u32 reserved12[2]; 77 u32 swinf_0_rdata_31_0; 78 u32 swinf_0_rdata_63_32; 79 u32 reserved13[2]; 80 u32 swinf_0_vld_clr; 81 u32 swinf_0_sta; 82 u32 reserved14[5]; 83 u32 swinf_1_acc; 84 u32 swinf_1_wdata_31_0; 85 u32 swinf_1_wdata_63_32; 86 u32 reserved15[2]; 87 u32 swinf_1_rdata_31_0; 88 u32 swinf_1_rdata_63_32; 89 u32 reserved16[2]; 90 u32 swinf_1_vld_clr; 91 u32 swinf_1_sta; 92 u32 reserved17[5]; 93 u32 swinf_2_acc; 94 u32 swinf_2_wdata_31_0; 95 u32 swinf_2_wdata_63_32; 96 u32 reserved18[2]; 97 u32 swinf_2_rdata_31_0; 98 u32 swinf_2_rdata_63_32; 99 u32 reserved19[2]; 100 u32 swinf_2_vld_clr; 101 u32 swinf_2_sta; 102 u32 reserved20[5]; 103 u32 swinf_3_acc; 104 u32 swinf_3_wdata_31_0; 105 u32 swinf_3_wdata_63_32; 106 u32 reserved21[2]; 107 u32 swinf_3_rdata_31_0; 108 u32 swinf_3_rdata_63_32; 109 u32 reserved22[2]; 110 u32 swinf_3_vld_clr; 111 u32 swinf_3_sta; 112 u32 reserved23[133]; 113 }; 114 115 check_member(mtk_pmif_regs, inf_busy_sta, 0x18); 116 check_member(mtk_pmif_regs, int_gps_auxadc_cmd_addr, 0x110); 117 check_member(mtk_pmif_regs, arb_en, 0x0150); 118 check_member(mtk_pmif_regs, lat_cnter_en, 0x1E0); 119 check_member(mtk_pmif_regs, crc_ctrl, 0x39C); 120 check_member(mtk_pmif_regs, cmdissue_en, 0x3B8); 121 check_member(mtk_pmif_regs, timer_ctrl, 0x3E4); 122 check_member(mtk_pmif_regs, spi_mode_ctrl, 0x408); 123 check_member(mtk_pmif_regs, pmic_eint_sta_addr, 0x414); 124 check_member(mtk_pmif_regs, irq_event_en_0, 0x420); 125 check_member(mtk_pmif_regs, swinf_0_acc, 0x800); 126 127 #define PMIF_SPMI_AP_CHAN (PMIF_SPMI_BASE + 0x880) 128 #define PMIF_SPI_AP_CHAN (PMIF_SPI_BASE + 0x880) 129 130 struct mtk_clk_monitor_regs { 131 u32 clk_monitor_ctrl; 132 }; 133 134 #define mtk_clk_monitor ((struct mtk_clk_monitor_regs *)EFUSE_BASE + 0x45C) 135 136 enum { 137 FREQ_260MHZ = 260, 138 }; 139 140 #define FREQ_METER_ABIST_AD_OSC_CK 42 141 #define CALI_DEFAULT_CAP_VALUE 0x3d 142 143 #endif /*__MT8188_SOC_PMIF_H__*/ 144