1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _SOC_CHIP_H_ 4 #define _SOC_CHIP_H_ 5 6 #include <device/pci_ids.h> 7 #include <drivers/i2c/designware/dw_i2c.h> 8 #include <gpio.h> 9 #include <drivers/intel/gma/gma.h> 10 #include <intelblocks/cfg.h> 11 #include <intelblocks/gspi.h> 12 #include <intelblocks/pcie_rp.h> 13 #include <intelblocks/power_limit.h> 14 #include <intelblocks/xhci.h> 15 #include <soc/gpe.h> 16 #include <soc/pch.h> 17 #include <soc/pci_devs.h> 18 #include <soc/pcie_modphy.h> 19 #include <soc/pmc.h> 20 #include <soc/serialio.h> 21 #include <soc/usb.h> 22 #include <stdint.h> 23 #include <stdbool.h> 24 25 #define MAX_HD_AUDIO_DMIC_LINKS 2 26 #define MAX_HD_AUDIO_SNDW_LINKS 4 27 #define MAX_HD_AUDIO_SSP_LINKS 6 28 29 /* Types of different SKUs */ 30 enum soc_intel_jasperlake_power_limits { 31 JSL_N4500_6W_CORE, 32 JSL_N6000_6W_CORE, 33 JSL_N5100_6W_CORE, 34 JSL_N4505_10W_CORE, 35 JSL_N5105_10W_CORE, 36 JSL_N6005_10W_CORE, 37 JSL_POWER_LIMITS_COUNT 38 }; 39 40 /* TDP values for different SKUs */ 41 enum soc_intel_jasperlake_cpu_tdps { 42 TDP_6W = 6, 43 TDP_10W = 10 44 }; 45 46 /* Mapping of different SKUs based on CPU ID and TDP values */ 47 static const struct { 48 unsigned int pci_did; 49 enum soc_intel_jasperlake_power_limits limits; 50 enum soc_intel_jasperlake_cpu_tdps cpu_tdp; 51 } cpuid_to_jsl[] = { 52 { PCI_DID_INTEL_JSL_ID_1, JSL_N4500_6W_CORE, TDP_6W }, 53 { PCI_DID_INTEL_JSL_ID_2, JSL_N6000_6W_CORE, TDP_6W }, 54 { PCI_DID_INTEL_JSL_ID_3, JSL_N5100_6W_CORE, TDP_6W }, 55 { PCI_DID_INTEL_JSL_ID_4, JSL_N4505_10W_CORE, TDP_10W }, 56 { PCI_DID_INTEL_JSL_ID_5, JSL_N5105_10W_CORE, TDP_10W }, 57 { PCI_DID_INTEL_JSL_ID_6, JSL_N6005_10W_CORE, TDP_10W }, 58 }; 59 60 struct soc_intel_jasperlake_config { 61 /* Common struct containing soc config data required by common code */ 62 struct soc_intel_common_config common_soc_config; 63 64 /* Common struct containing power limits configuration information */ 65 struct soc_power_limits_config power_limits_config[JSL_POWER_LIMITS_COUNT]; 66 67 /* Gpio group routed to each dword of the GPE0 block. Values are 68 * of the form PMC_GPP_[A:U] or GPD. */ 69 uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ 70 uint8_t pmc_gpe0_dw1; /* GPE0_63_32 STS/EN */ 71 uint8_t pmc_gpe0_dw2; /* GPE0_95_64 STS/EN */ 72 73 /* Generic IO decode ranges */ 74 uint32_t gen1_dec; 75 uint32_t gen2_dec; 76 uint32_t gen3_dec; 77 uint32_t gen4_dec; 78 79 /* Enable S0iX support */ 80 bool s0ix_enable; 81 /* Enable DPTF support */ 82 bool dptf_enable; 83 84 /* Deep SX enable for both AC and DC */ 85 bool deep_s3_enable_ac; 86 bool deep_s3_enable_dc; 87 bool deep_s5_enable_ac; 88 bool deep_s5_enable_dc; 89 90 /* Deep Sx Configuration 91 * DSX_EN_WAKE_PIN - Enable WAKE# pin 92 * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin 93 * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ 94 uint32_t deep_sx_config; 95 96 /* TCC activation offset */ 97 uint32_t tcc_offset; 98 99 /* System Agent dynamic frequency support. 100 * When enabled memory will be training at different frequencies. 101 * 0:Disabled, 1:FixedPoint0(low), 2:FixedPoint1(mid), 3:FixedPoint2 102 * (high), 4:Enabled */ 103 enum { 104 SaGv_Disabled, 105 SaGv_FixedPoint0, 106 SaGv_FixedPoint1, 107 SaGv_FixedPoint2, 108 SaGv_Enabled, 109 } SaGv; 110 111 /* Rank Margin Tool 112 * 113 * true: Enable 114 * false: Disable 115 */ 116 bool RMT; 117 118 /* USB related */ 119 struct usb2_port_config usb2_ports[16]; 120 struct usb3_port_config usb3_ports[10]; 121 /* Wake Enable Bitmap for USB2 ports */ 122 uint16_t usb2_wake_enable_bitmap; 123 /* Wake Enable Bitmap for USB3 ports */ 124 uint16_t usb3_wake_enable_bitmap; 125 126 /* Set the LFPS periodic sampling off time for USB3 Ports. 127 Default value of PMCTRL_REG bits[7:4] is 9 which means periodic 128 sampling off interval is 9ms, the range is from 0 to 15. */ 129 uint8_t xhci_lfps_sampling_offtime_ms; 130 131 /* SATA related */ 132 uint8_t SataMode; 133 bool SataSalpSupport; 134 bool SataPortsEnable[8]; 135 bool SataPortsDevSlp[8]; 136 137 /* Audio related */ 138 bool PchHdaDspEnable; 139 bool PchHdaAudioLinkHdaEnable; 140 bool PchHdaAudioLinkDmicEnable[MAX_HD_AUDIO_DMIC_LINKS]; 141 bool PchHdaAudioLinkSspEnable[MAX_HD_AUDIO_SSP_LINKS]; 142 bool PchHdaAudioLinkSndwEnable[MAX_HD_AUDIO_SNDW_LINKS]; 143 uint8_t PchHdaIDispLinkTmode; 144 uint8_t PchHdaIDispLinkFrequency; 145 bool PchHdaIDispCodecDisconnect; 146 147 /* PCIe Root Ports */ 148 /* PCIe output clocks type to PCIe devices. 149 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, 150 * 0xFF: not used */ 151 uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC]; 152 /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to 153 * clksrc. */ 154 uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC]; 155 156 /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ 157 bool PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; 158 159 /* PCIe RP L1 substate */ 160 enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; 161 162 /* PCIe ModPhy related */ 163 struct pcie_modphy_config pcie_mp_cfg[CONFIG_MAX_ROOT_PORTS]; 164 165 /* SMBus */ 166 bool SmbusEnable; 167 168 /* eMMC and SD */ 169 bool ScsEmmcHs400Enabled; 170 171 /* Enable if SD Card Power Enable Signal is Active High */ 172 bool SdCardPowerEnableActiveHigh; 173 174 /* VR Config Settings for IA Core */ 175 uint16_t ImonSlope; 176 uint16_t ImonOffset; 177 178 /* Gfx related */ 179 bool SkipExtGfxScan; 180 181 /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ 182 bool eist_enable; 183 184 /* Enable C6 DRAM */ 185 bool enable_c6dram; 186 187 /* 188 * SerialIO device mode selection: 189 * PchSerialIoDisabled, 190 * PchSerialIoPci, 191 * PchSerialIoHidden, 192 * PchSerialIoLegacyUart, 193 * PchSerialIoSkipInit 194 */ 195 uint8_t SerialIoI2cMode[CONFIG_SOC_INTEL_I2C_DEV_MAX]; 196 uint8_t SerialIoGSpiMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; 197 uint8_t SerialIoUartMode[CONFIG_SOC_INTEL_UART_DEV_MAX]; 198 /* 199 * GSPIn Default Chip Select Mode: 200 * 0:Hardware Mode, 201 * 1:Software Mode 202 */ 203 uint8_t SerialIoGSpiCsMode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; 204 /* 205 * GSPIn Default Chip Select State: 206 * 0: Low, 207 * 1: High 208 */ 209 uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX]; 210 211 /* 212 * TraceHubMode config 213 * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode 214 */ 215 uint8_t TraceHubMode; 216 217 /* Debug interface selection */ 218 enum { 219 DEBUG_INTERFACE_RAM = (1 << 0), 220 DEBUG_INTERFACE_UART_8250IO = (1 << 1), 221 DEBUG_INTERFACE_USB3 = (1 << 3), 222 DEBUG_INTERFACE_LPSS_SERIAL_IO = (1 << 4), 223 DEBUG_INTERFACE_TRACEHUB = (1 << 5), 224 } debug_interface_flag; 225 226 /* GPIO SD card detect pin */ 227 unsigned int sdcard_cd_gpio; 228 229 /* Enable Pch iSCLK */ 230 bool pch_isclk; 231 232 /* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */ 233 bool CnviBtAudioOffload; 234 235 /* Tcss */ 236 bool TcssXhciEn; 237 bool TcssXdciEn; 238 239 /* 240 * Override GPIO PM configuration: 241 * false: Use FSP default GPIO PM program, 242 * true: coreboot to override GPIO PM program 243 */ 244 bool gpio_override_pm; 245 246 /* 247 * GPIO PM configuration: 0 to disable, 1 to enable power gating 248 * Bit 6-7: Reserved 249 * Bit 5: MISCCFG_GPSIDEDPCGEN 250 * Bit 4: MISCCFG_GPRCOMPCDLCGEN 251 * Bit 3: MISCCFG_GPRTCDLCGEN 252 * Bit 2: MISCCFG_GSXLCGEN 253 * Bit 1: MISCCFG_GPDPCGEN 254 * Bit 0: MISCCFG_GPDLCGEN 255 */ 256 uint8_t gpio_pm[TOTAL_GPIO_COMM]; 257 258 /* DP config */ 259 /* 260 * Port config 261 * 0:Disabled, 1:eDP, 2:MIPI DSI 262 */ 263 uint8_t DdiPortAConfig; 264 uint8_t DdiPortBConfig; 265 266 /* HDP config 267 * 268 * true: Enable HDB 269 * false: Disable HDP 270 */ 271 bool DdiPortAHpd; 272 bool DdiPortBHpd; 273 bool DdiPortCHpd; 274 bool DdiPort1Hpd; 275 bool DdiPort2Hpd; 276 bool DdiPort3Hpd; 277 bool DdiPort4Hpd; 278 279 /* DDC config 280 * 281 * true: Enable DDC 282 * false: Disable DDC 283 */ 284 bool DdiPortADdc; 285 bool DdiPortBDdc; 286 bool DdiPortCDdc; 287 bool DdiPort1Ddc; 288 bool DdiPort2Ddc; 289 bool DdiPort3Ddc; 290 bool DdiPort4Ddc; 291 292 /* Hybrid storage mode 293 * This mode makes FSP detect Optane and NVME and set PCIe lane mode 294 * accordingly 295 * 296 * true: Enable Hybrid storage mode 297 * false Dsiable Hybrid storage mode 298 */ 299 bool HybridStorageMode; 300 301 /* 302 * Override CPU flex ratio value: 303 * CPU ratio value controls the maximum processor non-turbo ratio. 304 * Valid Range 0 to 63. 305 * In general descriptor provides option to set default cpu flex ratio. 306 * Default cpu flex ratio 0 ensures booting with non-turbo max frequency. 307 * That's the reason FSP skips cpu_ratio override if cpu_ratio is 0. 308 * Only override CPU flex ratio to not boot with non-turbo max. 309 */ 310 uint8_t cpu_ratio_override; 311 312 /* Skip CPU replacement check 313 * 314 * Setting this option to skip CPU replacement check to avoid the forced MRC training 315 * for the platforms with soldered down SOC. 316 * 317 * false: disable 318 * true: enable 319 */ 320 bool SkipCpuReplacementCheck; 321 322 /* 323 * SLP_S3 Minimum Assertion Width Policy 324 * 1 = 60us 325 * 2 = 1ms 326 * 3 = 50ms (default) 327 * 4 = 2s 328 */ 329 uint8_t PchPmSlpS3MinAssert; 330 331 /* 332 * SLP_S4 Minimum Assertion Width Policy 333 * 1 = 1s (default) 334 * 2 = 2s 335 * 3 = 3s 336 * 4 = 4s 337 */ 338 uint8_t PchPmSlpS4MinAssert; 339 340 /* 341 * SLP_SUS Minimum Assertion Width Policy 342 * 1 = 0ms 343 * 2 = 500ms 344 * 3 = 1s 345 * 4 = 4s (default) 346 */ 347 uint8_t PchPmSlpSusMinAssert; 348 349 /* 350 * SLP_A Minimum Assertion Width Policy 351 * 1 = 0ms 352 * 2 = 4s 353 * 3 = 98ms 354 * 4 = 2s (default) 355 */ 356 uint8_t PchPmSlpAMinAssert; 357 358 /* 359 * PCH PM Reset Power Cycle Duration 360 * 0 = 4s (default) 361 * 1 = 1s 362 * 2 = 2s 363 * 3 = 3s 364 * 4 = 4s 365 * 366 * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the 367 * stretch duration programmed in the following registers: 368 * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) 369 * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) 370 * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) 371 * - PM_CFG.SLP_LAN_MIN_ASST_WDTH 372 */ 373 uint8_t PchPmPwrCycDur; 374 375 /* 376 * FIVR RFI Frequency 377 * PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 378 * 0: Auto. 379 * Range varies based on XTAL clock: 380 * 0-1918 (Up to 191.8HMz) for 24MHz clock; 381 * 0-1535 (Up to 153.5MHz) for 19MHz clock. 382 */ 383 uint16_t FivrRfiFrequency; 384 385 /* 386 * FIVR RFI Spread Spectrum 387 * Set the Spread Spectrum Range. <b>0: 0%</b>; 388 * FIVR RFI Spread Spectrum, in 0.1% increments. 389 * Range: 0.0% to 10.0% (0-100) 390 */ 391 uint8_t FivrSpreadSpectrum; 392 393 /* 394 * Disable Fast Slew Rate for Deep Package C States for VCCIN VR domain 395 * Disable Fast Slew Rate for Deep Package C States based on 396 * Acoustic Noise Mitigation feature enabled. 397 */ 398 bool FastPkgCRampDisable; 399 400 /* 401 * Slew Rate configuration for Deep Package C States for VCCIN VR domain 402 * based on Acoustic Noise Mitigation feature enabled. 403 * 0: Fast/2 ; 1: Fast/4; 2: Fast/8; 3: Fast/16 404 */ 405 enum { 406 SlewRateFastBy2 = 0, 407 SlewRateFastBy4, 408 SlewRateFastBy8, 409 SlewRateFastBy16 410 } SlowSlewRate; 411 412 /* 413 * Enable or Disable Acoustic Noise Mitigation feature. 414 * 415 * false: Disabled 416 * true: Enabled 417 */ 418 bool AcousticNoiseMitigation; 419 420 /* 421 * Acoustic Noise Mitigation Range.Defines the maximum Pre-Wake 422 * randomization time in micro ticks.This can be programmed only 423 * if AcousticNoiseMitigation is enabled. 424 * Range 0-255 425 */ 426 uint8_t PreWake; 427 428 /* 429 * Acoustic Noise Mitigation Range.Defines the maximum Ramp Up 430 * randomization time in micro ticks.This can be programmed only 431 * if AcousticNoiseMitigation is enabled. 432 * Range 0-255 433 */ 434 uint8_t RampUp; 435 436 /* 437 * Acoustic Noise Mitigation Range.Defines the maximum Ramp Down 438 * randomization time in micro ticks.This can be programmed only 439 * if AcousticNoiseMitigation is enabled. 440 * Range 0-255 441 */ 442 uint8_t RampDown; 443 444 /* 445 * It controls below soc variables 446 * 447 * PchFivrExtV1p05RailEnabledStates 448 * PchFivrExtVnnRailSxEnabledStates 449 * PchFivrExtVnnRailEnabledStates 450 * 451 * If your platform does not support external vnn power rail please set to 1 452 * 1: Disabled ; 0: Enabled 453 */ 454 bool disable_external_bypass_vr; 455 456 /* 457 * Core Display Clock Frequency selection, FSP UPD CdClock values + 1 458 * 459 * FSP will use the value to program clock frequency for core display if GOP 460 * is not run. Ex: the Chromebook normal mode. 461 * For the cases GOP is run, GOP will be in charge of the related register 462 * settings. 463 */ 464 enum { 465 CD_CLOCK_172_8_MHZ = 1, 466 CD_CLOCK_180_MHZ = 2, 467 CD_CLOCK_192_MHZ = 3, 468 CD_CLOCK_307_MHZ = 4, 469 CD_CLOCK_312_MHZ = 5, 470 CD_CLOCK_552_MHZ = 6, 471 CD_CLOCK_556_8_MHZ = 7, 472 } cd_clock; 473 474 /* Platform Power Pmax */ 475 uint16_t PsysPmax; 476 477 /* 478 * This is a workaround to mitigate higher SoC power consumption in S0ix 479 * when the CNVI has background activity. 480 * 481 * Setting this on a system that supports S0i3 (set xtalsdqdis [Bit 22] in 482 * cppmvric1 register to 0) will break CNVI timing. 483 * Affected Intel wireless chipsets: AC9560 (JfP2), AC9461/AC9462 (JfP1) and 484 * AX201 (HrP2) 485 * 486 * true: Enabled (fewer wakes, lower power) 487 * false: Disabled (more wakes, higher power) 488 */ 489 bool cnvi_reduce_s0ix_pwr_usage; 490 491 /* i915 struct for GMA backlight control */ 492 struct i915_gpu_controller_info gfx; 493 }; 494 495 typedef struct soc_intel_jasperlake_config config_t; 496 497 #endif 498