1 /*
2 * Copyright 2019-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef DRAM_H
8 #define DRAM_H
9
10 #include <assert.h>
11
12 #include <arch_helpers.h>
13 #include <lib/utils_def.h>
14
15 #include <ddrc.h>
16 #include <platform_def.h>
17
18 #define DDRC_LPDDR4 BIT(5)
19 #define DDRC_DDR4 BIT(4)
20 #define DDRC_DDR3L BIT(0)
21 #define DDR_TYPE_MASK U(0x3f)
22 #define ACTIVE_RANK_MASK U(0x3)
23 #define DDRC_ACTIVE_ONE_RANK U(0x1)
24 #define DDRC_ACTIVE_TWO_RANK U(0x2)
25
26 #define MR12 U(12)
27 #define MR14 U(14)
28
29 #define MAX_FSP_NUM U(3)
30
31 /* reg & config param */
32 struct dram_cfg_param {
33 unsigned int reg;
34 unsigned int val;
35 };
36
37 struct dram_timing_info {
38 /* umctl2 config */
39 struct dram_cfg_param *ddrc_cfg;
40 unsigned int ddrc_cfg_num;
41 /* ddrphy config */
42 struct dram_cfg_param *ddrphy_cfg;
43 unsigned int ddrphy_cfg_num;
44 /* ddr fsp train info */
45 struct dram_fsp_msg *fsp_msg;
46 unsigned int fsp_msg_num;
47 /* ddr phy trained CSR */
48 struct dram_cfg_param *ddrphy_trained_csr;
49 unsigned int ddrphy_trained_csr_num;
50 /* ddr phy PIE */
51 struct dram_cfg_param *ddrphy_pie;
52 unsigned int ddrphy_pie_num;
53 /* initialized fsp table */
54 unsigned int fsp_table[4];
55 };
56
57 struct dram_info {
58 int dram_type;
59 unsigned int num_rank;
60 uint32_t num_fsp;
61 int current_fsp;
62 int boot_fsp;
63 bool bypass_mode;
64 struct dram_timing_info *timing_info;
65 /* mr, emr, emr2, emr3, mr11, mr12, mr22, mr14 */
66 uint32_t mr_table[3][8];
67 /* used for workaround for rank to rank issue */
68 uint32_t rank_setting[3][3];
69 };
70
71 extern struct dram_info dram_info;
72
73 void dram_umctl2_init(struct dram_timing_info *timing);
74 void dram_phy_init(struct dram_timing_info *timing);
75
76 /* dram retention */
77 #if IMX_DRAM_RETENTION
78 void dram_info_init(unsigned long dram_timing_base);
79 void dram_enter_retention(void);
80 void dram_exit_retention(void);
81 #else
dram_info_init(unsigned long dram_timing_base)82 static inline void dram_info_init(unsigned long dram_timing_base) {}
dram_enter_retention(void)83 static inline void dram_enter_retention(void) {}
dram_exit_retention(void)84 static inline void dram_exit_retention(void) {}
85 #endif
86
87 void dram_clock_switch(unsigned int target_drate, bool bypass_mode);
88
89 /* dram frequency change */
90 void lpddr4_swffc(struct dram_info *info, unsigned int init_fsp, unsigned int fsp_index);
91 void ddr4_swffc(struct dram_info *dram_info, unsigned int pstate);
92
93 #endif /* DRAM_H */
94