1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _SOC_PM_H_ 4 #define _SOC_PM_H_ 5 6 #include <acpi/acpi.h> 7 #include <device/mmio.h> 8 #include <soc/gpe.h> 9 #include <soc/iomap.h> 10 #include <soc/pmc.h> 11 #include <soc/smbus.h> 12 13 /* ACPI_BASE_ADDRESS / PMBASE */ 14 15 #define PM1_STS 0x00 16 #define WAK_STS (1 << 15) 17 #define PCIEXPWAK_STS (1 << 14) 18 #define PRBTNOR_STS (1 << 11) 19 #define RTC_STS (1 << 10) 20 #define PWRBTN_STS (1 << 8) 21 #define GBL_STS (1 << 5) 22 #define BM_STS (1 << 4) 23 #define TMROF_STS (1 << 0) 24 #define PM1_EN 0x02 25 #define PCIEXPWAK_DIS (1 << 14) 26 #define RTC_EN (1 << 10) 27 #define PWRBTN_EN (1 << 8) 28 #define GBL_EN (1 << 5) 29 #define TMROF_EN (1 << 0) 30 #define PM1_CNT 0x04 31 #define GBL_RLS (1 << 2) 32 #define BM_RLD (1 << 1) 33 #define SCI_EN (1 << 0) 34 #define PM1_TMR 0x08 35 #define SMI_EN 0x30 36 #define XHCI_SMI_EN (1 << 31) 37 #define ME_SMI_EN (1 << 30) 38 #define ESPI_SMI_EN (1 << 28) 39 #define GPIO_UNLOCK_SMI_EN (1 << 27) 40 #define INTEL_USB2_EN (1 << 18) 41 #define LEGACY_USB2_EN (1 << 17) 42 #define PERIODIC_EN (1 << 14) 43 #define TCO_SMI_EN (1 << 13) 44 #define MCSMI_EN (1 << 11) 45 #define BIOS_RLS (1 << 7) 46 #define SWSMI_TMR_EN (1 << 6) 47 #define APMC_EN (1 << 5) 48 #define SLP_SMI_EN (1 << 4) 49 #define LEGACY_USB_EN (1 << 3) 50 #define BIOS_EN (1 << 2) 51 #define EOS (1 << 1) 52 #define GBL_SMI_EN (1 << 0) 53 #define SMI_STS 0x34 54 #define SMI_STS_BITS 32 55 #define XHCI_SMI_STS_BIT 31 56 #define ME_SMI_STS_BIT 30 57 #define SERIAL_IO_SMI_STS_BIT 29 58 #define ESPI_SMI_STS_BIT 28 59 #define GPIO_UNLOCK_SMI_STS_BIT 27 60 #define SPI_SMI_STS_BIT 26 61 #define SCC_SMI_STS_BIT 25 62 #define MONITOR_STS_BIT 21 63 #define PCI_EXP_SMI_STS_BIT 20 64 #define SMBUS_SMI_STS_BIT 16 65 #define SERIRQ_SMI_STS_BIT 15 66 #define PERIODIC_STS_BIT 14 67 #define TCO_STS_BIT 13 68 #define DEVMON_STS_BIT 12 69 #define MCSMI_STS_BIT 11 70 #define GPIO_STS_BIT 10 71 #define GPE0_STS_BIT 9 72 #define PM1_STS_BIT 8 73 #define SWSMI_TMR_STS_BIT 6 74 #define APM_STS_BIT 5 75 #define SMI_ON_SLP_EN_STS_BIT 4 76 #define LEGACY_USB_STS_BIT 3 77 #define BIOS_STS_BIT 2 78 #define UPWRC 0x3c 79 #define UPWRC_WS (1 << 8) 80 #define UPWRC_WE (1 << 1) 81 #define UPWRC_SMI (1 << 0) 82 #define GPE_CNTL 0x42 83 #define SWGPE_CTRL (1 << 1) 84 #define DEVACT_STS 0x44 85 #define PM2_CNT 0x50 86 87 #define GPE0_REG_MAX 4 88 #define GPE0_REG_SIZE 32 89 #define GPE0_STS(x) (0x80 + ((x) * 4)) 90 #define GPE_31_0 0 /* 0x80/0x90 = GPE[31:0] */ 91 #define GPE_63_32 1 /* 0x84/0x94 = GPE[63:32] */ 92 #define GPE_95_64 2 /* 0x88/0x98 = GPE[95:64] */ 93 #define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */ 94 #define GPE_STS_RSVD GPE_STD 95 #define WADT_STS (1 << 18) 96 #define LAN_WAK_STS (1 << 16) 97 #define GPIO_T2_STS (1 << 15) 98 #define ESPI_STS (1 << 14) 99 #define PME_B0_STS (1 << 13) 100 #define ME_SCI_STS (1 << 12) 101 #define PME_STS (1 << 11) 102 #define BATLOW_STS (1 << 10) 103 #define PCI_EXP_STS (1 << 9) 104 #define SMB_WAK_STS (1 << 7) 105 #define TCOSCI_STS (1 << 6) 106 #define SWGPE_STS (1 << 2) 107 #define HOT_PLUG_STS (1 << 1) 108 #define GPE0_EN(x) (0x90 + ((x) * 4)) 109 #define WADT_EN (1 << 18) 110 #define LAN_WAK_EN (1 << 16) 111 #define GPIO_T2_EN (1 << 15) 112 #define ESPI_EN (1 << 14) 113 #define PME_B0_EN (1 << 13) 114 #define ME_SCI_EN (1 << 12) 115 #define PME_EN (1 << 11) 116 #define BATLOW_EN (1 << 10) 117 #define PCI_EXP_EN (1 << 9) 118 #define TCOSCI_EN (1 << 6) 119 #define SWGPE_EN (1 << 2) 120 #define HOT_PLUG_EN (1 << 1) 121 122 #define GBLRST_CAUSE0_THERMTRIP (1 << 5) 123 124 /* 125 * Enable SMI generation: 126 * - on APMC writes (io 0xb2) 127 * - on writes to SLP_EN (sleep states) 128 * - on writes to GBL_RLS (bios commands) 129 * - on eSPI events (does nothing on LPC systems) 130 * No SMIs: 131 * - on TCO events, unless enabled in common code 132 * - on microcontroller writes (io 0x62/0x66) 133 */ 134 #define ENABLE_SMI_PARAMS \ 135 (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) 136 137 /* This is defined as ETR3 in EDS. We named it as ETR here for consistency */ 138 #define ETR 0xac 139 #define CF9_LOCK (1 << 31) 140 #define CF9_GLB_RST (1 << 20) 141 142 #define PRSTS 0x10 143 144 /* P-state configuration */ 145 #define PSS_MAX_ENTRIES 8 146 #define PSS_RATIO_STEP 2 147 #define PSS_LATENCY_TRANSITION 10 148 #define PSS_LATENCY_BUSMASTER 10 149 150 struct chipset_power_state { 151 uint16_t pm1_sts; 152 uint16_t pm1_en; 153 uint32_t pm1_cnt; 154 uint16_t tco1_sts; 155 uint16_t tco2_sts; 156 uint32_t gpe0_sts[4]; 157 uint32_t gpe0_en[4]; 158 uint32_t gen_pmcon_a; 159 uint32_t gen_pmcon_b; 160 uint32_t gblrst_cause[2]; 161 uint32_t prev_sleep_state; 162 } __packed; 163 164 /* Get base address PMC memory mapped registers. */ 165 uint8_t *pmc_mmio_regs(void); 166 167 /* Set the DISB after DRAM init */ 168 void pmc_set_disb(void); 169 170 /* Return non-zero when RTC failure happened. */ 171 int rtc_failure(void); 172 deep_s3_enabled(void)173static inline int deep_s3_enabled(void) 174 { 175 uint32_t deep_s3_pol; 176 177 deep_s3_pol = read32(pmc_mmio_regs() + S3_PWRGATE_POL); 178 return !!(deep_s3_pol & (S3DC_GATE_SUS | S3AC_GATE_SUS)); 179 } 180 deep_s5_enabled(void)181static inline int deep_s5_enabled(void) 182 { 183 uint32_t deep_s5_pol; 184 185 deep_s5_pol = read32(pmc_mmio_regs() + S5_PWRGATE_POL); 186 return !!(deep_s5_pol & (S5DC_GATE_SUS | S5AC_GATE_SUS)); 187 } 188 189 /* STM Support */ 190 uint16_t get_pmbase(void); 191 192 #endif 193