1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _MT8183_SOC_DDP_H_ 4 #define _MT8183_SOC_DDP_H_ 5 6 #include <soc/addressmap.h> 7 #include <soc/ddp_common.h> 8 #include <types.h> 9 10 #define MAIN_PATH_OVL_NR 2 11 12 struct mmsys_cfg_regs { 13 u32 reserved_0x000[64]; /* 0x000 */ 14 u32 mmsys_cg_con0; /* 0x100 */ 15 u32 mmsys_cg_set0; /* 0x104 */ 16 u32 mmsys_cg_clr0; /* 0x108 */ 17 u32 reserved_0x10C; /* 0x10C */ 18 u32 mmsys_cg_con1; /* 0x110 */ 19 u32 mmsys_cg_set1; /* 0x114 */ 20 u32 mmsys_cg_clr1; /* 0x118 */ 21 u32 reserved_0x11C[33]; /* 0x11C */ 22 u32 mmsys_cg_con2; /* 0x1A0 */ 23 u32 mmsys_cg_set2; /* 0x1A4 */ 24 u32 mmsys_cg_clr2; /* 0x1A8 */ 25 u32 reserved_0x1AC[853]; /* 0x1AC */ 26 u32 reserved_0xF00; /* 0xF00 */ 27 u32 mmsys_ovl_mout_en; /* 0xF04 */ 28 u32 reserved_0xF08; /* 0xF08 */ 29 u32 reserved_0xF0C; /* 0xF0C */ 30 u32 reserved_0xF10; /* 0xF10 */ 31 u32 reserved_0xF14; /* 0xF14 */ 32 u32 ovl0_2l_mout_en; /* 0xF18 */ 33 u32 ovl0_mout_en; /* 0xF1C */ 34 u32 reserved_0xF20; /* 0xF20 */ 35 u32 reserved_0xF24; /* 0xF24 */ 36 u32 reserved_0xF28; /* 0xF28 */ 37 u32 rdma0_sel_in; /* 0xF2C */ 38 u32 rdma0_sout_sel; /* 0xF30 */ 39 u32 ccorr0_sout_sel; /* 0xF34 */ 40 u32 aal0_sel_in; /* 0xF38 */ 41 u32 dither0_mout_en; /* 0xF3C*/ 42 u32 dsi0_sel_in; /* 0xF40*/ 43 }; 44 45 check_member(mmsys_cfg_regs, mmsys_cg_con0, 0x100); 46 check_member(mmsys_cfg_regs, mmsys_cg_con1, 0x110); 47 check_member(mmsys_cfg_regs, mmsys_cg_con2, 0x1A0); 48 check_member(mmsys_cfg_regs, mmsys_ovl_mout_en, 0xF04); 49 check_member(mmsys_cfg_regs, ovl0_2l_mout_en, 0xF18); 50 check_member(mmsys_cfg_regs, dsi0_sel_in, 0xF40); 51 static struct mmsys_cfg_regs *const mmsys_cfg = 52 (void *)MMSYS_BASE; 53 54 55 /* DISP_REG_CONFIG_MMSYS_CG_CON0 56 Configures free-run clock gating 0 57 0: Enable clock 58 1: Clock gating */ 59 enum { 60 CG_CON0_DISP_MUTEX0 = BIT(0), 61 CG_CON0_DISPSYS_CONFIG = BIT(1), 62 CG_CON0_DISP_OVL0 = BIT(2), 63 CG_CON0_DISP_RDMA0 = BIT(3), 64 CG_CON0_DISP_OVL0_2L = BIT(4), 65 CG_CON0_DISP_AAL0 = BIT(8), 66 CG_CON0_DISP_CCORR0 = BIT(9), 67 CG_CON0_DISP_DITHER0 = BIT(10), 68 CG_CON0_SMI_INFRA = BIT(11), 69 CG_CON0_DISP_GAMMA0 = BIT(12), 70 CG_CON0_DISP_POSTMASK0 = BIT(13), 71 CG_CON0_DISP_DSI0 = BIT(15), 72 CG_CON0_DISP_COLOR0 = BIT(16), 73 CG_CON0_SMI_COMMON = BIT(17), 74 75 CG_CON0_SMI_GALS = BIT(27), 76 CG_CON0_DISP_ALL = CG_CON0_SMI_INFRA | 77 CG_CON0_SMI_COMMON | 78 CG_CON0_SMI_GALS | 79 CG_CON0_DISP_MUTEX0 | 80 CG_CON0_DISPSYS_CONFIG | 81 CG_CON0_DISP_OVL0 | 82 CG_CON0_DISP_RDMA0 | 83 CG_CON0_DISP_OVL0_2L | 84 CG_CON0_DISP_AAL0 | 85 CG_CON0_DISP_CCORR0 | 86 CG_CON0_DISP_DITHER0 | 87 CG_CON0_DISP_GAMMA0 | 88 CG_CON0_DISP_POSTMASK0 | 89 CG_CON0_DISP_DSI0 | 90 CG_CON0_DISP_COLOR0, 91 CG_CON0_ALL = 0xffffffff 92 }; 93 94 /* DISP_REG_CONFIG_MMSYS_CG_CON1 95 Configures free-run clock gating 1 96 0: Enable clock 97 1: Clock gating */ 98 enum { 99 CG_CON1_SMI_IOMMU = BIT(0), 100 CG_CON1_DISP_ALL = CG_CON1_SMI_IOMMU, 101 CG_CON1_ALL = 0xffffffff 102 }; 103 104 enum { 105 CG_CON2_DSI_DSI0 = BIT(0), 106 CG_CON2_DPI_DPI0 = BIT(8), 107 CG_CON2_MM_26MHZ = BIT(24), 108 CG_CON2_DISP_ALL = CG_CON2_DSI_DSI0 | 109 CG_CON2_MM_26MHZ, 110 CG_CON2_ALL = 0xffffffff 111 }; 112 113 114 enum { 115 DISP_OVL0_GO_BLEND = BIT(0), 116 DISP_OVL0_GO_BG = BIT(1), 117 DISP_OVL0_2L_GO_BLEND = BIT(2), 118 DISP_OVL0_2L_GO_BG = BIT(3), 119 OVL0_MOUT_EN_DISP_RDMA0 = BIT(0), 120 DITHER0_MOUT_DSI0 = BIT(0), 121 }; 122 123 enum { 124 RDMA0_SEL_IN_OVL0_2L = 0x3, 125 RDMA0_SOUT_COLOR0 = 0x1, 126 CCORR0_SOUT_AAL0 = 0x1, 127 AAL0_SEL_IN_CCORR0 = 0x1, 128 DSI0_SEL_IN_DITHER0 = 0x1, 129 }; 130 131 struct disp_mutex_regs { 132 u32 inten; 133 u32 intsta; 134 u32 reserved0[6]; 135 struct { 136 u32 en; 137 u32 dummy; 138 u32 rst; 139 u32 ctl; 140 u32 mod; 141 u32 reserved[3]; 142 } mutex[12]; 143 }; 144 145 static struct disp_mutex_regs *const disp_mutex = (void *)DISP_MUTEX_BASE; 146 147 enum { 148 MUTEX_MOD_DISP_OVL0 = BIT(0), 149 MUTEX_MOD_DISP_OVL0_2L = BIT(1), 150 MUTEX_MOD_DISP_RDMA0 = BIT(2), 151 MUTEX_MOD_DISP_COLOR0 = BIT(4), 152 MUTEX_MOD_DISP_CCORR0 = BIT(5), 153 MUTEX_MOD_DISP_AAL0 = BIT(6), 154 MUTEX_MOD_DISP_GAMMA0 = BIT(7), 155 MUTEX_MOD_DISP_POSTMASK0 = BIT(8), 156 MUTEX_MOD_DISP_DITHER0 = BIT(9), 157 MUTEX_MOD_MAIN_PATH = MUTEX_MOD_DISP_OVL0 | 158 MUTEX_MOD_DISP_OVL0_2L | 159 MUTEX_MOD_DISP_RDMA0 | 160 MUTEX_MOD_DISP_COLOR0 | 161 MUTEX_MOD_DISP_CCORR0 | 162 MUTEX_MOD_DISP_AAL0 | 163 MUTEX_MOD_DISP_GAMMA0 | 164 MUTEX_MOD_DISP_POSTMASK0 | 165 MUTEX_MOD_DISP_DITHER0, 166 }; 167 168 enum { 169 MUTEX_SOF_SINGLE_MODE = 0, 170 MUTEX_SOF_DSI0 = 1, 171 MUTEX_SOF_DPI0 = 2, 172 }; 173 174 struct disp_ccorr_regs { 175 u32 en; 176 u32 reset; 177 u32 inten; 178 u32 intsta; 179 u32 status; 180 u32 reserved0[3]; 181 u32 cfg; 182 u32 reserved1[3]; 183 u32 size; 184 u32 reserved2[27]; 185 u32 shadow; 186 }; 187 check_member(disp_ccorr_regs, shadow, 0xA0); 188 189 struct disp_gamma_regs { 190 u32 en; 191 u32 reset; 192 u32 inten; 193 u32 intsta; 194 u32 status; 195 u32 reserved0[3]; 196 u32 cfg; 197 u32 reserved1[3]; 198 u32 size; 199 }; 200 check_member(disp_gamma_regs, size, 0x30); 201 202 struct disp_aal_regs { 203 u32 en; 204 u32 reset; 205 u32 inten; 206 u32 intsta; 207 u32 status; 208 u32 reserved0[3]; 209 u32 cfg; 210 u32 reserved1[3]; 211 u32 size; 212 u32 reserved2[47]; 213 u32 shadow; 214 u32 reserved3[249]; 215 u32 output_size; 216 }; 217 check_member(disp_aal_regs, shadow, 0xF0); 218 check_member(disp_aal_regs, output_size, 0x4D8); 219 220 struct disp_postmask_regs { 221 u32 en; 222 u32 reset; 223 u32 inten; 224 u32 intsta; 225 u32 reserved0[4]; 226 u32 cfg; 227 u32 reserved1[3]; 228 u32 size; 229 }; 230 check_member(disp_postmask_regs, size, 0x30); 231 232 struct disp_dither_regs { 233 u32 en; 234 u32 reset; 235 u32 inten; 236 u32 intsta; 237 u32 status; 238 u32 reserved0[3]; 239 u32 cfg; 240 u32 reserved1[3]; 241 u32 size; 242 u32 reserved2[51]; 243 u32 shadow; 244 }; 245 check_member(disp_dither_regs, shadow, 0x100); 246 247 enum { 248 PQ_EN = BIT(0), 249 PQ_RELAY_MODE = BIT(0), 250 PQ_ENGINE_EN = BIT(1), 251 }; 252 253 static struct disp_ccorr_regs *const disp_ccorr = (void *)DISP_CCORR0_BASE; 254 255 static struct disp_aal_regs *const disp_aal = (void *)DISP_AAL0_BASE; 256 257 static struct disp_gamma_regs *const disp_gamma = (void *)DISP_GAMMA0_BASE; 258 259 static struct disp_dither_regs *const disp_dither = (void *)DISP_DITHER0_BASE; 260 261 static struct disp_postmask_regs *const disp_postmask = (void *)DISP_POSTMASK0_BASE; 262 263 enum { 264 SMI_LARB_PORT_L0_OVL_RDMA0 = 0x388, 265 }; 266 267 void mtk_ddp_init(void); 268 void mtk_ddp_mode_set(const struct edid *edid); 269 270 #endif 271