1 /*
2 * Copyright © 2015-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "elk_compiler.h"
25 #include "elk_shader.h"
26 #include "elk_eu.h"
27 #include "elk_nir.h"
28 #include "elk_nir_options.h"
29 #include "dev/intel_debug.h"
30 #include "compiler/nir/nir.h"
31 #include "util/u_debug.h"
32
33 struct elk_compiler *
elk_compiler_create(void * mem_ctx,const struct intel_device_info * devinfo)34 elk_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
35 {
36 assert(devinfo->ver <= 8);
37
38 struct elk_compiler *compiler = rzalloc(mem_ctx, struct elk_compiler);
39
40 compiler->devinfo = devinfo;
41
42 elk_init_isa_info(&compiler->isa, devinfo);
43
44 elk_fs_alloc_reg_sets(compiler);
45 if (devinfo->ver < 8)
46 elk_vec4_alloc_reg_set(compiler);
47
48 compiler->precise_trig = debug_get_bool_option("INTEL_PRECISE_TRIG", false);
49
50 /* Default to the sampler since that's what we've done since forever */
51 compiler->indirect_ubos_use_sampler = true;
52
53 /* There is no vec4 mode on Gfx10+, and we don't use it at all on Gfx8+. */
54 for (int i = MESA_SHADER_VERTEX; i < MESA_ALL_SHADER_STAGES; i++) {
55 compiler->scalar_stage[i] = devinfo->ver >= 8 ||
56 i == MESA_SHADER_FRAGMENT || i == MESA_SHADER_COMPUTE;
57 }
58
59 nir_lower_int64_options int64_options =
60 nir_lower_imul64 |
61 nir_lower_isign64 |
62 nir_lower_divmod64 |
63 nir_lower_imul_high64 |
64 nir_lower_find_lsb64 |
65 nir_lower_ufind_msb64 |
66 nir_lower_bit_count64;
67 nir_lower_doubles_options fp64_options =
68 nir_lower_drcp |
69 nir_lower_dsqrt |
70 nir_lower_drsq |
71 nir_lower_dsign |
72 nir_lower_dtrunc |
73 nir_lower_dfloor |
74 nir_lower_dceil |
75 nir_lower_dfract |
76 nir_lower_dround_even |
77 nir_lower_dmod |
78 nir_lower_dsub |
79 nir_lower_ddiv;
80
81 if (!devinfo->has_64bit_float || INTEL_DEBUG(DEBUG_SOFT64))
82 fp64_options |= nir_lower_fp64_full_software;
83 if (!devinfo->has_64bit_int)
84 int64_options |= (nir_lower_int64_options)~0;
85
86 /* The Bspec's section titled "Instruction_multiply[DevBDW+]" claims that
87 * destination type can be Quadword and source type Doubleword for Gfx8 and
88 * Gfx9. So, lower 64 bit multiply instruction on rest of the platforms.
89 */
90 if (devinfo->ver < 8)
91 int64_options |= nir_lower_imul_2x32_64;
92
93 /* We want the GLSL compiler to emit code that uses condition codes */
94 for (int i = 0; i < MESA_ALL_SHADER_STAGES; i++) {
95 struct nir_shader_compiler_options *nir_options =
96 rzalloc(compiler, struct nir_shader_compiler_options);
97 bool is_scalar = compiler->scalar_stage[i];
98 if (is_scalar) {
99 *nir_options = elk_scalar_nir_options;
100 int64_options |= nir_lower_usub_sat64;
101 } else {
102 *nir_options = elk_vector_nir_options;
103 }
104
105 /* Prior to Gfx6, there are no three source operations, and Gfx11 loses
106 * LRP.
107 */
108 nir_options->lower_ffma16 = devinfo->ver < 6;
109 nir_options->lower_ffma32 = devinfo->ver < 6;
110 nir_options->lower_ffma64 = devinfo->ver < 6;
111 nir_options->lower_flrp32 = devinfo->ver < 6;
112
113 nir_options->has_bfe = devinfo->ver >= 7;
114 nir_options->has_bfm = devinfo->ver >= 7;
115 nir_options->has_bfi = devinfo->ver >= 7;
116
117 nir_options->lower_bitfield_reverse = devinfo->ver < 7;
118 nir_options->lower_find_lsb = devinfo->ver < 7;
119 nir_options->lower_ifind_msb = devinfo->ver < 7;
120
121 nir_options->lower_int64_options = int64_options;
122 nir_options->lower_doubles_options = fp64_options;
123
124 nir_options->unify_interfaces = i < MESA_SHADER_FRAGMENT;
125 nir_options->support_indirect_inputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
126 nir_options->support_indirect_outputs = (uint8_t)BITFIELD_MASK(PIPE_SHADER_TYPES),
127
128 nir_options->force_indirect_unrolling |=
129 elk_nir_no_indirect_mask(compiler, i);
130 nir_options->force_indirect_unrolling_sampler = devinfo->ver < 7;
131
132 nir_options->divergence_analysis_options |=
133 nir_divergence_single_prim_per_subgroup;
134
135 compiler->nir_options[i] = nir_options;
136 }
137
138 return compiler;
139 }
140
141 static void
insert_u64_bit(uint64_t * val,bool add)142 insert_u64_bit(uint64_t *val, bool add)
143 {
144 *val = (*val << 1) | !!add;
145 }
146
147 uint64_t
elk_get_compiler_config_value(const struct elk_compiler * compiler)148 elk_get_compiler_config_value(const struct elk_compiler *compiler)
149 {
150 uint64_t config = 0;
151 unsigned bits = 0;
152
153 insert_u64_bit(&config, compiler->precise_trig);
154 bits++;
155
156 uint64_t mask = DEBUG_DISK_CACHE_MASK;
157 bits += util_bitcount64(mask);
158
159 u_foreach_bit64(bit, mask)
160 insert_u64_bit(&config, INTEL_DEBUG(1ULL << bit));
161
162 mask = SIMD_DISK_CACHE_MASK;
163 bits += util_bitcount64(mask);
164
165 u_foreach_bit64(bit, mask)
166 insert_u64_bit(&config, (intel_simd & (1ULL << bit)) != 0);
167
168 mask = 3;
169 bits += util_bitcount64(mask);
170
171 assert(bits <= util_bitcount64(UINT64_MAX));
172
173 return config;
174 }
175
176 unsigned
elk_prog_data_size(gl_shader_stage stage)177 elk_prog_data_size(gl_shader_stage stage)
178 {
179 static const size_t stage_sizes[] = {
180 [MESA_SHADER_VERTEX] = sizeof(struct elk_vs_prog_data),
181 [MESA_SHADER_TESS_CTRL] = sizeof(struct elk_tcs_prog_data),
182 [MESA_SHADER_TESS_EVAL] = sizeof(struct elk_tes_prog_data),
183 [MESA_SHADER_GEOMETRY] = sizeof(struct elk_gs_prog_data),
184 [MESA_SHADER_FRAGMENT] = sizeof(struct elk_wm_prog_data),
185 [MESA_SHADER_COMPUTE] = sizeof(struct elk_cs_prog_data),
186 };
187 assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
188 return stage_sizes[stage];
189 }
190
191 unsigned
elk_prog_key_size(gl_shader_stage stage)192 elk_prog_key_size(gl_shader_stage stage)
193 {
194 static const size_t stage_sizes[] = {
195 [MESA_SHADER_VERTEX] = sizeof(struct elk_vs_prog_key),
196 [MESA_SHADER_TESS_CTRL] = sizeof(struct elk_tcs_prog_key),
197 [MESA_SHADER_TESS_EVAL] = sizeof(struct elk_tes_prog_key),
198 [MESA_SHADER_GEOMETRY] = sizeof(struct elk_gs_prog_key),
199 [MESA_SHADER_FRAGMENT] = sizeof(struct elk_wm_prog_key),
200 [MESA_SHADER_COMPUTE] = sizeof(struct elk_cs_prog_key),
201 };
202 assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
203 return stage_sizes[stage];
204 }
205
206 void
elk_write_shader_relocs(const struct elk_isa_info * isa,void * program,const struct elk_stage_prog_data * prog_data,struct elk_shader_reloc_value * values,unsigned num_values)207 elk_write_shader_relocs(const struct elk_isa_info *isa,
208 void *program,
209 const struct elk_stage_prog_data *prog_data,
210 struct elk_shader_reloc_value *values,
211 unsigned num_values)
212 {
213 for (unsigned i = 0; i < prog_data->num_relocs; i++) {
214 assert(prog_data->relocs[i].offset % 8 == 0);
215 void *dst = program + prog_data->relocs[i].offset;
216 for (unsigned j = 0; j < num_values; j++) {
217 if (prog_data->relocs[i].id == values[j].id) {
218 uint32_t value = values[j].value + prog_data->relocs[i].delta;
219 switch (prog_data->relocs[i].type) {
220 case ELK_SHADER_RELOC_TYPE_U32:
221 *(uint32_t *)dst = value;
222 break;
223 case ELK_SHADER_RELOC_TYPE_MOV_IMM:
224 elk_update_reloc_imm(isa, dst, value);
225 break;
226 default:
227 unreachable("Invalid relocation type");
228 }
229 break;
230 }
231 }
232 }
233 }
234