1 /* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keithw@vmware.com> 30 */ 31 32 #pragma once 33 34 #include <stdint.h> 35 #include <stdlib.h> 36 #include "util/macros.h" 37 #include "dev/intel_device_info.h" 38 #include "elk_eu_opcodes.h" 39 40 /* The following hunk, up-to "Execution Unit" is used by both the 41 * intel/compiler and i965 codebase. */ 42 43 #define INTEL_MASK(high, low) (((1u<<((high)-(low)+1))-1)<<(low)) 44 /* Using the GNU statement expression extension */ 45 #define SET_FIELD(value, field) \ 46 ({ \ 47 uint32_t fieldval = (uint32_t)(value) << field ## _SHIFT; \ 48 assert((fieldval & ~ field ## _MASK) == 0); \ 49 fieldval & field ## _MASK; \ 50 }) 51 52 #define SET_BITS(value, high, low) \ 53 ({ \ 54 const uint32_t fieldval = (uint32_t)(value) << (low); \ 55 assert((fieldval & ~INTEL_MASK(high, low)) == 0); \ 56 fieldval & INTEL_MASK(high, low); \ 57 }) 58 59 #define GET_BITS(data, high, low) ((data & INTEL_MASK((high), (low))) >> (low)) 60 #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT) 61 62 /* Bitfields for the URB_WRITE message, DW2 of message header: */ 63 #define URB_WRITE_PRIM_END 0x1 64 #define URB_WRITE_PRIM_START 0x2 65 #define URB_WRITE_PRIM_TYPE_SHIFT 2 66 67 #define ELK_SPRITE_POINT_ENABLE 16 68 69 # define GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT 0 70 # define GFX7_GS_CONTROL_DATA_FORMAT_GSCTL_SID 1 71 72 /* Execution Unit (EU) defines 73 */ 74 75 #define ELK_ALIGN_1 0 76 #define ELK_ALIGN_16 1 77 78 #define ELK_ADDRESS_DIRECT 0 79 #define ELK_ADDRESS_REGISTER_INDIRECT_REGISTER 1 80 81 #define ELK_CHANNEL_X 0 82 #define ELK_CHANNEL_Y 1 83 #define ELK_CHANNEL_Z 2 84 #define ELK_CHANNEL_W 3 85 86 enum elk_compression { 87 ELK_COMPRESSION_NONE = 0, 88 ELK_COMPRESSION_2NDHALF = 1, 89 ELK_COMPRESSION_COMPRESSED = 2, 90 }; 91 92 #define GFX6_COMPRESSION_1Q 0 93 #define GFX6_COMPRESSION_2Q 1 94 #define GFX6_COMPRESSION_3Q 2 95 #define GFX6_COMPRESSION_4Q 3 96 #define GFX6_COMPRESSION_1H 0 97 #define GFX6_COMPRESSION_2H 2 98 99 enum ENUM_PACKED elk_conditional_mod { 100 ELK_CONDITIONAL_NONE = 0, 101 ELK_CONDITIONAL_Z = 1, 102 ELK_CONDITIONAL_NZ = 2, 103 ELK_CONDITIONAL_EQ = 1, /* Z */ 104 ELK_CONDITIONAL_NEQ = 2, /* NZ */ 105 ELK_CONDITIONAL_G = 3, 106 ELK_CONDITIONAL_GE = 4, 107 ELK_CONDITIONAL_L = 5, 108 ELK_CONDITIONAL_LE = 6, 109 ELK_CONDITIONAL_R = 7, /* Gen <= 5 */ 110 ELK_CONDITIONAL_O = 8, 111 ELK_CONDITIONAL_U = 9, 112 }; 113 114 #define ELK_DEBUG_NONE 0 115 #define ELK_DEBUG_BREAKPOINT 1 116 117 #define ELK_DEPENDENCY_NORMAL 0 118 #define ELK_DEPENDENCY_NOTCLEARED 1 119 #define ELK_DEPENDENCY_NOTCHECKED 2 120 #define ELK_DEPENDENCY_DISABLE 3 121 122 enum ENUM_PACKED elk_execution_size { 123 ELK_EXECUTE_1 = 0, 124 ELK_EXECUTE_2 = 1, 125 ELK_EXECUTE_4 = 2, 126 ELK_EXECUTE_8 = 3, 127 ELK_EXECUTE_16 = 4, 128 ELK_EXECUTE_32 = 5, 129 }; 130 131 enum ENUM_PACKED elk_horizontal_stride { 132 ELK_HORIZONTAL_STRIDE_0 = 0, 133 ELK_HORIZONTAL_STRIDE_1 = 1, 134 ELK_HORIZONTAL_STRIDE_2 = 2, 135 ELK_HORIZONTAL_STRIDE_4 = 3, 136 }; 137 138 enum ENUM_PACKED gfx10_align1_3src_src_horizontal_stride { 139 ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_0 = 0, 140 ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_1 = 1, 141 ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_2 = 2, 142 ELK_ALIGN1_3SRC_SRC_HORIZONTAL_STRIDE_4 = 3, 143 }; 144 145 enum ENUM_PACKED gfx10_align1_3src_dst_horizontal_stride { 146 ELK_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_1 = 0, 147 ELK_ALIGN1_3SRC_DST_HORIZONTAL_STRIDE_2 = 1, 148 }; 149 150 #define ELK_INSTRUCTION_NORMAL 0 151 #define ELK_INSTRUCTION_SATURATE 1 152 153 #define ELK_MASK_ENABLE 0 154 #define ELK_MASK_DISABLE 1 155 156 /** @{ 157 * 158 * Gfx6 has replaced "mask enable/disable" with WECtrl, which is 159 * effectively the same but much simpler to think about. Now, there 160 * are two contributors ANDed together to whether channels are 161 * executed: The predication on the instruction, and the channel write 162 * enable. 163 */ 164 /** 165 * This is the default value. It means that a channel's write enable is set 166 * if the per-channel IP is pointing at this instruction. 167 */ 168 #define ELK_WE_NORMAL 0 169 /** 170 * This is used like ELK_MASK_DISABLE, and causes all channels to have 171 * their write enable set. Note that predication still contributes to 172 * whether the channel actually gets written. 173 */ 174 #define ELK_WE_ALL 1 175 /** @} */ 176 177 enum elk_urb_write_flags { 178 ELK_URB_WRITE_NO_FLAGS = 0, 179 180 /** 181 * Causes a new URB entry to be allocated, and its address stored in the 182 * destination register (gen < 7). 183 */ 184 ELK_URB_WRITE_ALLOCATE = 0x1, 185 186 /** 187 * Causes the current URB entry to be deallocated (gen < 7). 188 */ 189 ELK_URB_WRITE_UNUSED = 0x2, 190 191 /** 192 * Causes the thread to terminate. 193 */ 194 ELK_URB_WRITE_EOT = 0x4, 195 196 /** 197 * Indicates that the given URB entry is complete, and may be sent further 198 * down the 3D pipeline (gen < 7). 199 */ 200 ELK_URB_WRITE_COMPLETE = 0x8, 201 202 /** 203 * Indicates that an additional offset (which may be different for the two 204 * vec4 slots) is stored in the message header (gen == 7). 205 */ 206 ELK_URB_WRITE_PER_SLOT_OFFSET = 0x10, 207 208 /** 209 * Indicates that the channel masks in the URB_WRITE message header should 210 * not be overridden to 0xff (gen == 7). 211 */ 212 ELK_URB_WRITE_USE_CHANNEL_MASKS = 0x20, 213 214 /** 215 * Indicates that the data should be sent to the URB using the 216 * URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7). This 217 * causes offsets to be interpreted as multiples of an OWORD instead of an 218 * HWORD, and only allows one OWORD to be written. 219 */ 220 ELK_URB_WRITE_OWORD = 0x40, 221 222 /** 223 * Convenient combination of flags: end the thread while simultaneously 224 * marking the given URB entry as complete. 225 */ 226 ELK_URB_WRITE_EOT_COMPLETE = ELK_URB_WRITE_EOT | ELK_URB_WRITE_COMPLETE, 227 228 /** 229 * Convenient combination of flags: mark the given URB entry as complete 230 * and simultaneously allocate a new one. 231 */ 232 ELK_URB_WRITE_ALLOCATE_COMPLETE = 233 ELK_URB_WRITE_ALLOCATE | ELK_URB_WRITE_COMPLETE, 234 }; 235 236 enum fb_write_logical_srcs { 237 FB_WRITE_LOGICAL_SRC_COLOR0, /* REQUIRED */ 238 FB_WRITE_LOGICAL_SRC_COLOR1, /* for dual source blend messages */ 239 FB_WRITE_LOGICAL_SRC_SRC0_ALPHA, 240 FB_WRITE_LOGICAL_SRC_SRC_DEPTH, /* gl_FragDepth */ 241 FB_WRITE_LOGICAL_SRC_DST_DEPTH, /* GFX4-5: passthrough from thread */ 242 FB_WRITE_LOGICAL_SRC_OMASK, /* Sample Mask (gl_SampleMask) */ 243 FB_WRITE_LOGICAL_SRC_COMPONENTS, /* REQUIRED */ 244 FB_WRITE_LOGICAL_NUM_SRCS 245 }; 246 247 enum tex_logical_srcs { 248 /** Texture coordinates */ 249 TEX_LOGICAL_SRC_COORDINATE, 250 /** Shadow comparator */ 251 TEX_LOGICAL_SRC_SHADOW_C, 252 /** dPdx if the operation takes explicit derivatives, otherwise LOD value */ 253 TEX_LOGICAL_SRC_LOD, 254 /** dPdy if the operation takes explicit derivatives */ 255 TEX_LOGICAL_SRC_LOD2, 256 /** Min LOD */ 257 TEX_LOGICAL_SRC_MIN_LOD, 258 /** Sample index */ 259 TEX_LOGICAL_SRC_SAMPLE_INDEX, 260 /** MCS data */ 261 TEX_LOGICAL_SRC_MCS, 262 /** REQUIRED: Texture surface index */ 263 TEX_LOGICAL_SRC_SURFACE, 264 /** Texture sampler index */ 265 TEX_LOGICAL_SRC_SAMPLER, 266 /** Texture surface bindless handle */ 267 TEX_LOGICAL_SRC_SURFACE_HANDLE, 268 /** Texture sampler bindless handle */ 269 TEX_LOGICAL_SRC_SAMPLER_HANDLE, 270 /** Texel offset for gathers */ 271 TEX_LOGICAL_SRC_TG4_OFFSET, 272 /** REQUIRED: Number of coordinate components (as UD immediate) */ 273 TEX_LOGICAL_SRC_COORD_COMPONENTS, 274 /** REQUIRED: Number of derivative components (as UD immediate) */ 275 TEX_LOGICAL_SRC_GRAD_COMPONENTS, 276 /** REQUIRED: request residency (as UD immediate) */ 277 TEX_LOGICAL_SRC_RESIDENCY, 278 279 TEX_LOGICAL_NUM_SRCS, 280 }; 281 282 enum pull_uniform_constant_srcs { 283 /** Surface binding table index */ 284 PULL_UNIFORM_CONSTANT_SRC_SURFACE, 285 /** Surface bindless handle */ 286 PULL_UNIFORM_CONSTANT_SRC_SURFACE_HANDLE, 287 /** Surface offset */ 288 PULL_UNIFORM_CONSTANT_SRC_OFFSET, 289 /** Pull size */ 290 PULL_UNIFORM_CONSTANT_SRC_SIZE, 291 292 PULL_UNIFORM_CONSTANT_SRCS, 293 }; 294 295 enum pull_varying_constant_srcs { 296 /** Surface binding table index */ 297 PULL_VARYING_CONSTANT_SRC_SURFACE, 298 /** Surface bindless handle */ 299 PULL_VARYING_CONSTANT_SRC_SURFACE_HANDLE, 300 /** Surface offset */ 301 PULL_VARYING_CONSTANT_SRC_OFFSET, 302 /** Pull alignment */ 303 PULL_VARYING_CONSTANT_SRC_ALIGNMENT, 304 305 PULL_VARYING_CONSTANT_SRCS, 306 }; 307 308 enum get_buffer_size_srcs { 309 /** Surface binding table index */ 310 GET_BUFFER_SIZE_SRC_SURFACE, 311 /** Surface bindless handle */ 312 GET_BUFFER_SIZE_SRC_SURFACE_HANDLE, 313 /** LOD */ 314 GET_BUFFER_SIZE_SRC_LOD, 315 316 GET_BUFFER_SIZE_SRCS 317 }; 318 319 enum surface_logical_srcs { 320 /** Surface binding table index */ 321 SURFACE_LOGICAL_SRC_SURFACE, 322 /** Surface bindless handle */ 323 SURFACE_LOGICAL_SRC_SURFACE_HANDLE, 324 /** Surface address; could be multi-dimensional for typed opcodes */ 325 SURFACE_LOGICAL_SRC_ADDRESS, 326 /** Data to be written or used in an atomic op */ 327 SURFACE_LOGICAL_SRC_DATA, 328 /** Surface number of dimensions. Affects the size of ADDRESS */ 329 SURFACE_LOGICAL_SRC_IMM_DIMS, 330 /** Per-opcode immediate argument. For atomics, this is the atomic opcode */ 331 SURFACE_LOGICAL_SRC_IMM_ARG, 332 /** 333 * Some instructions with side-effects should not be predicated on 334 * sample mask, e.g. lowered stores to scratch. 335 */ 336 SURFACE_LOGICAL_SRC_ALLOW_SAMPLE_MASK, 337 338 SURFACE_LOGICAL_NUM_SRCS 339 }; 340 341 enum a64_logical_srcs { 342 /** Address the A64 message operates on */ 343 A64_LOGICAL_ADDRESS, 344 /** Source for the operation (unused of LOAD ops) */ 345 A64_LOGICAL_SRC, 346 /** Per-opcode immediate argument. Number of dwords, bit size, or atomic op. */ 347 A64_LOGICAL_ARG, 348 /** 349 * Some instructions do want to run on helper lanes (like ray queries). 350 */ 351 A64_LOGICAL_ENABLE_HELPERS, 352 353 A64_LOGICAL_NUM_SRCS 354 }; 355 356 enum urb_logical_srcs { 357 URB_LOGICAL_SRC_HANDLE, 358 URB_LOGICAL_SRC_PER_SLOT_OFFSETS, 359 URB_LOGICAL_SRC_CHANNEL_MASK, 360 /** Data to be written. BAD_FILE for reads. */ 361 URB_LOGICAL_SRC_DATA, 362 URB_LOGICAL_SRC_COMPONENTS, 363 URB_LOGICAL_NUM_SRCS 364 }; 365 366 enum interpolator_logical_srcs { 367 /** Interpolation offset */ 368 INTERP_SRC_OFFSET, 369 /** Message data */ 370 INTERP_SRC_MSG_DESC, 371 /** Flag register for dynamic mode */ 372 INTERP_SRC_DYNAMIC_MODE, 373 374 INTERP_NUM_SRCS 375 }; 376 377 378 #ifdef __cplusplus 379 /** 380 * Allow elk_urb_write_flags enums to be ORed together. 381 */ 382 inline elk_urb_write_flags 383 operator|(elk_urb_write_flags x, elk_urb_write_flags y) 384 { 385 return static_cast<elk_urb_write_flags>(static_cast<int>(x) | 386 static_cast<int>(y)); 387 } 388 #endif 389 390 enum ENUM_PACKED elk_predicate { 391 ELK_PREDICATE_NONE = 0, 392 ELK_PREDICATE_NORMAL = 1, 393 ELK_PREDICATE_ALIGN1_ANYV = 2, 394 ELK_PREDICATE_ALIGN1_ALLV = 3, 395 ELK_PREDICATE_ALIGN1_ANY2H = 4, 396 ELK_PREDICATE_ALIGN1_ALL2H = 5, 397 ELK_PREDICATE_ALIGN1_ANY4H = 6, 398 ELK_PREDICATE_ALIGN1_ALL4H = 7, 399 ELK_PREDICATE_ALIGN1_ANY8H = 8, 400 ELK_PREDICATE_ALIGN1_ALL8H = 9, 401 ELK_PREDICATE_ALIGN1_ANY16H = 10, 402 ELK_PREDICATE_ALIGN1_ALL16H = 11, 403 ELK_PREDICATE_ALIGN1_ANY32H = 12, 404 ELK_PREDICATE_ALIGN1_ALL32H = 13, 405 ELK_PREDICATE_ALIGN16_REPLICATE_X = 2, 406 ELK_PREDICATE_ALIGN16_REPLICATE_Y = 3, 407 ELK_PREDICATE_ALIGN16_REPLICATE_Z = 4, 408 ELK_PREDICATE_ALIGN16_REPLICATE_W = 5, 409 ELK_PREDICATE_ALIGN16_ANY4H = 6, 410 ELK_PREDICATE_ALIGN16_ALL4H = 7, 411 XE2_PREDICATE_ANY = 2, 412 XE2_PREDICATE_ALL = 3 413 }; 414 415 enum ENUM_PACKED elk_reg_file { 416 ELK_ARCHITECTURE_REGISTER_FILE = 0, 417 ELK_GENERAL_REGISTER_FILE = 1, 418 ELK_MESSAGE_REGISTER_FILE = 2, 419 ELK_IMMEDIATE_VALUE = 3, 420 421 ARF = ELK_ARCHITECTURE_REGISTER_FILE, 422 FIXED_GRF = ELK_GENERAL_REGISTER_FILE, 423 MRF = ELK_MESSAGE_REGISTER_FILE, 424 IMM = ELK_IMMEDIATE_VALUE, 425 426 /* These are not hardware values */ 427 VGRF, 428 ATTR, 429 UNIFORM, /* prog_data->params[reg] */ 430 BAD_FILE, 431 }; 432 433 enum ENUM_PACKED gfx10_align1_3src_reg_file { 434 ELK_ALIGN1_3SRC_GENERAL_REGISTER_FILE = 0, 435 ELK_ALIGN1_3SRC_IMMEDIATE_VALUE = 1, /* src0, src2 */ 436 ELK_ALIGN1_3SRC_ACCUMULATOR = 1, /* dest, src1 */ 437 }; 438 439 /* CNL adds Align1 support for 3-src instructions. Bit 35 of the instruction 440 * word is "Execution Datatype" which controls whether the instruction operates 441 * on float or integer types. The register arguments have fields that offer 442 * more fine control their respective types. 443 */ 444 enum ENUM_PACKED gfx10_align1_3src_exec_type { 445 ELK_ALIGN1_3SRC_EXEC_TYPE_INT = 0, 446 ELK_ALIGN1_3SRC_EXEC_TYPE_FLOAT = 1, 447 }; 448 449 #define ELK_ARF_NULL 0x00 450 #define ELK_ARF_ADDRESS 0x10 451 #define ELK_ARF_ACCUMULATOR 0x20 452 #define ELK_ARF_FLAG 0x30 453 #define ELK_ARF_MASK 0x40 454 #define ELK_ARF_MASK_STACK 0x50 455 #define ELK_ARF_MASK_STACK_DEPTH 0x60 456 #define ELK_ARF_STATE 0x70 457 #define ELK_ARF_CONTROL 0x80 458 #define ELK_ARF_NOTIFICATION_COUNT 0x90 459 #define ELK_ARF_IP 0xA0 460 #define ELK_ARF_TDR 0xB0 461 #define ELK_ARF_TIMESTAMP 0xC0 462 463 #define ELK_MRF_COMPR4 (1 << 7) 464 465 #define ELK_AMASK 0 466 #define ELK_IMASK 1 467 #define ELK_LMASK 2 468 #define ELK_CMASK 3 469 470 471 472 #define ELK_THREAD_NORMAL 0 473 #define ELK_THREAD_ATOMIC 1 474 #define ELK_THREAD_SWITCH 2 475 476 enum ENUM_PACKED elk_vertical_stride { 477 ELK_VERTICAL_STRIDE_0 = 0, 478 ELK_VERTICAL_STRIDE_1 = 1, 479 ELK_VERTICAL_STRIDE_2 = 2, 480 ELK_VERTICAL_STRIDE_4 = 3, 481 ELK_VERTICAL_STRIDE_8 = 4, 482 ELK_VERTICAL_STRIDE_16 = 5, 483 ELK_VERTICAL_STRIDE_32 = 6, 484 ELK_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF, 485 }; 486 487 enum ENUM_PACKED gfx10_align1_3src_vertical_stride { 488 ELK_ALIGN1_3SRC_VERTICAL_STRIDE_0 = 0, 489 ELK_ALIGN1_3SRC_VERTICAL_STRIDE_1 = 1, 490 ELK_ALIGN1_3SRC_VERTICAL_STRIDE_2 = 1, 491 ELK_ALIGN1_3SRC_VERTICAL_STRIDE_4 = 2, 492 ELK_ALIGN1_3SRC_VERTICAL_STRIDE_8 = 3, 493 }; 494 495 enum ENUM_PACKED elk_width { 496 ELK_WIDTH_1 = 0, 497 ELK_WIDTH_2 = 1, 498 ELK_WIDTH_4 = 2, 499 ELK_WIDTH_8 = 3, 500 ELK_WIDTH_16 = 4, 501 }; 502 503 /** 504 * Message target: Shared Function ID for where to SEND a message. 505 * 506 * These are enumerated in the ISA reference under "send - Send Message". 507 * In particular, see the following tables: 508 * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition" 509 * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor" 510 * - Ivybridge PRM, Volume 1 Part 1, section 3.2.7 "GPE Function IDs" 511 */ 512 enum elk_message_target { 513 ELK_SFID_NULL = 0, 514 ELK_SFID_MATH = 1, /* Only valid on Gfx4-5 */ 515 ELK_SFID_SAMPLER = 2, 516 ELK_SFID_MESSAGE_GATEWAY = 3, 517 ELK_SFID_DATAPORT_READ = 4, 518 ELK_SFID_DATAPORT_WRITE = 5, 519 ELK_SFID_URB = 6, 520 ELK_SFID_THREAD_SPAWNER = 7, 521 ELK_SFID_VME = 8, 522 523 GFX6_SFID_DATAPORT_SAMPLER_CACHE = 4, 524 GFX6_SFID_DATAPORT_RENDER_CACHE = 5, 525 GFX6_SFID_DATAPORT_CONSTANT_CACHE = 9, 526 527 GFX7_SFID_DATAPORT_DATA_CACHE = 10, 528 GFX7_SFID_PIXEL_INTERPOLATOR = 11, 529 HSW_SFID_DATAPORT_DATA_CACHE_1 = 12, 530 HSW_SFID_CRE = 13, 531 }; 532 533 #define GFX7_MESSAGE_TARGET_DP_DATA_CACHE 10 534 535 #define ELK_SAMPLER_RETURN_FORMAT_FLOAT32 0 536 #define ELK_SAMPLER_RETURN_FORMAT_UINT32 2 537 #define ELK_SAMPLER_RETURN_FORMAT_SINT32 3 538 539 #define GFX8_SAMPLER_RETURN_FORMAT_32BITS 0 540 #define GFX8_SAMPLER_RETURN_FORMAT_16BITS 1 541 542 #define ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE 0 543 #define ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE 0 544 #define ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0 545 #define ELK_SAMPLER_MESSAGE_SIMD8_KILLPIX 1 546 #define ELK_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1 547 #define ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1 548 #define ELK_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2 549 #define ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2 550 #define ELK_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0 551 #define ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2 552 #define ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0 553 #define ELK_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1 554 #define ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1 555 #define ELK_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2 556 #define ELK_SAMPLER_MESSAGE_SIMD16_RESINFO 2 557 #define ELK_SAMPLER_MESSAGE_SIMD4X2_LD 3 558 #define ELK_SAMPLER_MESSAGE_SIMD8_LD 3 559 #define ELK_SAMPLER_MESSAGE_SIMD16_LD 3 560 561 #define GFX5_SAMPLER_MESSAGE_SAMPLE 0 562 #define GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS 1 563 #define GFX5_SAMPLER_MESSAGE_SAMPLE_LOD 2 564 #define GFX5_SAMPLER_MESSAGE_SAMPLE_COMPARE 3 565 #define GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS 4 566 #define GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5 567 #define GFX5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6 568 #define GFX5_SAMPLER_MESSAGE_SAMPLE_LD 7 569 #define GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4 8 570 #define GFX5_SAMPLER_MESSAGE_LOD 9 571 #define GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10 572 #define GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO 11 573 #define GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C 16 574 #define GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO 17 575 #define GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C 18 576 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20 577 #define GFX7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29 578 #define GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30 579 #define GFX7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31 580 581 /* for GFX5 only */ 582 #define ELK_SAMPLER_SIMD_MODE_SIMD4X2 0 583 #define ELK_SAMPLER_SIMD_MODE_SIMD8 1 584 #define ELK_SAMPLER_SIMD_MODE_SIMD16 2 585 #define ELK_SAMPLER_SIMD_MODE_SIMD32_64 3 586 587 #define ELK_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0 588 #define ELK_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1 589 #define ELK_DATAPORT_OWORD_BLOCK_2_OWORDS 2 590 #define ELK_DATAPORT_OWORD_BLOCK_4_OWORDS 3 591 #define ELK_DATAPORT_OWORD_BLOCK_8_OWORDS 4 592 #define ELK_DATAPORT_OWORD_BLOCK_OWORDS(n) \ 593 ((n) == 1 ? ELK_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \ 594 (n) == 2 ? ELK_DATAPORT_OWORD_BLOCK_2_OWORDS : \ 595 (n) == 4 ? ELK_DATAPORT_OWORD_BLOCK_4_OWORDS : \ 596 (n) == 8 ? ELK_DATAPORT_OWORD_BLOCK_8_OWORDS : \ 597 (abort(), ~0)) 598 #define ELK_DATAPORT_OWORD_BLOCK_DWORDS(n) \ 599 ((n) == 4 ? ELK_DATAPORT_OWORD_BLOCK_1_OWORDLOW : \ 600 (n) == 8 ? ELK_DATAPORT_OWORD_BLOCK_2_OWORDS : \ 601 (n) == 16 ? ELK_DATAPORT_OWORD_BLOCK_4_OWORDS : \ 602 (n) == 32 ? ELK_DATAPORT_OWORD_BLOCK_8_OWORDS : \ 603 (abort(), ~0)) 604 605 #define ELK_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0 606 #define ELK_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2 607 608 #define ELK_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2 609 #define ELK_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3 610 611 /* This one stays the same across generations. */ 612 #define ELK_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0 613 /* GFX4 */ 614 #define ELK_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1 615 #define ELK_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2 616 #define ELK_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3 617 /* G45, GFX5 */ 618 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1 619 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2 620 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ 3 621 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4 622 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6 623 /* GFX6 */ 624 #define GFX6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1 625 #define GFX6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2 626 #define GFX6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4 627 #define GFX6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5 628 #define GFX6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6 629 630 #define ELK_DATAPORT_READ_TARGET_DATA_CACHE 0 631 #define ELK_DATAPORT_READ_TARGET_RENDER_CACHE 1 632 #define ELK_DATAPORT_READ_TARGET_SAMPLER_CACHE 2 633 634 #define ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0 635 #define ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1 636 #define ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2 637 #define ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3 638 #define ELK_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4 639 640 #define ELK_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0 641 #define ELK_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1 642 #define ELK_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2 643 #define ELK_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3 644 #define ELK_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4 645 #define ELK_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5 646 #define ELK_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7 647 648 /* GFX6 */ 649 #define GFX6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7 650 #define GFX6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8 651 #define GFX6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9 652 #define GFX6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10 653 #define GFX6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 11 654 #define GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12 655 #define GFX6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13 656 #define GFX6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14 657 658 /* GFX7 */ 659 #define GFX7_DATAPORT_RC_MEDIA_BLOCK_READ 4 660 #define GFX7_DATAPORT_RC_TYPED_SURFACE_READ 5 661 #define GFX7_DATAPORT_RC_TYPED_ATOMIC_OP 6 662 #define GFX7_DATAPORT_RC_MEMORY_FENCE 7 663 #define GFX7_DATAPORT_RC_MEDIA_BLOCK_WRITE 10 664 #define GFX7_DATAPORT_RC_RENDER_TARGET_WRITE 12 665 #define GFX7_DATAPORT_RC_TYPED_SURFACE_WRITE 13 666 #define GFX7_DATAPORT_DC_OWORD_BLOCK_READ 0 667 #define GFX7_DATAPORT_DC_UNALIGNED_OWORD_BLOCK_READ 1 668 #define GFX7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ 2 669 #define GFX7_DATAPORT_DC_DWORD_SCATTERED_READ 3 670 #define GFX7_DATAPORT_DC_BYTE_SCATTERED_READ 4 671 #define GFX7_DATAPORT_DC_UNTYPED_SURFACE_READ 5 672 #define GFX7_DATAPORT_DC_UNTYPED_ATOMIC_OP 6 673 #define GFX7_DATAPORT_DC_MEMORY_FENCE 7 674 #define GFX7_DATAPORT_DC_OWORD_BLOCK_WRITE 8 675 #define GFX7_DATAPORT_DC_OWORD_DUAL_BLOCK_WRITE 10 676 #define GFX7_DATAPORT_DC_DWORD_SCATTERED_WRITE 11 677 #define GFX7_DATAPORT_DC_BYTE_SCATTERED_WRITE 12 678 #define GFX7_DATAPORT_DC_UNTYPED_SURFACE_WRITE 13 679 680 #define GFX7_DATAPORT_SCRATCH_READ ((1 << 18) | \ 681 (0 << 17)) 682 #define GFX7_DATAPORT_SCRATCH_WRITE ((1 << 18) | \ 683 (1 << 17)) 684 #define GFX7_DATAPORT_SCRATCH_NUM_REGS_SHIFT 12 685 686 #define GFX7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET 0 687 #define GFX7_PIXEL_INTERPOLATOR_LOC_SAMPLE 1 688 #define GFX7_PIXEL_INTERPOLATOR_LOC_CENTROID 2 689 #define GFX7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET 3 690 691 /* HSW */ 692 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ 0 693 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ 1 694 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_READ 2 695 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_READ 3 696 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_READ 4 697 #define HSW_DATAPORT_DC_PORT0_MEMORY_FENCE 7 698 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_WRITE 8 699 #define HSW_DATAPORT_DC_PORT0_OWORD_DUAL_BLOCK_WRITE 10 700 #define HSW_DATAPORT_DC_PORT0_DWORD_SCATTERED_WRITE 11 701 #define HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE 12 702 703 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ 1 704 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP 2 705 #define HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2 3 706 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_READ 4 707 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_READ 5 708 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP 6 709 #define HSW_DATAPORT_DC_PORT1_TYPED_ATOMIC_OP_SIMD4X2 7 710 #define HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_WRITE 9 711 #define HSW_DATAPORT_DC_PORT1_MEDIA_BLOCK_WRITE 10 712 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP 11 713 #define HSW_DATAPORT_DC_PORT1_ATOMIC_COUNTER_OP_SIMD4X2 12 714 #define HSW_DATAPORT_DC_PORT1_TYPED_SURFACE_WRITE 13 715 #define GFX9_DATAPORT_DC_PORT1_A64_SCATTERED_READ 0x10 716 #define GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_READ 0x11 717 #define GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_ATOMIC_OP 0x12 718 #define GFX8_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_READ 0x14 719 #define GFX8_DATAPORT_DC_PORT1_A64_OWORD_BLOCK_WRITE 0x15 720 #define GFX8_DATAPORT_DC_PORT1_A64_UNTYPED_SURFACE_WRITE 0x19 721 #define GFX8_DATAPORT_DC_PORT1_A64_SCATTERED_WRITE 0x1a 722 723 /* A64 scattered message subtype */ 724 #define GFX8_A64_SCATTERED_SUBTYPE_BYTE 0 725 #define GFX8_A64_SCATTERED_SUBTYPE_DWORD 1 726 #define GFX8_A64_SCATTERED_SUBTYPE_QWORD 2 727 #define GFX8_A64_SCATTERED_SUBTYPE_HWORD 3 728 729 /* Dataport special binding table indices: */ 730 #define ELK_BTI_STATELESS 255 731 #define GFX7_BTI_SLM 254 732 733 #define HSW_BTI_STATELESS_LOCALLY_COHERENT 255 734 #define HSW_BTI_STATELESS_NON_COHERENT 253 735 #define HSW_BTI_STATELESS_GLOBALLY_COHERENT 252 736 #define HSW_BTI_STATELESS_LLC_COHERENT 251 737 #define HSW_BTI_STATELESS_L3_UNCACHED 250 738 739 /* The hardware docs are a bit contradictory here. On Haswell, where they 740 * first added cache ability control, there were 5 different cache modes (see 741 * HSW_BTI_STATELESS_* above). On Broadwell, they reduced to two: 742 * 743 * - IA-Coherent (BTI=255): Coherent within Gen and coherent within the 744 * entire IA cache memory hierarchy. 745 * 746 * - Non-Coherent (BTI=253): Coherent within Gen, same cache type. 747 * 748 * Information about stateless cache coherency can be found in the "A32 749 * Stateless" section of the "3D Media GPGPU" volume of the PRM for each 750 * hardware generation. 751 * 752 * Unfortunately, the docs for MDC_STATELESS appear to have been copied and 753 * pasted from Haswell and give the Haswell definitions for the BTI values of 754 * 255 and 253 including a warning about accessing 253 surfaces from multiple 755 * threads. This seems to be a copy+paste error and the definitions from the 756 * "A32 Stateless" section should be trusted instead. 757 * 758 * Note that because the DRM sets bit 4 of HDC_CHICKEN0 on BDW, CHV and at 759 * least some pre-production steppings of SKL due to WaForceEnableNonCoherent, 760 * HDC memory access may have been overridden by the kernel to be non-coherent 761 * (matching the behavior of the same BTI on pre-Gfx8 hardware) and BTI 255 762 * may actually be an alias for BTI 253. 763 */ 764 #define GFX8_BTI_STATELESS_IA_COHERENT 255 765 #define GFX8_BTI_STATELESS_NON_COHERENT 253 766 767 /* Dataport atomic operations for Untyped Atomic Integer Operation message 768 * (and others). 769 */ 770 #define ELK_AOP_AND 1 771 #define ELK_AOP_OR 2 772 #define ELK_AOP_XOR 3 773 #define ELK_AOP_MOV 4 774 #define ELK_AOP_INC 5 775 #define ELK_AOP_DEC 6 776 #define ELK_AOP_ADD 7 777 #define ELK_AOP_SUB 8 778 #define ELK_AOP_REVSUB 9 779 #define ELK_AOP_IMAX 10 780 #define ELK_AOP_IMIN 11 781 #define ELK_AOP_UMAX 12 782 #define ELK_AOP_UMIN 13 783 #define ELK_AOP_CMPWR 14 784 #define ELK_AOP_PREDEC 15 785 786 /* Dataport atomic operations for Untyped Atomic Float Operation message. */ 787 #define ELK_AOP_FMAX 1 788 #define ELK_AOP_FMIN 2 789 #define ELK_AOP_FCMPWR 3 790 #define ELK_AOP_FADD 4 791 792 #define ELK_MATH_FUNCTION_INV 1 793 #define ELK_MATH_FUNCTION_LOG 2 794 #define ELK_MATH_FUNCTION_EXP 3 795 #define ELK_MATH_FUNCTION_SQRT 4 796 #define ELK_MATH_FUNCTION_RSQ 5 797 #define ELK_MATH_FUNCTION_SIN 6 798 #define ELK_MATH_FUNCTION_COS 7 799 #define ELK_MATH_FUNCTION_SINCOS 8 /* gfx4, gfx5 */ 800 #define ELK_MATH_FUNCTION_FDIV 9 /* gfx6+ */ 801 #define ELK_MATH_FUNCTION_POW 10 802 #define ELK_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11 803 #define ELK_MATH_FUNCTION_INT_DIV_QUOTIENT 12 804 #define ELK_MATH_FUNCTION_INT_DIV_REMAINDER 13 805 #define GFX8_MATH_FUNCTION_INVM 14 806 #define GFX8_MATH_FUNCTION_RSQRTM 15 807 808 #define ELK_MATH_INTEGER_UNSIGNED 0 809 #define ELK_MATH_INTEGER_SIGNED 1 810 811 #define ELK_MATH_PRECISION_FULL 0 812 #define ELK_MATH_PRECISION_PARTIAL 1 813 814 #define ELK_MATH_SATURATE_NONE 0 815 #define ELK_MATH_SATURATE_SATURATE 1 816 817 #define ELK_MATH_DATA_VECTOR 0 818 #define ELK_MATH_DATA_SCALAR 1 819 820 #define ELK_URB_OPCODE_WRITE_HWORD 0 821 #define ELK_URB_OPCODE_WRITE_OWORD 1 822 #define ELK_URB_OPCODE_READ_HWORD 2 823 #define ELK_URB_OPCODE_READ_OWORD 3 824 #define GFX7_URB_OPCODE_ATOMIC_MOV 4 825 #define GFX7_URB_OPCODE_ATOMIC_INC 5 826 #define GFX8_URB_OPCODE_ATOMIC_ADD 6 827 #define GFX8_URB_OPCODE_SIMD8_WRITE 7 828 #define GFX8_URB_OPCODE_SIMD8_READ 8 829 830 #define ELK_URB_SWIZZLE_NONE 0 831 #define ELK_URB_SWIZZLE_INTERLEAVE 1 832 #define ELK_URB_SWIZZLE_TRANSPOSE 2 833 834 #define ELK_SCRATCH_SPACE_SIZE_1K 0 835 #define ELK_SCRATCH_SPACE_SIZE_2K 1 836 #define ELK_SCRATCH_SPACE_SIZE_4K 2 837 #define ELK_SCRATCH_SPACE_SIZE_8K 3 838 #define ELK_SCRATCH_SPACE_SIZE_16K 4 839 #define ELK_SCRATCH_SPACE_SIZE_32K 5 840 #define ELK_SCRATCH_SPACE_SIZE_64K 6 841 #define ELK_SCRATCH_SPACE_SIZE_128K 7 842 #define ELK_SCRATCH_SPACE_SIZE_256K 8 843 #define ELK_SCRATCH_SPACE_SIZE_512K 9 844 #define ELK_SCRATCH_SPACE_SIZE_1M 10 845 #define ELK_SCRATCH_SPACE_SIZE_2M 11 846 847 #define ELK_MESSAGE_GATEWAY_SFID_OPEN_GATEWAY 0 848 #define ELK_MESSAGE_GATEWAY_SFID_CLOSE_GATEWAY 1 849 #define ELK_MESSAGE_GATEWAY_SFID_FORWARD_MSG 2 850 #define ELK_MESSAGE_GATEWAY_SFID_GET_TIMESTAMP 3 851 #define ELK_MESSAGE_GATEWAY_SFID_BARRIER_MSG 4 852 #define ELK_MESSAGE_GATEWAY_SFID_UPDATE_GATEWAY_STATE 5 853 #define ELK_MESSAGE_GATEWAY_SFID_MMIO_READ_WRITE 6 854 855 856 /* Gfx7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size 857 * is 2^9, or 512. It's counted in multiples of 64 bytes. 858 * 859 * Identical for VS, DS, and HS. 860 */ 861 #define GFX7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64) 862 #define GFX7_MAX_DS_URB_ENTRY_SIZE_BYTES (512*64) 863 #define GFX7_MAX_HS_URB_ENTRY_SIZE_BYTES (512*64) 864 #define GFX7_MAX_VS_URB_ENTRY_SIZE_BYTES (512*64) 865 866 #define ELK_GS_EDGE_INDICATOR_0 (1 << 8) 867 #define ELK_GS_EDGE_INDICATOR_1 (1 << 9) 868 869 /* Gfx6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit 870 * (128 bytes) URB rows and the maximum allowed value is 5 rows. 871 */ 872 #define GFX6_MAX_GS_URB_ENTRY_SIZE_BYTES (5*128) 873 874 /* GS Thread Payload 875 */ 876 877 /* 3DSTATE_GS "Output Vertex Size" has an effective maximum of 62. It's 878 * counted in multiples of 16 bytes. 879 */ 880 #define GFX7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES (62*16) 881 882 883 /* R0 */ 884 # define GFX7_GS_PAYLOAD_INSTANCE_ID_SHIFT 27 885 886 /* CR0.0[5:4] Floating-Point Rounding Modes 887 * Skylake PRM, Volume 7 Part 1, "Control Register", page 756 888 */ 889 890 #define ELK_CR0_RND_MODE_MASK 0x30 891 #define ELK_CR0_RND_MODE_SHIFT 4 892 893 enum ENUM_PACKED elk_rnd_mode { 894 ELK_RND_MODE_RTNE = 0, /* Round to Nearest or Even */ 895 ELK_RND_MODE_RU = 1, /* Round Up, toward +inf */ 896 ELK_RND_MODE_RD = 2, /* Round Down, toward -inf */ 897 ELK_RND_MODE_RTZ = 3, /* Round Toward Zero */ 898 ELK_RND_MODE_UNSPECIFIED, /* Unspecified rounding mode */ 899 }; 900 901 #define ELK_CR0_FP64_DENORM_PRESERVE (1 << 6) 902 #define ELK_CR0_FP32_DENORM_PRESERVE (1 << 7) 903 #define ELK_CR0_FP16_DENORM_PRESERVE (1 << 10) 904 905 #define ELK_CR0_FP_MODE_MASK (ELK_CR0_FP64_DENORM_PRESERVE | \ 906 ELK_CR0_FP32_DENORM_PRESERVE | \ 907 ELK_CR0_FP16_DENORM_PRESERVE | \ 908 ELK_CR0_RND_MODE_MASK) 909 910 /* MDC_DS - Data Size Message Descriptor Control Field 911 * Skylake PRM, Volume 2d, page 129 912 * 913 * Specifies the number of Bytes to be read or written per Dword used at 914 * byte_scattered read/write and byte_scaled read/write messages. 915 */ 916 #define GFX7_BYTE_SCATTERED_DATA_ELEMENT_BYTE 0 917 #define GFX7_BYTE_SCATTERED_DATA_ELEMENT_WORD 1 918 #define GFX7_BYTE_SCATTERED_DATA_ELEMENT_DWORD 2 919 920 /* Starting with Xe-HPG, the old dataport was massively reworked dataport. 921 * The new thing, called Load/Store Cache or LSC, has a significantly improved 922 * interface. Instead of bespoke messages for every case, there's basically 923 * one or two messages with different bits to control things like address 924 * size, how much data is read/written, etc. It's way nicer but also means we 925 * get to rewrite all our dataport encoding/decoding code. This patch kicks 926 * off the party with all of the new enums. 927 */ 928 enum elk_lsc_opcode { 929 LSC_OP_LOAD = 0, 930 LSC_OP_LOAD_CMASK = 2, 931 LSC_OP_STORE = 4, 932 LSC_OP_STORE_CMASK = 6, 933 LSC_OP_ATOMIC_INC = 8, 934 LSC_OP_ATOMIC_DEC = 9, 935 LSC_OP_ATOMIC_LOAD = 10, 936 LSC_OP_ATOMIC_STORE = 11, 937 LSC_OP_ATOMIC_ADD = 12, 938 LSC_OP_ATOMIC_SUB = 13, 939 LSC_OP_ATOMIC_MIN = 14, 940 LSC_OP_ATOMIC_MAX = 15, 941 LSC_OP_ATOMIC_UMIN = 16, 942 LSC_OP_ATOMIC_UMAX = 17, 943 LSC_OP_ATOMIC_CMPXCHG = 18, 944 LSC_OP_ATOMIC_FADD = 19, 945 LSC_OP_ATOMIC_FSUB = 20, 946 LSC_OP_ATOMIC_FMIN = 21, 947 LSC_OP_ATOMIC_FMAX = 22, 948 LSC_OP_ATOMIC_FCMPXCHG = 23, 949 LSC_OP_ATOMIC_AND = 24, 950 LSC_OP_ATOMIC_OR = 25, 951 LSC_OP_ATOMIC_XOR = 26, 952 LSC_OP_FENCE = 31 953 }; 954 955 /* 956 * Specifies the size of the dataport address payload in registers. 957 */ 958 enum ENUM_PACKED lsc_addr_reg_size { 959 LSC_ADDR_REG_SIZE_1 = 1, 960 LSC_ADDR_REG_SIZE_2 = 2, 961 LSC_ADDR_REG_SIZE_3 = 3, 962 LSC_ADDR_REG_SIZE_4 = 4, 963 LSC_ADDR_REG_SIZE_6 = 6, 964 LSC_ADDR_REG_SIZE_8 = 8, 965 }; 966 967 /* 968 * Specifies the size of the address payload item in a dataport message. 969 */ 970 enum ENUM_PACKED lsc_addr_size { 971 LSC_ADDR_SIZE_A16 = 1, /* 16-bit address offset */ 972 LSC_ADDR_SIZE_A32 = 2, /* 32-bit address offset */ 973 LSC_ADDR_SIZE_A64 = 3, /* 64-bit address offset */ 974 }; 975 976 /* 977 * Specifies the type of the address payload item in a dataport message. The 978 * address type specifies how the dataport message decodes the Extended 979 * Descriptor for the surface attributes and address calculation. 980 */ 981 enum ENUM_PACKED lsc_addr_surface_type { 982 LSC_ADDR_SURFTYPE_FLAT = 0, /* Flat */ 983 LSC_ADDR_SURFTYPE_BSS = 1, /* Bindless surface state */ 984 LSC_ADDR_SURFTYPE_SS = 2, /* Surface state */ 985 LSC_ADDR_SURFTYPE_BTI = 3, /* Binding table index */ 986 }; 987 988 /* 989 * Specifies the dataport message override to the default L1 and L3 memory 990 * cache policies. Dataport L1 cache policies are uncached (UC), cached (C), 991 * cache streaming (S) and invalidate-after-read (IAR). Dataport L3 cache 992 * policies are uncached (UC) and cached (C). 993 */ 994 enum lsc_cache_load { 995 /* No override. Use the non-pipelined state or surface state cache settings 996 * for L1 and L3. 997 */ 998 LSC_CACHE_LOAD_L1STATE_L3MOCS = 0, 999 /* Override to L1 uncached and L3 uncached */ 1000 LSC_CACHE_LOAD_L1UC_L3UC = 1, 1001 /* Override to L1 uncached and L3 cached */ 1002 LSC_CACHE_LOAD_L1UC_L3C = 2, 1003 /* Override to L1 cached and L3 uncached */ 1004 LSC_CACHE_LOAD_L1C_L3UC = 3, 1005 /* Override to cache at both L1 and L3 */ 1006 LSC_CACHE_LOAD_L1C_L3C = 4, 1007 /* Override to L1 streaming load and L3 uncached */ 1008 LSC_CACHE_LOAD_L1S_L3UC = 5, 1009 /* Override to L1 streaming load and L3 cached */ 1010 LSC_CACHE_LOAD_L1S_L3C = 6, 1011 /* For load messages, override to L1 invalidate-after-read, and L3 cached. */ 1012 LSC_CACHE_LOAD_L1IAR_L3C = 7, 1013 }; 1014 1015 /* 1016 * Specifies the dataport message override to the default L1 and L3 memory 1017 * cache policies. Dataport L1 cache policies are uncached (UC), cached (C), 1018 * streaming (S) and invalidate-after-read (IAR). Dataport L3 cache policies 1019 * are uncached (UC), cached (C), cached-as-a-constand (CC) and 1020 * invalidate-after-read (IAR). 1021 */ 1022 enum PACKED xe2_lsc_cache_load { 1023 /* No override. Use the non-pipelined or surface state cache settings for L1 1024 * and L3. 1025 */ 1026 XE2_LSC_CACHE_LOAD_L1STATE_L3MOCS = 0, 1027 /* Override to L1 uncached and L3 uncached */ 1028 XE2_LSC_CACHE_LOAD_L1UC_L3UC = 2, 1029 /* Override to L1 uncached and L3 cached */ 1030 XE2_LSC_CACHE_LOAD_L1UC_L3C = 4, 1031 /* Override to L1 uncached and L3 cached as a constant */ 1032 XE2_LSC_CACHE_LOAD_L1UC_L3CC = 5, 1033 /* Override to L1 cached and L3 uncached */ 1034 XE2_LSC_CACHE_LOAD_L1C_L3UC = 6, 1035 /* Override to L1 cached and L3 cached */ 1036 XE2_LSC_CACHE_LOAD_L1C_L3C = 8, 1037 /* Override to L1 cached and L3 cached as a constant */ 1038 XE2_LSC_CACHE_LOAD_L1C_L3CC = 9, 1039 /* Override to L1 cached as streaming load and L3 uncached */ 1040 XE2_LSC_CACHE_LOAD_L1S_L3UC = 10, 1041 /* Override to L1 cached as streaming load and L3 cached */ 1042 XE2_LSC_CACHE_LOAD_L1S_L3C = 12, 1043 /* Override to L1 and L3 invalidate after read */ 1044 XE2_LSC_CACHE_LOAD_L1IAR_L3IAR = 14, 1045 1046 }; 1047 1048 /* 1049 * Specifies the dataport message override to the default L1 and L3 memory 1050 * cache policies. Dataport L1 cache policies are uncached (UC), write-through 1051 * (WT), write-back (WB) and streaming (S). Dataport L3 cache policies are 1052 * uncached (UC) and cached (WB). 1053 */ 1054 enum ENUM_PACKED lsc_cache_store { 1055 /* No override. Use the non-pipelined or surface state cache settings for L1 1056 * and L3. 1057 */ 1058 LSC_CACHE_STORE_L1STATE_L3MOCS = 0, 1059 /* Override to L1 uncached and L3 uncached */ 1060 LSC_CACHE_STORE_L1UC_L3UC = 1, 1061 /* Override to L1 uncached and L3 cached */ 1062 LSC_CACHE_STORE_L1UC_L3WB = 2, 1063 /* Override to L1 write-through and L3 uncached */ 1064 LSC_CACHE_STORE_L1WT_L3UC = 3, 1065 /* Override to L1 write-through and L3 cached */ 1066 LSC_CACHE_STORE_L1WT_L3WB = 4, 1067 /* Override to L1 streaming and L3 uncached */ 1068 LSC_CACHE_STORE_L1S_L3UC = 5, 1069 /* Override to L1 streaming and L3 cached */ 1070 LSC_CACHE_STORE_L1S_L3WB = 6, 1071 /* Override to L1 write-back, and L3 cached */ 1072 LSC_CACHE_STORE_L1WB_L3WB = 7, 1073 1074 }; 1075 1076 /* 1077 * Specifies the dataport message override to the default L1 and L3 memory 1078 * cache policies. Dataport L1 cache policies are uncached (UC), write-through 1079 * (WT), write-back (WB) and streaming (S). Dataport L3 cache policies are 1080 * uncached (UC) and cached (WB). 1081 */ 1082 enum PACKED xe2_lsc_cache_store { 1083 /* No override. Use the non-pipelined or surface state cache settings for L1 1084 * and L3. 1085 */ 1086 XE2_LSC_CACHE_STORE_L1STATE_L3MOCS = 0, 1087 /* Override to L1 uncached and L3 uncached */ 1088 XE2_LSC_CACHE_STORE_L1UC_L3UC = 2, 1089 /* Override to L1 uncached and L3 cached */ 1090 XE2_LSC_CACHE_STORE_L1UC_L3WB = 4, 1091 /* Override to L1 write-through and L3 uncached */ 1092 XE2_LSC_CACHE_STORE_L1WT_L3UC = 6, 1093 /* Override to L1 write-through and L3 cached */ 1094 XE2_LSC_CACHE_STORE_L1WT_L3WB = 8, 1095 /* Override to L1 streaming and L3 uncached */ 1096 XE2_LSC_CACHE_STORE_L1S_L3UC = 10, 1097 /* Override to L1 streaming and L3 cached */ 1098 XE2_LSC_CACHE_STORE_L1S_L3WB = 12, 1099 /* Override to L1 write-back and L3 cached */ 1100 XE2_LSC_CACHE_STORE_L1WB_L3WB = 14, 1101 1102 }; 1103 1104 #define LSC_CACHE(devinfo, l_or_s, cc) \ 1105 ((devinfo)->ver < 20 ? (unsigned)LSC_CACHE_ ## l_or_s ## _ ## cc : \ 1106 (unsigned)XE2_LSC_CACHE_ ## l_or_s ## _ ## cc) 1107 1108 /* 1109 * Specifies which components of the data payload 4-element vector (X,Y,Z,W) is 1110 * packed into the register payload. 1111 */ 1112 enum ENUM_PACKED lsc_cmask { 1113 LSC_CMASK_X = 0x1, 1114 LSC_CMASK_Y = 0x2, 1115 LSC_CMASK_XY = 0x3, 1116 LSC_CMASK_Z = 0x4, 1117 LSC_CMASK_XZ = 0x5, 1118 LSC_CMASK_YZ = 0x6, 1119 LSC_CMASK_XYZ = 0x7, 1120 LSC_CMASK_W = 0x8, 1121 LSC_CMASK_XW = 0x9, 1122 LSC_CMASK_YW = 0xa, 1123 LSC_CMASK_XYW = 0xb, 1124 LSC_CMASK_ZW = 0xc, 1125 LSC_CMASK_XZW = 0xd, 1126 LSC_CMASK_YZW = 0xe, 1127 LSC_CMASK_XYZW = 0xf, 1128 }; 1129 1130 /* 1131 * Specifies the size of the data payload item in a dataport message. 1132 */ 1133 enum ENUM_PACKED lsc_data_size { 1134 /* 8-bit scalar data value in memory, packed into a 8-bit data value in 1135 * register. 1136 */ 1137 LSC_DATA_SIZE_D8 = 0, 1138 /* 16-bit scalar data value in memory, packed into a 16-bit data value in 1139 * register. 1140 */ 1141 LSC_DATA_SIZE_D16 = 1, 1142 /* 32-bit scalar data value in memory, packed into 32-bit data value in 1143 * register. 1144 */ 1145 LSC_DATA_SIZE_D32 = 2, 1146 /* 64-bit scalar data value in memory, packed into 64-bit data value in 1147 * register. 1148 */ 1149 LSC_DATA_SIZE_D64 = 3, 1150 /* 8-bit scalar data value in memory, packed into 32-bit unsigned data value 1151 * in register. 1152 */ 1153 LSC_DATA_SIZE_D8U32 = 4, 1154 /* 16-bit scalar data value in memory, packed into 32-bit unsigned data 1155 * value in register. 1156 */ 1157 LSC_DATA_SIZE_D16U32 = 5, 1158 /* 16-bit scalar BigFloat data value in memory, packed into 32-bit float 1159 * value in register. 1160 */ 1161 LSC_DATA_SIZE_D16BF32 = 6, 1162 }; 1163 1164 /* 1165 * Enum specifies the scope of the fence. 1166 */ 1167 enum ENUM_PACKED lsc_fence_scope { 1168 /* Wait until all previous memory transactions from this thread are observed 1169 * within the local thread-group. 1170 */ 1171 LSC_FENCE_THREADGROUP = 0, 1172 /* Wait until all previous memory transactions from this thread are observed 1173 * within the local sub-slice. 1174 */ 1175 LSC_FENCE_LOCAL = 1, 1176 /* Wait until all previous memory transactions from this thread are observed 1177 * in the local tile. 1178 */ 1179 LSC_FENCE_TILE = 2, 1180 /* Wait until all previous memory transactions from this thread are observed 1181 * in the local GPU. 1182 */ 1183 LSC_FENCE_GPU = 3, 1184 /* Wait until all previous memory transactions from this thread are observed 1185 * across all GPUs in the system. 1186 */ 1187 LSC_FENCE_ALL_GPU = 4, 1188 /* Wait until all previous memory transactions from this thread are observed 1189 * at the "system" level. 1190 */ 1191 LSC_FENCE_SYSTEM_RELEASE = 5, 1192 /* For GPUs that do not follow PCIe Write ordering for downstream writes 1193 * targeting device memory, a fence message with scope=System_Acquire will 1194 * commit to device memory all downstream and peer writes that have reached 1195 * the device. 1196 */ 1197 LSC_FENCE_SYSTEM_ACQUIRE = 6, 1198 }; 1199 1200 /* 1201 * Specifies the type of cache flush operation to perform after a fence is 1202 * complete. 1203 */ 1204 enum ENUM_PACKED lsc_flush_type { 1205 LSC_FLUSH_TYPE_NONE = 0, 1206 /* 1207 * For a R/W cache, evict dirty lines (M to I state) and invalidate clean 1208 * lines. For a RO cache, invalidate clean lines. 1209 */ 1210 LSC_FLUSH_TYPE_EVICT = 1, 1211 /* 1212 * For both R/W and RO cache, invalidate clean lines in the cache. 1213 */ 1214 LSC_FLUSH_TYPE_INVALIDATE = 2, 1215 /* 1216 * For a R/W cache, invalidate dirty lines (M to I state), without 1217 * write-back to next level. This opcode does nothing for a RO cache. 1218 */ 1219 LSC_FLUSH_TYPE_DISCARD = 3, 1220 /* 1221 * For a R/W cache, write-back dirty lines to the next level, but kept in 1222 * the cache as "clean" (M to V state). This opcode does nothing for a RO 1223 * cache. 1224 */ 1225 LSC_FLUSH_TYPE_CLEAN = 4, 1226 /* 1227 * Flush "RW" section of the L3 cache, but leave L1 and L2 caches untouched. 1228 */ 1229 LSC_FLUSH_TYPE_L3ONLY = 5, 1230 /* 1231 * HW maps this flush type internally to NONE. 1232 */ 1233 LSC_FLUSH_TYPE_NONE_6 = 6, 1234 1235 }; 1236 1237 enum ENUM_PACKED lsc_backup_fence_routing { 1238 /* Normal routing: UGM fence is routed to UGM pipeline. */ 1239 LSC_NORMAL_ROUTING, 1240 /* Route UGM fence to LSC unit. */ 1241 LSC_ROUTE_TO_LSC, 1242 }; 1243 1244 /* 1245 * Specifies the size of the vector in a dataport message. 1246 */ 1247 enum ENUM_PACKED lsc_vect_size { 1248 LSC_VECT_SIZE_V1 = 0, /* vector length 1 */ 1249 LSC_VECT_SIZE_V2 = 1, /* vector length 2 */ 1250 LSC_VECT_SIZE_V3 = 2, /* Vector length 3 */ 1251 LSC_VECT_SIZE_V4 = 3, /* Vector length 4 */ 1252 LSC_VECT_SIZE_V8 = 4, /* Vector length 8 */ 1253 LSC_VECT_SIZE_V16 = 5, /* Vector length 16 */ 1254 LSC_VECT_SIZE_V32 = 6, /* Vector length 32 */ 1255 LSC_VECT_SIZE_V64 = 7, /* Vector length 64 */ 1256 }; 1257 1258 #define LSC_ONE_ADDR_REG 1 1259