1 /* 2 * Copyright © 2024 Intel Corporation 3 * SPDX-License-Identifier: MIT 4 */ 5 6 #pragma once 7 8 #ifdef __cplusplus 9 extern "C" { 10 #endif 11 12 enum elk_opcode { 13 /* These are the actual hardware instructions. */ 14 ELK_OPCODE_ILLEGAL, 15 ELK_OPCODE_MOV, 16 ELK_OPCODE_SEL, 17 ELK_OPCODE_MOVI, /**< G45+ */ 18 ELK_OPCODE_NOT, 19 ELK_OPCODE_AND, 20 ELK_OPCODE_OR, 21 ELK_OPCODE_XOR, 22 ELK_OPCODE_SHR, 23 ELK_OPCODE_SHL, 24 ELK_OPCODE_DIM, /**< Gfx7.5 only */ 25 ELK_OPCODE_SMOV, /**< Gfx8+ */ 26 ELK_OPCODE_ASR, 27 ELK_OPCODE_CMP, 28 ELK_OPCODE_CMPN, 29 ELK_OPCODE_CSEL, /**< Gfx8+ */ 30 ELK_OPCODE_F32TO16, /**< Gfx7 only */ 31 ELK_OPCODE_F16TO32, /**< Gfx7 only */ 32 ELK_OPCODE_BFREV, /**< Gfx7+ */ 33 ELK_OPCODE_BFE, /**< Gfx7+ */ 34 ELK_OPCODE_BFI1, /**< Gfx7+ */ 35 ELK_OPCODE_BFI2, /**< Gfx7+ */ 36 ELK_OPCODE_JMPI, 37 ELK_OPCODE_BRD, /**< Gfx7+ */ 38 ELK_OPCODE_IF, 39 ELK_OPCODE_IFF, /**< Pre-Gfx6 */ 40 ELK_OPCODE_BRC, /**< Gfx7+ */ 41 ELK_OPCODE_ELSE, 42 ELK_OPCODE_ENDIF, 43 ELK_OPCODE_DO, /**< Pre-Gfx6 */ 44 ELK_OPCODE_CASE, /**< Gfx6 only */ 45 ELK_OPCODE_WHILE, 46 ELK_OPCODE_BREAK, 47 ELK_OPCODE_CONTINUE, 48 ELK_OPCODE_HALT, 49 ELK_OPCODE_CALLA, /**< Gfx7.5+ */ 50 ELK_OPCODE_MSAVE, /**< Pre-Gfx6 */ 51 ELK_OPCODE_CALL, /**< Gfx6+ */ 52 ELK_OPCODE_MREST, /**< Pre-Gfx6 */ 53 ELK_OPCODE_RET, /**< Gfx6+ */ 54 ELK_OPCODE_PUSH, /**< Pre-Gfx6 */ 55 ELK_OPCODE_FORK, /**< Gfx6 only */ 56 ELK_OPCODE_GOTO, /**< Gfx8+ */ 57 ELK_OPCODE_POP, /**< Pre-Gfx6 */ 58 ELK_OPCODE_WAIT, 59 ELK_OPCODE_SEND, 60 ELK_OPCODE_SENDC, 61 ELK_OPCODE_MATH, /**< Gfx6+ */ 62 ELK_OPCODE_ADD, 63 ELK_OPCODE_MUL, 64 ELK_OPCODE_AVG, 65 ELK_OPCODE_FRC, 66 ELK_OPCODE_RNDU, 67 ELK_OPCODE_RNDD, 68 ELK_OPCODE_RNDE, 69 ELK_OPCODE_RNDZ, 70 ELK_OPCODE_MAC, 71 ELK_OPCODE_MACH, 72 ELK_OPCODE_LZD, 73 ELK_OPCODE_FBH, /**< Gfx7+ */ 74 ELK_OPCODE_FBL, /**< Gfx7+ */ 75 ELK_OPCODE_CBIT, /**< Gfx7+ */ 76 ELK_OPCODE_ADDC, /**< Gfx7+ */ 77 ELK_OPCODE_SUBB, /**< Gfx7+ */ 78 ELK_OPCODE_SAD2, 79 ELK_OPCODE_SADA2, 80 ELK_OPCODE_DP4, 81 ELK_OPCODE_DPH, 82 ELK_OPCODE_DP3, 83 ELK_OPCODE_DP2, 84 ELK_OPCODE_LINE, 85 ELK_OPCODE_PLN, /**< G45+ */ 86 ELK_OPCODE_MAD, /**< Gfx6+ */ 87 ELK_OPCODE_LRP, /**< Gfx6+ */ 88 ELK_OPCODE_MADM, /**< Gfx8+ */ 89 ELK_OPCODE_NENOP, /**< G45 only */ 90 ELK_OPCODE_NOP, 91 92 NUM_ELK_OPCODES, 93 94 /* These are compiler backend opcodes that get translated into other 95 * instructions. 96 */ 97 ELK_FS_OPCODE_FB_WRITE = NUM_ELK_OPCODES, 98 99 /** 100 * Same as ELK_FS_OPCODE_FB_WRITE but expects its arguments separately as 101 * individual sources instead of as a single payload blob. The 102 * position/ordering of the arguments are defined by the enum 103 * fb_write_logical_srcs. 104 */ 105 ELK_FS_OPCODE_FB_WRITE_LOGICAL, 106 107 ELK_FS_OPCODE_REP_FB_WRITE, 108 109 ELK_SHADER_OPCODE_RCP, 110 ELK_SHADER_OPCODE_RSQ, 111 ELK_SHADER_OPCODE_SQRT, 112 ELK_SHADER_OPCODE_EXP2, 113 ELK_SHADER_OPCODE_LOG2, 114 ELK_SHADER_OPCODE_POW, 115 ELK_SHADER_OPCODE_INT_QUOTIENT, 116 ELK_SHADER_OPCODE_INT_REMAINDER, 117 ELK_SHADER_OPCODE_SIN, 118 ELK_SHADER_OPCODE_COS, 119 120 /** 121 * A generic "send" opcode. The first source is the descriptor and 122 * the second source is the message payload. 123 */ 124 ELK_SHADER_OPCODE_SEND, 125 126 /** 127 * An "undefined" write which does nothing but indicates to liveness that 128 * we don't care about any values in the register which predate this 129 * instruction. Used to prevent partial writes from causing issues with 130 * live ranges. 131 */ 132 ELK_SHADER_OPCODE_UNDEF, 133 134 /** 135 * Texture sampling opcodes. 136 * 137 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL 138 * opcode but instead of taking a single payload blob they expect their 139 * arguments separately as individual sources. The position/ordering of the 140 * arguments are defined by the enum tex_logical_srcs. 141 */ 142 ELK_SHADER_OPCODE_TEX, 143 ELK_SHADER_OPCODE_TEX_LOGICAL, 144 ELK_SHADER_OPCODE_TXD, 145 ELK_SHADER_OPCODE_TXD_LOGICAL, 146 ELK_SHADER_OPCODE_TXF, 147 ELK_SHADER_OPCODE_TXF_LOGICAL, 148 ELK_SHADER_OPCODE_TXF_LZ, 149 ELK_SHADER_OPCODE_TXL, 150 ELK_SHADER_OPCODE_TXL_LOGICAL, 151 ELK_SHADER_OPCODE_TXL_LZ, 152 ELK_SHADER_OPCODE_TXS, 153 ELK_SHADER_OPCODE_TXS_LOGICAL, 154 ELK_FS_OPCODE_TXB, 155 ELK_FS_OPCODE_TXB_LOGICAL, 156 ELK_SHADER_OPCODE_TXF_CMS, 157 ELK_SHADER_OPCODE_TXF_CMS_LOGICAL, 158 ELK_SHADER_OPCODE_TXF_CMS_W, 159 ELK_SHADER_OPCODE_TXF_CMS_W_LOGICAL, 160 ELK_SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL, 161 ELK_SHADER_OPCODE_TXF_UMS, 162 ELK_SHADER_OPCODE_TXF_UMS_LOGICAL, 163 ELK_SHADER_OPCODE_TXF_MCS, 164 ELK_SHADER_OPCODE_TXF_MCS_LOGICAL, 165 ELK_SHADER_OPCODE_LOD, 166 ELK_SHADER_OPCODE_LOD_LOGICAL, 167 ELK_SHADER_OPCODE_TG4, 168 ELK_SHADER_OPCODE_TG4_LOGICAL, 169 ELK_SHADER_OPCODE_TG4_OFFSET, 170 ELK_SHADER_OPCODE_TG4_OFFSET_LOGICAL, 171 ELK_SHADER_OPCODE_SAMPLEINFO, 172 ELK_SHADER_OPCODE_SAMPLEINFO_LOGICAL, 173 174 ELK_SHADER_OPCODE_IMAGE_SIZE_LOGICAL, 175 176 /** 177 * Combines multiple sources of size 1 into a larger virtual GRF. 178 * For example, parameters for a send-from-GRF message. Or, updating 179 * channels of a size 4 VGRF used to store vec4s such as texturing results. 180 * 181 * This will be lowered into MOVs from each source to consecutive offsets 182 * of the destination VGRF. 183 * 184 * src[0] may be BAD_FILE. If so, the lowering pass skips emitting the MOV, 185 * but still reserves the first channel of the destination VGRF. This can be 186 * used to reserve space for, say, a message header set up by the generators. 187 */ 188 ELK_SHADER_OPCODE_LOAD_PAYLOAD, 189 190 /** 191 * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this 192 * acts intra-channel, obtaining the final value for each channel by 193 * combining the sources values for the same channel, the first source 194 * occupying the lowest bits and the last source occupying the highest 195 * bits. 196 */ 197 ELK_FS_OPCODE_PACK, 198 199 /** 200 * Typed and untyped surface access opcodes. 201 * 202 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL 203 * opcode but instead of taking a single payload blob they expect their 204 * arguments separately as individual sources: 205 * 206 * Source 0: [required] Surface coordinates. 207 * Source 1: [optional] Operation source. 208 * Source 2: [required] Surface index. 209 * Source 3: [required] Number of coordinate components (as UD immediate). 210 * Source 4: [required] Opcode-specific control immediate, same as source 2 211 * of the matching non-LOGICAL opcode. 212 */ 213 ELK_VEC4_OPCODE_UNTYPED_ATOMIC, 214 ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL, 215 ELK_VEC4_OPCODE_UNTYPED_SURFACE_READ, 216 ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL, 217 ELK_VEC4_OPCODE_UNTYPED_SURFACE_WRITE, 218 ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL, 219 220 ELK_SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL, 221 ELK_SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL, 222 223 /** 224 * Untyped A64 surface access opcodes. 225 * 226 * Source 0: 64-bit address 227 * Source 1: Operational source 228 * Source 2: [required] Opcode-specific control immediate, same as source 2 229 * of the matching non-LOGICAL opcode. 230 */ 231 ELK_SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL, 232 ELK_SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL, 233 ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL, 234 ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL, 235 ELK_SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL, 236 ELK_SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL, 237 ELK_SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL, 238 ELK_SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL, 239 240 ELK_SHADER_OPCODE_TYPED_ATOMIC_LOGICAL, 241 ELK_SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL, 242 ELK_SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL, 243 244 ELK_SHADER_OPCODE_RND_MODE, 245 ELK_SHADER_OPCODE_FLOAT_CONTROL_MODE, 246 247 /** 248 * Byte scattered write/read opcodes. 249 * 250 * LOGICAL opcodes are eventually translated to the matching non-LOGICAL 251 * opcode, but instead of taking a single payload blog they expect their 252 * arguments separately as individual sources, like untyped write/read. 253 */ 254 ELK_SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL, 255 ELK_SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL, 256 ELK_SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL, 257 ELK_SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL, 258 259 /** 260 * Memory fence messages. 261 * 262 * Source 0: Must be register g0, used as header. 263 * Source 1: Immediate bool to indicate whether control is returned to the 264 * thread only after the fence has been honored. 265 * Source 2: Immediate byte indicating which memory to fence. Zero means 266 * global memory; GFX7_BTI_SLM means SLM (for Gfx11+ only). 267 * 268 * Vec4 backend only uses Source 0. 269 */ 270 ELK_SHADER_OPCODE_MEMORY_FENCE, 271 272 /** 273 * Scheduling-only fence. 274 * 275 * Sources can be used to force a stall until the registers in those are 276 * available. This might generate MOVs or SYNC_NOPs (Gfx12+). 277 */ 278 ELK_FS_OPCODE_SCHEDULING_FENCE, 279 280 ELK_SHADER_OPCODE_GFX4_SCRATCH_READ, 281 ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE, 282 ELK_SHADER_OPCODE_GFX7_SCRATCH_READ, 283 284 ELK_SHADER_OPCODE_SCRATCH_HEADER, 285 286 /** 287 * Gfx8+ SIMD8 URB messages. 288 */ 289 ELK_SHADER_OPCODE_URB_READ_LOGICAL, 290 ELK_SHADER_OPCODE_URB_WRITE_LOGICAL, 291 292 /** 293 * Return the index of the first enabled live channel and assign it to 294 * to the first component of the destination. Frequently used as input 295 * for the BROADCAST pseudo-opcode. 296 */ 297 ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL, 298 299 /** 300 * Return the index of the last enabled live channel and assign it to 301 * the first component of the destination. 302 */ 303 ELK_SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL, 304 305 /** 306 * Return the current execution mask in the specified flag subregister. 307 * Can be CSE'ed more easily than a plain MOV from the ce0 ARF register. 308 */ 309 ELK_FS_OPCODE_LOAD_LIVE_CHANNELS, 310 311 /** 312 * Pick the channel from its first source register given by the index 313 * specified as second source. Useful for variable indexing of surfaces. 314 * 315 * Note that because the result of this instruction is by definition 316 * uniform and it can always be splatted to multiple channels using a 317 * scalar regioning mode, only the first channel of the destination region 318 * is guaranteed to be updated, which implies that BROADCAST instructions 319 * should usually be marked force_writemask_all. 320 */ 321 ELK_SHADER_OPCODE_BROADCAST, 322 323 /* Pick the channel from its first source register given by the index 324 * specified as second source. 325 * 326 * This is similar to the BROADCAST instruction except that it takes a 327 * dynamic index and potentially puts a different value in each output 328 * channel. 329 */ 330 ELK_SHADER_OPCODE_SHUFFLE, 331 332 /* Select between src0 and src1 based on channel enables. 333 * 334 * This instruction copies src0 into the enabled channels of the 335 * destination and copies src1 into the disabled channels. 336 */ 337 ELK_SHADER_OPCODE_SEL_EXEC, 338 339 /* This turns into an align16 mov from src0 to dst with a swizzle 340 * provided as an immediate in src1. 341 */ 342 ELK_SHADER_OPCODE_QUAD_SWIZZLE, 343 344 /* Take every Nth element in src0 and broadcast it to the group of N 345 * channels in which it lives in the destination. The offset within the 346 * cluster is given by src1 and the cluster size is given by src2. 347 */ 348 ELK_SHADER_OPCODE_CLUSTER_BROADCAST, 349 350 ELK_SHADER_OPCODE_GET_BUFFER_SIZE, 351 352 ELK_SHADER_OPCODE_INTERLOCK, 353 354 /** Target for a HALT 355 * 356 * All HALT instructions in a shader must target the same jump point and 357 * that point is denoted by a HALT_TARGET instruction. 358 */ 359 ELK_SHADER_OPCODE_HALT_TARGET, 360 361 ELK_VEC4_OPCODE_MOV_BYTES, 362 ELK_VEC4_OPCODE_PACK_BYTES, 363 ELK_VEC4_OPCODE_UNPACK_UNIFORM, 364 ELK_VEC4_OPCODE_DOUBLE_TO_F32, 365 ELK_VEC4_OPCODE_DOUBLE_TO_D32, 366 ELK_VEC4_OPCODE_DOUBLE_TO_U32, 367 ELK_VEC4_OPCODE_TO_DOUBLE, 368 ELK_VEC4_OPCODE_PICK_LOW_32BIT, 369 ELK_VEC4_OPCODE_PICK_HIGH_32BIT, 370 ELK_VEC4_OPCODE_SET_LOW_32BIT, 371 ELK_VEC4_OPCODE_SET_HIGH_32BIT, 372 ELK_VEC4_OPCODE_MOV_FOR_SCRATCH, 373 ELK_VEC4_OPCODE_ZERO_OOB_PUSH_REGS, 374 375 ELK_FS_OPCODE_DDX_COARSE, 376 ELK_FS_OPCODE_DDX_FINE, 377 /** 378 * Compute dFdy(), dFdyCoarse(), or dFdyFine(). 379 */ 380 ELK_FS_OPCODE_DDY_COARSE, 381 ELK_FS_OPCODE_DDY_FINE, 382 ELK_FS_OPCODE_LINTERP, 383 ELK_FS_OPCODE_PIXEL_X, 384 ELK_FS_OPCODE_PIXEL_Y, 385 ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, 386 ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4, 387 ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL, 388 ELK_FS_OPCODE_SET_SAMPLE_ID, 389 ELK_FS_OPCODE_PACK_HALF_2x16_SPLIT, 390 ELK_FS_OPCODE_INTERPOLATE_AT_SAMPLE, 391 ELK_FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET, 392 ELK_FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET, 393 394 ELK_VEC4_VS_OPCODE_URB_WRITE, 395 ELK_VS_OPCODE_PULL_CONSTANT_LOAD, 396 ELK_VS_OPCODE_PULL_CONSTANT_LOAD_GFX7, 397 398 ELK_VS_OPCODE_UNPACK_FLAGS_SIMD4X2, 399 400 /** 401 * Write geometry shader output data to the URB. 402 * 403 * Unlike ELK_VEC4_VS_OPCODE_URB_WRITE, this opcode doesn't do an implied move from 404 * R0 to the first MRF. This allows the geometry shader to override the 405 * "Slot {0,1} Offset" fields in the message header. 406 */ 407 ELK_VEC4_GS_OPCODE_URB_WRITE, 408 409 /** 410 * Write geometry shader output data to the URB and request a new URB 411 * handle (gfx6). 412 * 413 * This opcode doesn't do an implied move from R0 to the first MRF. 414 */ 415 ELK_VEC4_GS_OPCODE_URB_WRITE_ALLOCATE, 416 417 /** 418 * Terminate the geometry shader thread by doing an empty URB write. 419 * 420 * This opcode doesn't do an implied move from R0 to the first MRF. This 421 * allows the geometry shader to override the "GS Number of Output Vertices 422 * for Slot {0,1}" fields in the message header. 423 */ 424 ELK_GS_OPCODE_THREAD_END, 425 426 /** 427 * Set the "Slot {0,1} Offset" fields of a URB_WRITE message header. 428 * 429 * - dst is the MRF containing the message header. 430 * 431 * - src0.x indicates which portion of the URB should be written to (e.g. a 432 * vertex number) 433 * 434 * - src1 is an immediate multiplier which will be applied to src0 435 * (e.g. the size of a single vertex in the URB). 436 * 437 * Note: the hardware will apply this offset *in addition to* the offset in 438 * vec4_instruction::offset. 439 */ 440 ELK_GS_OPCODE_SET_WRITE_OFFSET, 441 442 /** 443 * Set the "GS Number of Output Vertices for Slot {0,1}" fields of a 444 * URB_WRITE message header. 445 * 446 * - dst is the MRF containing the message header. 447 * 448 * - src0.x is the vertex count. The upper 16 bits will be ignored. 449 */ 450 ELK_GS_OPCODE_SET_VERTEX_COUNT, 451 452 /** 453 * Set DWORD 2 of dst to the value in src. 454 */ 455 ELK_GS_OPCODE_SET_DWORD_2, 456 457 /** 458 * Prepare the dst register for storage in the "Channel Mask" fields of a 459 * URB_WRITE message header. 460 * 461 * DWORD 4 of dst is shifted left by 4 bits, so that later, 462 * ELK_GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the 463 * final channel mask. 464 * 465 * Note: since ELK_GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to 466 * form the final channel mask, DWORDs 0 and 4 of the dst register must not 467 * have any extraneous bits set prior to execution of this opcode (that is, 468 * they should be in the range 0x0 to 0xf). 469 */ 470 ELK_GS_OPCODE_PREPARE_CHANNEL_MASKS, 471 472 /** 473 * Set the "Channel Mask" fields of a URB_WRITE message header. 474 * 475 * - dst is the MRF containing the message header. 476 * 477 * - src.x is the channel mask, as prepared by 478 * ELK_GS_OPCODE_PREPARE_CHANNEL_MASKS. DWORDs 0 and 4 are OR'ed together to 479 * form the final channel mask. 480 */ 481 ELK_GS_OPCODE_SET_CHANNEL_MASKS, 482 483 /** 484 * Get the "Instance ID" fields from the payload. 485 * 486 * - dst is the GRF for gl_InvocationID. 487 */ 488 ELK_GS_OPCODE_GET_INSTANCE_ID, 489 490 /** 491 * Send a FF_SYNC message to allocate initial URB handles (gfx6). 492 * 493 * - dst will be used as the writeback register for the FF_SYNC operation. 494 * 495 * - src0 is the number of primitives written. 496 * 497 * - src1 is the value to hold in M0.0: number of SO vertices to write 498 * and number of SO primitives needed. Its value will be overwritten 499 * with the SVBI values if transform feedback is enabled. 500 * 501 * Note: This opcode uses an implicit MRF register for the ff_sync message 502 * header, so the caller is expected to set inst->base_mrf and initialize 503 * that MRF register to r0. This opcode will also write to this MRF register 504 * to include the allocated URB handle so it can then be reused directly as 505 * the header in the URB write operation we are allocating the handle for. 506 */ 507 ELK_GS_OPCODE_FF_SYNC, 508 509 /** 510 * Move r0.1 (which holds PrimitiveID information in gfx6) to a separate 511 * register. 512 * 513 * - dst is the GRF where PrimitiveID information will be moved. 514 */ 515 ELK_GS_OPCODE_SET_PRIMITIVE_ID, 516 517 /** 518 * Write transform feedback data to the SVB by sending a SVB WRITE message. 519 * Used in gfx6. 520 * 521 * - dst is the MRF register containing the message header. 522 * 523 * - src0 is the register where the vertex data is going to be copied from. 524 * 525 * - src1 is the destination register when write commit occurs. 526 */ 527 ELK_GS_OPCODE_SVB_WRITE, 528 529 /** 530 * Set destination index in the SVB write message payload (M0.5). Used 531 * in gfx6 for transform feedback. 532 * 533 * - dst is the header to save the destination indices for SVB WRITE. 534 * - src is the register that holds the destination indices value. 535 */ 536 ELK_GS_OPCODE_SVB_SET_DST_INDEX, 537 538 /** 539 * Prepare Mx.0 subregister for being used in the FF_SYNC message header. 540 * Used in gfx6 for transform feedback. 541 * 542 * - dst will hold the register with the final Mx.0 value. 543 * 544 * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite) 545 * 546 * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded) 547 * 548 * - src2 is the value to hold in M0: number of SO vertices to write 549 * and number of SO primitives needed. 550 */ 551 ELK_GS_OPCODE_FF_SYNC_SET_PRIMITIVES, 552 553 /** 554 * Terminate the compute shader. 555 */ 556 ELK_CS_OPCODE_CS_TERMINATE, 557 558 /** 559 * GLSL barrier() 560 */ 561 ELK_SHADER_OPCODE_BARRIER, 562 563 /** 564 * Calculate the high 32-bits of a 32x32 multiply. 565 */ 566 ELK_SHADER_OPCODE_MULH, 567 568 /** Signed subtraction with saturation. */ 569 ELK_SHADER_OPCODE_ISUB_SAT, 570 571 /** Unsigned subtraction with saturation. */ 572 ELK_SHADER_OPCODE_USUB_SAT, 573 574 /** 575 * A MOV that uses VxH indirect addressing. 576 * 577 * Source 0: A register to start from (HW_REG). 578 * Source 1: An indirect offset (in bytes, UD GRF). 579 * Source 2: The length of the region that could be accessed (in bytes, 580 * UD immediate). 581 */ 582 ELK_SHADER_OPCODE_MOV_INDIRECT, 583 584 /** Fills out a relocatable immediate */ 585 ELK_SHADER_OPCODE_MOV_RELOC_IMM, 586 587 ELK_VEC4_OPCODE_URB_READ, 588 ELK_TCS_OPCODE_GET_INSTANCE_ID, 589 ELK_VEC4_TCS_OPCODE_URB_WRITE, 590 ELK_VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS, 591 ELK_VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS, 592 ELK_TCS_OPCODE_GET_PRIMITIVE_ID, 593 ELK_TCS_OPCODE_CREATE_BARRIER_HEADER, 594 ELK_TCS_OPCODE_SRC0_010_IS_ZERO, 595 ELK_TCS_OPCODE_RELEASE_INPUT, 596 ELK_TCS_OPCODE_THREAD_END, 597 598 ELK_TES_OPCODE_GET_PRIMITIVE_ID, 599 ELK_TES_OPCODE_CREATE_INPUT_READ_HEADER, 600 ELK_TES_OPCODE_ADD_INDIRECT_URB_OFFSET, 601 602 ELK_SHADER_OPCODE_READ_SR_REG, 603 }; 604 605 606 #ifdef __cplusplus 607 } 608 #endif 609