1 /* 2 * Copyright (C) 2021-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MNPMUSRAMMSGBLOCK_LPDDR4_H 8 #define MNPMUSRAMMSGBLOCK_LPDDR4_H 9 10 /* LPDDR4_1D training firmware message block structure 11 * 12 * Please refer to the Training Firmware App Note for futher information about 13 * the usage for Message Block. 14 */ 15 struct pmu_smb_ddr_1d { 16 uint8_t reserved00; /* 17 * Byte offset 0x00, CSR Addr 0x54000, Direction=In 18 * reserved00[0:4] RFU, must be zero 19 * 20 * reserved00[5] = Quick Rd2D during 1D Training 21 * 0x1 = Read Deskew will begin by enabling and quickly 22 * training the phy's per-lane reference voltages. 23 * Training the vrefDACs CSRs will increase the maximum 1D 24 * training time by around half a millisecond, but will 25 * improve 1D training accuracy on systems with 26 * significant voltage-offsets between lane read eyes. 27 * 0x0 = Read Deskew will assume the messageblock's 28 * phyVref setting is optimal for all lanes. 29 * 30 * reserved00[6] = Enable High Effort WrDQ1D 31 * 0x1 = WrDQ1D will conditionally retry training at 32 * several extra RxClkDly Timings. This will increase the 33 * maximum 1D training time by up to 4 extra iterations of 34 * WrDQ1D. This is only required in systems that suffer 35 * from very large, asymmetric eye-collapse when receiving 36 * PRBS patterns. 37 * 0x0 = WrDQ1D assume rxClkDly values found by SI 38 * Friendly RdDqs1D will work for receiving PRBS patterns 39 * 40 * reserved00[7] = Optimize for the special hard macros in 41 * TSMC28. 42 * 0x1 = set if the phy being trained was manufactured in 43 * any TSMC28 process node. 44 * 0x0 = otherwise, when not training a TSMC28 phy, leave 45 * this field as 0. 46 */ 47 uint8_t msgmisc; /* 48 * Byte offset 0x01, CSR Addr 0x54000, Direction=In 49 * Contains various global options for training. 50 * 51 * Bit fields: 52 * 53 * msgmisc[0] MTESTEnable 54 * 0x1 = Pulse primary digital test output bump at the end 55 * of each major training stage. This enables observation 56 * of training stage completion by observing the digital 57 * test output. 58 * 0x0 = Do not pulse primary digital test output bump 59 * 60 * msgmisc[1] SimulationOnlyReset 61 * 0x1 = Verilog only simulation option to shorten 62 * duration of DRAM reset pulse length to 1ns. 63 * Must never be set to 1 in silicon. 64 * 0x0 = Use reset pulse length specified by JEDEC 65 * standard. 66 * 67 * msgmisc[2] SimulationOnlyTraining 68 * 0x1 = Verilog only simulation option to shorten the 69 * duration of the training steps by performing fewer 70 * iterations. 71 * Must never be set to 1 in silicon. 72 * 0x0 = Use standard training duration. 73 * 74 * msgmisc[3] Disable Boot Clock 75 * 0x1 = Disable boot frequency clock when initializing 76 * DRAM. (not recommended) 77 * 0x0 = Use Boot Frequency Clock 78 * 79 * msgmisc[4] Suppress streaming messages, including 80 * assertions, regardless of hdtctrl setting. 81 * Stage Completion messages, as well as training completion 82 * and error messages are still sent depending on hdtctrl 83 * setting. 84 * 85 * msgmisc[5] PerByteMaxRdLat 86 * 0x1 = Each DBYTE will return dfi_rddata_valid at the 87 * lowest possible latency. This may result in unaligned 88 * data between bytes to be returned to the DFI. 89 * 0x0 = Every DBYTE will return dfi_rddata_valid 90 * simultaneously. This will ensure that data bytes will 91 * return aligned accesses to the DFI. 92 * 93 * msgmisc[7-6] RFU, must be zero 94 * 95 * Notes: 96 * 97 * - SimulationOnlyReset and SimulationOnlyTraining can be 98 * used to speed up simulation run times, and must never 99 * be used in real silicon. Some VIPs may have checks on 100 * DRAM reset parameters that may need to be disabled when 101 * using SimulationOnlyReset. 102 */ 103 uint16_t pmurevision; /* 104 * Byte offset 0x02, CSR Addr 0x54001, Direction=Out 105 * PMU firmware revision ID 106 * After training is run, this address will contain the 107 * revision ID of the firmware 108 */ 109 uint8_t pstate; /* 110 * Byte offset 0x04, CSR Addr 0x54002, Direction=In 111 * Must be set to the target pstate to be trained 112 * 0x0 = pstate 0 113 * 0x1 = pstate 1 114 * 0x2 = pstate 2 115 * 0x3 = pstate 3 116 * All other encodings are reserved 117 */ 118 uint8_t pllbypassen; /* 119 * Byte offset 0x05, CSR Addr 0x54002, Direction=In 120 * Set according to whether target pstate uses PHY PLL 121 * bypass 122 * 0x0 = PHY PLL is enabled for target pstate 123 * 0x1 = PHY PLL is bypassed for target pstate 124 */ 125 uint16_t dramfreq; /* 126 * Byte offset 0x06, CSR Addr 0x54003, Direction=In 127 * DDR data rate for the target pstate in units of MT/s. 128 * For example enter 0x0640 for DDR1600. 129 */ 130 uint8_t dfifreqratio; /* 131 * Byte offset 0x08, CSR Addr 0x54004, Direction=In 132 * Frequency ratio betwen DfiCtlClk and SDRAM memclk. 133 * 0x1 = 1:1 134 * 0x2 = 1:2 135 * 0x4 = 1:4 136 */ 137 uint8_t bpznresval; /* 138 * Byte offset 0x09, CSR Addr 0x54004, Direction=In 139 * Overwrite the value of precision resistor connected to 140 * Phy BP_ZN 141 * 0x00 = Do not program. Use current CSR value. 142 * 0xf0 = 240 Ohm 143 * 0x78 = 120 Ohm 144 * 0x28 = 40 Ohm 145 * All other values are reserved. 146 * It is recommended to set this to 0x00. 147 */ 148 uint8_t phyodtimpedance; /* 149 * Byte offset 0x0a, CSR Addr 0x54005, Direction=In 150 * Must be programmed to the termination impedance in ohms 151 * used by PHY during reads. 152 * 153 * 0x0 = Firmware skips programming (must be manually 154 * programmed by user prior to training start) 155 * 156 * See PHY databook for legal termination impedance values. 157 * 158 * For digital simulation, any legal value can be used. For 159 * silicon, the users must determine the correct value 160 * through SI simulation or other methods. 161 */ 162 uint8_t phydrvimpedance; /* 163 * Byte offset 0x0b, CSR Addr 0x54005, Direction=In 164 * Must be programmed to the driver impedance in ohms used 165 * by PHY during writes for all DBYTE drivers 166 * (DQ/DM/DBI/DQS). 167 * 168 * 0x0 = Firmware skips programming (must be manually 169 * programmed by user prior to training start) 170 * 171 * See PHY databook for legal R_on driver impedance values. 172 * 173 * For digital simulation, any value can be used that is not 174 * Hi-Z. For silicon, the users must determine the correct 175 * value through SI simulation or other methods. 176 */ 177 uint8_t phyvref; /* 178 * Byte offset 0x0c, CSR Addr 0x54006, Direction=In 179 * Must be programmed with the Vref level to be used by the 180 * PHY during reads 181 * 182 * The units of this field are a percentage of VDDQ 183 * according to the following equation: 184 * 185 * Receiver Vref = VDDQ*phyvref[6:0]/128 186 * 187 * For example to set Vref at 0.25*VDDQ, set this field to 188 * 0x20. 189 * 190 * For digital simulation, any legal value can be used. For 191 * silicon, the users must calculate the analytical Vref by 192 * using the impedances, terminations, and series resistance 193 * present in the system. 194 */ 195 uint8_t lp4misc; /* 196 * Byte offset 0x0d, CSR Addr 0x54006, Direction=In 197 * Lp4 specific options for training. 198 * 199 * Bit fields: 200 * 201 * lp4misc[0] Enable dfi_reset_n 202 * 203 * 0x0 = (Recommended) PHY internal registers control 204 * memreset during training, and also after training. 205 * dfi_reset_n cannot control the PHY BP_MEMRESET_L pin. 206 * 207 * 0x1 = Enables dfi_reset_n to control memreset after 208 * training. PHY Internal registers control memreset 209 * during training only. To ensure that no glitches occur 210 * on BP_MEMRESET at the end of training, The MC must 211 * drive dfi_reset_n=1'b1 _prior to starting training_ 212 * 213 * lp4misc[7-1] RFU, must be zero 214 */ 215 uint8_t reserved0e; /* 216 * Byte offset 0x0e, CSR Addr 0x54007, Direction=In 217 * Bit Field for enabling optional 2D training features 218 * that impact both Rx2D and Tx2D. 219 * 220 * reserved0E[0:3]: bitTimeControl 221 * input for the amount of data bits 2D writes/reads per DQ 222 * before deciding if any specific voltage and delay setting 223 * passes or fails. Every time this input increases by 1, 224 * the number of 2D data comparisons is doubled. The 2D run 225 * time will increase proportionally to the number of bit 226 * times requested per point. 227 * 0 = 288 bits per point (legacy behavior) 228 * 1 = 576 bits per point 229 * 2 = 1.125 kilobits per point 230 * . . . 231 * 15 = 9 megabits per point 232 * 233 * reserved0E[4]: Exhaustive2D 234 * 0 = 2D optimization assumes the optimal trained point 235 * is near the 1D trained point (legacy behavior) 236 * 1 = 2D optimization searches the entire passing region 237 * at the cost of run time. Recommended for optimal 238 * results any time the optimal trained point is expected 239 * to be near the edges of the eyes instead of near the 1D 240 * trained point. 241 * 242 * reserved0E[5]: Detect Vref Eye Truncation, ignored if 243 * eyeWeight2DControl == 0. 244 * 0 = 2D optimizes for the passing region it can measure. 245 * 1 = For every eye, 2D checks If the legal voltage range 246 * truncated the eye. If the true voltage margin cannot be 247 * measured, 2D will optimize heavily for delay margin 248 * instead of using incomplete voltage margin data. Eyes 249 * that are not truncated will still be optimized using 250 * user programmed weights. 251 * 252 * reserved0E[6]: eyeWeight2DControl 253 * 0 = Use 8 bit weights for Delay_Weight2D and 254 * Voltage_Weight2D and disable TrunkV behavior. 255 * 1 = Use 4 bit weights for Delay_weight2D and 256 * Voltage_Weight2D and enable TrunkV behavior. 257 * 258 * reserved0E[7]: RFU, must be 0 259 */ 260 uint8_t cstestfail; /* 261 * Byte offset 0x0f, CSR Addr 0x54007, Direction=Out 262 * This field will be set if training fails on any rank. 263 * 0x0 = No failures 264 * non-zero = one or more ranks failed training 265 */ 266 uint16_t sequencectrl; /* 267 * Byte offset 0x10, CSR Addr 0x54008, Direction=In 268 * Controls the training steps to be run. Each bit 269 * corresponds to a training step. 270 * 271 * If the bit is set to 1, the training step will run. 272 * If the bit is set to 0, the training step will be 273 * skipped. 274 * 275 * Training step to bit mapping: 276 * sequencectrl[0] = Run DevInit - Device/phy 277 * initialization. Should always be set. 278 * sequencectrl[1] = Run WrLvl - Write leveling 279 * sequencectrl[2] = Run RxEn - Read gate training 280 * sequencectrl[3] = Run RdDQS1D - 1d read dqs training 281 * sequencectrl[4] = Run WrDQ1D - 1d write dq training 282 * sequencectrl[5] = RFU, must be zero 283 * sequencectrl[6] = RFU, must be zero 284 * sequencectrl[7] = RFU, must be zero 285 * sequencectrl[8] = Run RdDeskew - Per lane read dq deskew 286 * training 287 * sequencectrl[9] = Run MxRdLat - Max read latency training 288 * sequencectrl[11-10] = RFU, must be zero 289 * sequencectrl[12] = Run LPCA - CA Training 290 * sequencectrl[15-13] = RFU, must be zero 291 */ 292 uint8_t hdtctrl; /* 293 * Byte offset 0x12, CSR Addr 0x54009, Direction=In 294 * To control the total number of debug messages, a 295 * verbosity subfield (hdtctrl, Hardware Debug Trace 296 * Control) exists in the message block. Every message has a 297 * verbosity level associated with it, and as the hdtctrl 298 * value is increased, less important s messages stop being 299 * sent through the mailboxes. The meanings of several major 300 * hdtctrl thresholds are explained below: 301 * 302 * 0x04 = Maximal debug messages (e.g., Eye contours) 303 * 0x05 = Detailed debug messages (e.g. Eye delays) 304 * 0x0A = Coarse debug messages (e.g. rank information) 305 * 0xC8 = Stage completion 306 * 0xC9 = Assertion messages 307 * 0xFF = Firmware completion messages only 308 */ 309 uint8_t reserved13; /* 310 * Byte offset 0x13, CSR Addr 0x54009, Direction=In 311 * 312 * 0 = Default operation, unchanged. 313 * Others = RD DQ calibration Training steps are completed 314 * with user specified pattern. 315 */ 316 uint8_t reserved14; /* 317 * Byte offset 0x14, CSR Addr 0x5400a, Direction=In 318 * Configure rd2D search iteration from a starting seed 319 * point: 320 * 321 * reserved14[5:0]: If reserved14[6] is 0, Number of search 322 * iterations (if 0, then default is 20); otherwise if this 323 * value non zero, this value is used as a delta to filter 324 * out points during the averaging: when averaging over a 325 * dimension (delay or voltage), the points having a margin 326 * smaller than the max of the eye in this dimension by at 327 * least this delta value are filtered out. 328 * 329 * reserved14[6]: If set, instead of search, extract center 330 * using an averaging function over the eye surface area, 331 * where some points can be filtered out using 332 * reserved14[5:0] 333 * 334 * reserved14[7]: if set, start search with large step size, 335 * decreasing at each 4 iterations, down to 1 (do not care 336 * if reserved14[6] is set) 337 */ 338 uint8_t reserved15; /* 339 * Byte offset 0x15, CSR Addr 0x5400a, Direction=In 340 * Configure wr2D search iteration from a starting seed 341 * point: 342 * 343 * reserved15[5:0]: If reserved15[6] is 0, Number of search 344 * iterations (if 0, then default is 20); otherwise if this 345 * value non zero, this value is used as a delta to filter 346 * out points during the averaging: when averaging over a 347 * dimension (delay or voltage), the points having a margin 348 * smaller than the max of the eye in this dimension by at 349 * least this delta value are filtered out. 350 * 351 * reserved15[6]: If set, instead of search, extract center 352 * using an averaging function over the eye surface area, 353 * where some points can be filtered out using 354 * reserved15[5:0] 355 * 356 * reserved15[7]: if set, start search with large step size, 357 * decreasing at each 4 iterations, down to 1 (do not care 358 * if reserved15[6] is set) 359 */ 360 uint8_t dfimrlmargin; /* 361 * Byte offset 0x16, CSR Addr 0x5400b, Direction=In 362 * Margin added to smallest passing trained DFI Max Read 363 * Latency value, in units of DFI clocks. Recommended to be 364 * >= 1. 365 * 366 * This margin must include the maximum positive drift 367 * expected in tDQSCK over the target temperature and 368 * voltage range of the users system. 369 */ 370 uint8_t reserved17; /* 371 * Byte offset 0x17, CSR Addr 0x5400b, Direction=In 372 * Configure DB from which extra info is dump during 2D 373 * training when maximal debug is set: 374 * 375 * reserved17[3:0]: first DB 376 * 377 * reserved17[7:4]: number of DB, including first DB (if 0, 378 * no extra debug per DB is dump) 379 */ 380 uint8_t usebroadcastmr; /* 381 * Byte offset 0x18, CSR Addr 0x5400c, Direction=In 382 * Training firmware can optionally set per rank mode 383 * register values for DRAM partial array self-refresh 384 * features if desired. 385 * 386 * 0x0 = Use mr<1:4, 11:14, 16:17, 22, 24>_a0 for rank 0 387 * channel A 388 * Use mr<1:4, 11:14, 16:17, 22, 24>_b0 for rank 0 389 * channel B 390 * Use mr<1:4, 11:14, 16:17, 22, 24>_a1 for rank 1 391 * channel A 392 * Use mr<1:4, 11:14, 16:17, 22, 24>_b1 for rank 1 393 * channel B 394 * 395 * 0x1 = Use mr<1:4, 11:14, 16:17, 22, 24>_a0 setting for 396 * all channels/ranks 397 * 398 * It is recommended in most LPDDR4 system configurations 399 * to set this to 1. 400 * It is recommended in LPDDR4x system configurations to 401 * set this to 0. 402 */ 403 uint8_t lp4quickboot; /* 404 * Byte offset 0x19, CSR Addr 0x5400c, Direction=In 405 * Enable Quickboot. It must be set to 0x0 since Quickboot 406 * is only supported in dedicated Quickboot firmware. 407 */ 408 uint8_t reserved1a; /* 409 * Byte offset 0x1a, CSR Addr 0x5400d, Direction=In 410 * Input for constraining the range of vref(DQ) values 411 * training will collect data for, usually reducing training 412 * time. However, too large of a voltage range may cause 413 * longer 2D training times while too small of a voltage 414 * range may truncate passing regions. When in doubt, leave 415 * this field set to 0. 416 * Used by 2D stages: Rd2D, Wr2D 417 * 418 * reserved1A[0-3]: Rd2D Voltage Range 419 * 0 = Training will search all phy vref(DQ) settings 420 * 1 = limit to +/-2 %VDDQ from phyVref 421 * 2 = limit to +/-4 %VDDQ from phyVref 422 * . . . 423 * 15 = limit to +/-30% VDDQ from phyVref 424 * 425 * reserved1A[4-7]: Wr2D Voltage Range 426 * 0 = Training will search all dram vref(DQ) settings 427 * 1 = limit to +/-2 %VDDQ from mr14 428 * 2 = limit to +/-4 %VDDQ from mr14 429 * . . . 430 * 15 = limit to +/-30% VDDQ from mr14 431 */ 432 uint8_t catrainopt; /* 433 * Byte offset 0x1b, CSR Addr 0x5400d, Direction=In 434 * CA training option bit field 435 * [0] CA VREF Training 436 * 1 = Enable CA VREF Training 437 * 0 = Disable CA VREF Training 438 * WARNING: catrainopt[0] must be set to the same value in 439 * 1D and 2D training. 440 * 441 * [1] Train terminated Rank only 442 * 1 = Only train terminated rank in CA training 443 * 0 = Train all ranks in CA training 444 * 445 * [2-7] RFU must be zero 446 */ 447 uint8_t x8mode; /* 448 * Byte offset 0x1c, CSR Addr 0x5400e, Direction=In 449 * X8 mode configuration: 450 * 0x0 = x16 configuration for all devices 451 * 0xF = x8 configuration for all devices 452 * All other values are RFU 453 */ 454 uint8_t reserved1d; /* Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A */ 455 uint8_t reserved1e; /* Byte offset 0x1e, CSR Addr 0x5400f, Direction=N/A */ 456 uint8_t share2dvrefresult; /* 457 * Byte offset 0x1f, CSR Addr 0x5400f, Direction=In 458 * Bitmap that designates the phy's vref source for every 459 * pstate 460 * If share2dvrefresult[x] = 0, then after 2D training, 461 * pstate x will continue using the phyVref provided in 462 * pstate x's 1D messageblock. 463 * If share2dvrefresult[x] = 1, then after 2D training, 464 * pstate x will use the per-lane VrefDAC0/1 CSRs trained by 465 * 2d training. 466 */ 467 uint8_t reserved20; /* Byte offset 0x20, CSR Addr 0x54010, Direction=N/A */ 468 uint8_t reserved21; /* Byte offset 0x21, CSR Addr 0x54010, Direction=N/A */ 469 uint16_t phyconfigoverride; /* 470 * Byte offset 0x22, CSR Addr 0x54011, Direction=In 471 * Override PhyConfig csr. 472 * 0x0: Use hardware csr value for PhyConfing 473 * (recommended) 474 * Other values: Use value for PhyConfig instead of 475 * Hardware value. 476 * 477 */ 478 uint8_t enableddqscha; /* 479 * Byte offset 0x24, CSR Addr 0x54012, Direction=In 480 * Total number of DQ bits enabled in PHY Channel A 481 */ 482 uint8_t cspresentcha; /* 483 * Byte offset 0x25, CSR Addr 0x54012, Direction=In 484 * Indicates presence of DRAM at each chip select for PHY 485 * channel A. 486 * 0x1 = CS0 is populated with DRAM 487 * 0x3 = CS0 and CS1 are populated with DRAM 488 * 489 * All other encodings are illegal 490 */ 491 int8_t cdd_cha_rr_1_0; /* 492 * Byte offset 0x26, CSR Addr 0x54013, Direction=Out 493 * This is a signed integer value. 494 * Read to read critical delay difference from cs 1 to cs 0 495 * on Channel A. 496 */ 497 int8_t cdd_cha_rr_0_1; /* 498 * Byte offset 0x27, CSR Addr 0x54013, Direction=Out 499 * This is a signed integer value. 500 * Read to read critical delay difference from cs 0 to cs 1 501 * on Channel A. 502 */ 503 int8_t cdd_cha_rw_1_1; /* 504 * Byte offset 0x28, CSR Addr 0x54014, Direction=Out 505 * This is a signed integer value. 506 * Read to write critical delay difference from cs 1 to cs 1 507 * on Channel A. 508 */ 509 int8_t cdd_cha_rw_1_0; /* 510 * Byte offset 0x29, CSR Addr 0x54014, Direction=Out 511 * This is a signed integer value. 512 * Read to write critical delay difference from cs 1 to cs 0 513 * on Channel A. 514 */ 515 int8_t cdd_cha_rw_0_1; /* 516 * Byte offset 0x2a, CSR Addr 0x54015, Direction=Out 517 * This is a signed integer value. 518 * Read to write critical delay difference from cs 0 to cs 1 519 * on Channel A. 520 */ 521 int8_t cdd_cha_rw_0_0; /* 522 * Byte offset 0x2b, CSR Addr 0x54015, Direction=Out 523 * This is a signed integer value. 524 * Read to write critical delay difference from cs0 to cs 0 525 * on Channel A. 526 */ 527 int8_t cdd_cha_wr_1_1; /* 528 * Byte offset 0x2c, CSR Addr 0x54016, Direction=Out 529 * This is a signed integer value. 530 * Write to read critical delay difference from cs 1 to cs 1 531 * on Channel A. 532 */ 533 int8_t cdd_cha_wr_1_0; /* 534 * Byte offset 0x2d, CSR Addr 0x54016, Direction=Out 535 * This is a signed integer value. 536 * Write to read critical delay difference from cs 1 to cs 0 537 * on Channel A. 538 */ 539 int8_t cdd_cha_wr_0_1; /* 540 * Byte offset 0x2e, CSR Addr 0x54017, Direction=Out 541 * This is a signed integer value. 542 * Write to read critical delay difference from cs 0 to cs 1 543 * on Channel A. 544 */ 545 int8_t cdd_cha_wr_0_0; /* 546 * Byte offset 0x2f, CSR Addr 0x54017, Direction=Out 547 * This is a signed integer value. 548 * Write to read critical delay difference from cs 0 to cs 0 549 * on Channel A. 550 */ 551 int8_t cdd_cha_ww_1_0; /* 552 * Byte offset 0x30, CSR Addr 0x54018, Direction=Out 553 * This is a signed integer value. 554 * Write to write critical delay difference from cs 1 to cs 555 * 0 on Channel A. 556 */ 557 int8_t cdd_cha_ww_0_1; /* 558 * Byte offset 0x31, CSR Addr 0x54018, Direction=Out 559 * This is a signed integer value. 560 * Write to write critical delay difference from cs 0 to cs 561 * 1 on Channel A. 562 */ 563 uint8_t mr1_a0; /* 564 * Byte offset 0x32, CSR Addr 0x54019, Direction=In 565 * Value to be programmed in DRAM Mode Register 1 566 * {Channel A, Rank 0} 567 */ 568 uint8_t mr2_a0; /* 569 * Byte offset 0x33, CSR Addr 0x54019, Direction=In 570 * Value to be programmed in DRAM Mode Register 2 571 * {Channel A, Rank 0} 572 */ 573 uint8_t mr3_a0; /* 574 * Byte offset 0x34, CSR Addr 0x5401a, Direction=In 575 * Value to be programmed in DRAM Mode Register 3 576 * {Channel A, Rank 0} 577 */ 578 uint8_t mr4_a0; /* 579 * Byte offset 0x35, CSR Addr 0x5401a, Direction=In 580 * Value to be programmed in DRAM Mode Register 4 581 * {Channel A, Rank 0} 582 */ 583 uint8_t mr11_a0; /* 584 * Byte offset 0x36, CSR Addr 0x5401b, Direction=In 585 * Value to be programmed in DRAM Mode Register 11 586 * {Channel A, Rank 0} 587 */ 588 uint8_t mr12_a0; /* 589 * Byte offset 0x37, CSR Addr 0x5401b, Direction=In 590 * Value to be programmed in DRAM Mode Register 12 591 * {Channel A, Rank 0} 592 */ 593 uint8_t mr13_a0; /* 594 * Byte offset 0x38, CSR Addr 0x5401c, Direction=In 595 * Value to be programmed in DRAM Mode Register 13 596 * {Channel A, Rank 0} 597 */ 598 uint8_t mr14_a0; /* 599 * Byte offset 0x39, CSR Addr 0x5401c, Direction=In 600 * Value to be programmed in DRAM Mode Register 14 601 * {Channel A, Rank 0} 602 */ 603 uint8_t mr16_a0; /* 604 * Byte offset 0x3a, CSR Addr 0x5401d, Direction=In 605 * Value to be programmed in DRAM Mode Register 16 606 * {Channel A, Rank 0} 607 */ 608 uint8_t mr17_a0; /* 609 * Byte offset 0x3b, CSR Addr 0x5401d, Direction=In 610 * Value to be programmed in DRAM Mode Register 17 611 * {Channel A, Rank 0} 612 */ 613 uint8_t mr22_a0; /* 614 * Byte offset 0x3c, CSR Addr 0x5401e, Direction=In 615 * Value to be programmed in DRAM Mode Register 22 616 * {Channel A, Rank 0} 617 */ 618 uint8_t mr24_a0; /* 619 * Byte offset 0x3d, CSR Addr 0x5401e, Direction=In 620 * Value to be programmed in DRAM Mode Register 24 621 * {Channel A, Rank 0} 622 */ 623 uint8_t mr1_a1; /* 624 * Byte offset 0x3e, CSR Addr 0x5401f, Direction=In 625 * Value to be programmed in DRAM Mode Register 1 626 * {Channel A, Rank 1} 627 */ 628 uint8_t mr2_a1; /* 629 * Byte offset 0x3f, CSR Addr 0x5401f, Direction=In 630 * Value to be programmed in DRAM Mode Register 2 631 * {Channel A, Rank 1} 632 */ 633 uint8_t mr3_a1; /* 634 * Byte offset 0x40, CSR Addr 0x54020, Direction=In 635 * Value to be programmed in DRAM Mode Register 3 636 * {Channel A, Rank 1} 637 */ 638 uint8_t mr4_a1; /* 639 * Byte offset 0x41, CSR Addr 0x54020, Direction=In 640 * Value to be programmed in DRAM Mode Register 4 641 * {Channel A, Rank 1} 642 */ 643 uint8_t mr11_a1; /* 644 * Byte offset 0x42, CSR Addr 0x54021, Direction=In 645 * Value to be programmed in DRAM Mode Register 11 646 * {Channel A, Rank 1} 647 */ 648 uint8_t mr12_a1; /* 649 * Byte offset 0x43, CSR Addr 0x54021, Direction=In 650 * Value to be programmed in DRAM Mode Register 12 651 * {Channel A, Rank 1} 652 */ 653 uint8_t mr13_a1; /* 654 * Byte offset 0x44, CSR Addr 0x54022, Direction=In 655 * Value to be programmed in DRAM Mode Register 13 656 * {Channel A, Rank 1} 657 */ 658 uint8_t mr14_a1; /* 659 * Byte offset 0x45, CSR Addr 0x54022, Direction=In 660 * Value to be programmed in DRAM Mode Register 14 661 * {Channel A, Rank 1} 662 */ 663 uint8_t mr16_a1; /* 664 * Byte offset 0x46, CSR Addr 0x54023, Direction=In 665 * Value to be programmed in DRAM Mode Register 16 666 * {Channel A, Rank 1} 667 */ 668 uint8_t mr17_a1; /* 669 * Byte offset 0x47, CSR Addr 0x54023, Direction=In 670 * Value to be programmed in DRAM Mode Register 17 671 * {Channel A, Rank 1} 672 */ 673 uint8_t mr22_a1; /* 674 * Byte offset 0x48, CSR Addr 0x54024, Direction=In 675 * Value to be programmed in DRAM Mode Register 22 676 * {Channel A, Rank 1} 677 */ 678 uint8_t mr24_a1; /* 679 * Byte offset 0x49, CSR Addr 0x54024, Direction=In 680 * Value to be programmed in DRAM Mode Register 24 681 * {Channel A, Rank 1} 682 */ 683 uint8_t caterminatingrankcha; /* Byte offset 0x4a, CSR Addr 0x54025, Direction=In 684 * Terminating Rank for CA bus on Channel A 685 * 0x0 = Rank 0 is terminating rank 686 * 0x1 = Rank 1 is terminating rank 687 */ 688 uint8_t reserved4b; /* Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A */ 689 uint8_t reserved4c; /* Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A */ 690 uint8_t reserved4d; /* Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A */ 691 uint8_t reserved4e; /* Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A */ 692 uint8_t reserved4f; /* Byte offset 0x4f, CSR Addr 0x54027, Direction=N/A */ 693 uint8_t reserved50; /* Byte offset 0x50, CSR Addr 0x54028, Direction=N/A */ 694 uint8_t reserved51; /* Byte offset 0x51, CSR Addr 0x54028, Direction=N/A */ 695 uint8_t reserved52; /* Byte offset 0x52, CSR Addr 0x54029, Direction=N/A */ 696 uint8_t reserved53; /* Byte offset 0x53, CSR Addr 0x54029, Direction=N/A */ 697 uint8_t reserved54; /* Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A */ 698 uint8_t reserved55; /* Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A */ 699 uint8_t reserved56; /* Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A */ 700 uint8_t enableddqschb; /* 701 * Byte offset 0x57, CSR Addr 0x5402b, Direction=In 702 * Total number of DQ bits enabled in PHY Channel B 703 */ 704 uint8_t cspresentchb; /* 705 * Byte offset 0x58, CSR Addr 0x5402c, Direction=In 706 * Indicates presence of DRAM at each chip select for PHY 707 * channel B. 708 * 0x0 = No chip selects are populated with DRAM 709 * 0x1 = CS0 is populated with DRAM 710 * 0x3 = CS0 and CS1 are populated with DRAM 711 * 712 * All other encodings are illegal 713 */ 714 int8_t cdd_chb_rr_1_0; /* 715 * Byte offset 0x59, CSR Addr 0x5402c, Direction=Out 716 * This is a signed integer value. 717 * Read to read critical delay difference from cs 1 to cs 0 718 * on Channel B. 719 */ 720 int8_t cdd_chb_rr_0_1; /* 721 * Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out 722 * This is a signed integer value. 723 * Read to read critical delay difference from cs 0 to cs 1 724 * on Channel B. 725 */ 726 int8_t cdd_chb_rw_1_1; /* 727 * Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out 728 * This is a signed integer value. 729 * Read to write critical delay difference from cs 1 to cs 1 730 * on Channel B. 731 */ 732 int8_t cdd_chb_rw_1_0; /* 733 * Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out 734 * This is a signed integer value. 735 * Read to write critical delay difference from cs 1 to cs 0 736 * on Channel B. 737 */ 738 int8_t cdd_chb_rw_0_1; /* 739 * Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out 740 * This is a signed integer value. 741 * Read to write critical delay difference from cs 0 to cs 1 742 * on Channel B. 743 */ 744 int8_t cdd_chb_rw_0_0; /* 745 * Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out 746 * This is a signed integer value. 747 * Read to write critical delay difference from cs01 to cs 0 748 * on Channel B. 749 */ 750 int8_t cdd_chb_wr_1_1; /* 751 * Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out 752 * This is a signed integer value. 753 * Write to read critical delay difference from cs 1 to cs 1 754 * on Channel B. 755 */ 756 int8_t cdd_chb_wr_1_0; /* 757 * Byte offset 0x60, CSR Addr 0x54030, Direction=Out 758 * This is a signed integer value. 759 * Write to read critical delay difference from cs 1 to cs 0 760 * on Channel B. 761 */ 762 int8_t cdd_chb_wr_0_1; /* 763 * Byte offset 0x61, CSR Addr 0x54030, Direction=Out 764 * This is a signed integer value. 765 * Write to read critical delay difference from cs 0 to cs 1 766 * on Channel B. 767 */ 768 int8_t cdd_chb_wr_0_0; /* 769 * Byte offset 0x62, CSR Addr 0x54031, Direction=Out 770 * This is a signed integer value. 771 * Write to read critical delay difference from cs 0 to cs 0 772 * on Channel B. 773 */ 774 int8_t cdd_chb_ww_1_0; /* 775 * Byte offset 0x63, CSR Addr 0x54031, Direction=Out 776 * This is a signed integer value. 777 * Write to write critical delay difference from cs 1 to cs 778 * 0 on Channel B. 779 */ 780 int8_t cdd_chb_ww_0_1; /* 781 * Byte offset 0x64, CSR Addr 0x54032, Direction=Out 782 * This is a signed integer value. 783 * Write to write critical delay difference from cs 0 to cs 784 * 1 on Channel B. 785 */ 786 uint8_t mr1_b0; /* 787 * Byte offset 0x65, CSR Addr 0x54032, Direction=In 788 * Value to be programmed in DRAM Mode Register 1 789 * {Channel B, Rank 0} 790 */ 791 uint8_t mr2_b0; /* 792 * Byte offset 0x66, CSR Addr 0x54033, Direction=In 793 * Value to be programmed in DRAM Mode Register 2 794 * {Channel B, Rank 0} 795 */ 796 uint8_t mr3_b0; /* 797 * Byte offset 0x67, CSR Addr 0x54033, Direction=In 798 * Value to be programmed in DRAM Mode Register 3 799 * {Channel B, Rank 0} 800 */ 801 uint8_t mr4_b0; /* 802 * Byte offset 0x68, CSR Addr 0x54034, Direction=In 803 * Value to be programmed in DRAM Mode Register 4 804 * {Channel B, Rank 0} 805 */ 806 uint8_t mr11_b0; /* 807 * Byte offset 0x69, CSR Addr 0x54034, Direction=In 808 * Value to be programmed in DRAM Mode Register 11 809 * {Channel B, Rank 0} 810 */ 811 uint8_t mr12_b0; /* 812 * Byte offset 0x6a, CSR Addr 0x54035, Direction=In 813 * Value to be programmed in DRAM Mode Register 12 814 * {Channel B, Rank 0} 815 */ 816 uint8_t mr13_b0; /* 817 * Byte offset 0x6b, CSR Addr 0x54035, Direction=In 818 * Value to be programmed in DRAM Mode Register 13 819 * {Channel B, Rank 0} 820 */ 821 uint8_t mr14_b0; /* 822 * Byte offset 0x6c, CSR Addr 0x54036, Direction=In 823 * Value to be programmed in DRAM Mode Register 14 824 * {Channel B, Rank 0} 825 */ 826 uint8_t mr16_b0; /* 827 * Byte offset 0x6d, CSR Addr 0x54036, Direction=In 828 * Value to be programmed in DRAM Mode Register 16 829 * {Channel B, Rank 0} 830 */ 831 uint8_t mr17_b0; /* 832 * Byte offset 0x6e, CSR Addr 0x54037, Direction=In 833 * Value to be programmed in DRAM Mode Register 17 834 * {Channel B, Rank 0} 835 */ 836 uint8_t mr22_b0; /* 837 * Byte offset 0x6f, CSR Addr 0x54037, Direction=In 838 * Value to be programmed in DRAM Mode Register 22 839 * {Channel B, Rank 0} 840 */ 841 uint8_t mr24_b0; /* 842 * Byte offset 0x70, CSR Addr 0x54038, Direction=In 843 * Value to be programmed in DRAM Mode Register 24 844 * {Channel B, Rank 0} 845 */ 846 uint8_t mr1_b1; /* 847 * Byte offset 0x71, CSR Addr 0x54038, Direction=In 848 * Value to be programmed in DRAM Mode Register 1 849 * {Channel B, Rank 1} 850 */ 851 uint8_t mr2_b1; /* 852 * Byte offset 0x72, CSR Addr 0x54039, Direction=In 853 * Value to be programmed in DRAM Mode Register 2 854 * {Channel B, Rank 1} 855 */ 856 uint8_t mr3_b1; /* 857 * Byte offset 0x73, CSR Addr 0x54039, Direction=In 858 * Value to be programmed in DRAM Mode Register 3 859 * {Channel B, Rank 1} 860 */ 861 uint8_t mr4_b1; /* 862 * Byte offset 0x74, CSR Addr 0x5403a, Direction=In 863 * Value to be programmed in DRAM Mode Register 4 864 * {Channel B, Rank 1} 865 */ 866 uint8_t mr11_b1; /* 867 * Byte offset 0x75, CSR Addr 0x5403a, Direction=In 868 * Value to be programmed in DRAM Mode Register 11 869 * {Channel B, Rank 1} 870 */ 871 uint8_t mr12_b1; /* 872 * Byte offset 0x76, CSR Addr 0x5403b, Direction=In 873 * Value to be programmed in DRAM Mode Register 12 874 * {Channel B, Rank 1} 875 */ 876 uint8_t mr13_b1; /* 877 * Byte offset 0x77, CSR Addr 0x5403b, Direction=In 878 * Value to be programmed in DRAM Mode Register 13 879 * {Channel B, Rank 1} 880 */ 881 uint8_t mr14_b1; /* 882 * Byte offset 0x78, CSR Addr 0x5403c, Direction=In 883 * Value to be programmed in DRAM Mode Register 14 884 * {Channel B, Rank 1} 885 */ 886 uint8_t mr16_b1; /* 887 * Byte offset 0x79, CSR Addr 0x5403c, Direction=In 888 * Value to be programmed in DRAM Mode Register 16 889 * {Channel B, Rank 1} 890 */ 891 uint8_t mr17_b1; /* 892 * Byte offset 0x7a, CSR Addr 0x5403d, Direction=In 893 * Value to be programmed in DRAM Mode Register 17 894 * {Channel B, Rank 1} 895 */ 896 uint8_t mr22_b1; /* 897 * Byte offset 0x7b, CSR Addr 0x5403d, Direction=In 898 * Value to be programmed in DRAM Mode Register 22 899 * {Channel B, Rank 1} 900 */ 901 uint8_t mr24_b1; /* 902 * Byte offset 0x7c, CSR Addr 0x5403e, Direction=In 903 * Value to be programmed in DRAM Mode Register 24 904 * {Channel B, Rank 1} 905 */ 906 uint8_t caterminatingrankchb; /* Byte offset 0x7d, CSR Addr 0x5403e, Direction=In 907 * Terminating Rank for CA bus on Channel B 908 * 0x0 = Rank 0 is terminating rank 909 * 0x1 = Rank 1 is terminating rank 910 */ 911 uint8_t reserved7e; /* Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A */ 912 uint8_t reserved7f; /* Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A */ 913 uint8_t reserved80; /* Byte offset 0x80, CSR Addr 0x54040, Direction=N/A */ 914 uint8_t reserved81; /* Byte offset 0x81, CSR Addr 0x54040, Direction=N/A */ 915 uint8_t reserved82; /* Byte offset 0x82, CSR Addr 0x54041, Direction=N/A */ 916 uint8_t reserved83; /* Byte offset 0x83, CSR Addr 0x54041, Direction=N/A */ 917 uint8_t reserved84; /* Byte offset 0x84, CSR Addr 0x54042, Direction=N/A */ 918 uint8_t reserved85; /* Byte offset 0x85, CSR Addr 0x54042, Direction=N/A */ 919 uint8_t reserved86; /* Byte offset 0x86, CSR Addr 0x54043, Direction=N/A */ 920 uint8_t reserved87; /* Byte offset 0x87, CSR Addr 0x54043, Direction=N/A */ 921 uint8_t reserved88; /* Byte offset 0x88, CSR Addr 0x54044, Direction=N/A */ 922 uint8_t reserved89; /* Byte offset 0x89, CSR Addr 0x54044, Direction=N/A */ 923 } __packed __aligned(2); 924 925 #endif /* MNPMUSRAMMSGBLOCK_LPDDR4_H */ 926