1 /************************************************************************** 2 * 3 * Copyright 2013 Advanced Micro Devices, Inc. 4 * 5 * SPDX-License-Identifier: MIT 6 * 7 **************************************************************************/ 8 9 #ifndef RADEON_VCE_H 10 #define RADEON_VCE_H 11 12 #include "radeon_video.h" 13 #include "util/list.h" 14 15 #define RVCE_CS(value) (enc->cs.current.buf[enc->cs.current.cdw++] = (value)) 16 #define RVCE_BEGIN(cmd) \ 17 { \ 18 uint32_t *begin = &enc->cs.current.buf[enc->cs.current.cdw++]; \ 19 RVCE_CS(cmd) 20 #define RVCE_READ(buf, domain, off) \ 21 si_vce_add_buffer(enc, (buf), RADEON_USAGE_READ, (domain), (off)) 22 #define RVCE_WRITE(buf, domain, off) \ 23 si_vce_add_buffer(enc, (buf), RADEON_USAGE_WRITE, (domain), (off)) 24 #define RVCE_READWRITE(buf, domain, off) \ 25 si_vce_add_buffer(enc, (buf), RADEON_USAGE_READWRITE, (domain), (off)) 26 #define RVCE_END() \ 27 *begin = (&enc->cs.current.buf[enc->cs.current.cdw] - begin) * 4; \ 28 } 29 30 #define RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE (4096 * 16 * 2.5) 31 #define RVCE_MAX_AUX_BUFFER_NUM 4 32 33 struct si_screen; 34 35 /* driver dependent callback */ 36 typedef void (*rvce_get_buffer)(struct pipe_resource *resource, struct pb_buffer_lean **handle, 37 struct radeon_surf **surface); 38 39 struct rvce_rate_control { 40 uint32_t rc_method; 41 uint32_t target_bitrate; 42 uint32_t peak_bitrate; 43 uint32_t frame_rate_num; 44 uint32_t gop_size; 45 uint32_t quant_i_frames; 46 uint32_t quant_p_frames; 47 uint32_t quant_b_frames; 48 uint32_t vbv_buffer_size; 49 uint32_t frame_rate_den; 50 uint32_t vbv_buf_lv; 51 uint32_t max_au_size; 52 uint32_t qp_initial_mode; 53 uint32_t target_bits_picture; 54 uint32_t peak_bits_picture_integer; 55 uint32_t peak_bits_picture_fraction; 56 uint32_t min_qp; 57 uint32_t max_qp; 58 uint32_t skip_frame_enable; 59 uint32_t fill_data_enable; 60 uint32_t enforce_hrd; 61 uint32_t b_pics_delta_qp; 62 uint32_t ref_b_pics_delta_qp; 63 uint32_t rc_reinit_disable; 64 uint32_t enc_lcvbr_init_qp_flag; 65 uint32_t lcvbrsatd_based_nonlinear_bit_budget_flag; 66 }; 67 68 struct rvce_motion_estimation { 69 uint32_t enc_ime_decimation_search; 70 uint32_t motion_est_half_pixel; 71 uint32_t motion_est_quarter_pixel; 72 uint32_t disable_favor_pmv_point; 73 uint32_t force_zero_point_center; 74 uint32_t lsmvert; 75 uint32_t enc_search_range_x; 76 uint32_t enc_search_range_y; 77 uint32_t enc_search1_range_x; 78 uint32_t enc_search1_range_y; 79 uint32_t disable_16x16_frame1; 80 uint32_t disable_satd; 81 uint32_t enable_amd; 82 uint32_t enc_disable_sub_mode; 83 uint32_t enc_ime_skip_x; 84 uint32_t enc_ime_skip_y; 85 uint32_t enc_en_ime_overw_dis_subm; 86 uint32_t enc_ime_overw_dis_subm_no; 87 uint32_t enc_ime2_search_range_x; 88 uint32_t enc_ime2_search_range_y; 89 uint32_t parallel_mode_speedup_enable; 90 uint32_t fme0_enc_disable_sub_mode; 91 uint32_t fme1_enc_disable_sub_mode; 92 uint32_t ime_sw_speedup_enable; 93 }; 94 95 struct rvce_pic_control { 96 uint32_t enc_use_constrained_intra_pred; 97 uint32_t enc_cabac_enable; 98 uint32_t enc_cabac_idc; 99 uint32_t enc_loop_filter_disable; 100 int32_t enc_lf_beta_offset; 101 int32_t enc_lf_alpha_c0_offset; 102 uint32_t enc_crop_left_offset; 103 uint32_t enc_crop_right_offset; 104 uint32_t enc_crop_top_offset; 105 uint32_t enc_crop_bottom_offset; 106 uint32_t enc_num_mbs_per_slice; 107 uint32_t enc_intra_refresh_num_mbs_per_slot; 108 uint32_t enc_force_intra_refresh; 109 uint32_t enc_force_imb_period; 110 uint32_t enc_pic_order_cnt_type; 111 uint32_t log2_max_pic_order_cnt_lsb_minus4; 112 uint32_t enc_sps_id; 113 uint32_t enc_pps_id; 114 uint32_t enc_constraint_set_flags; 115 uint32_t enc_b_pic_pattern; 116 uint32_t weight_pred_mode_b_picture; 117 uint32_t enc_number_of_reference_frames; 118 uint32_t enc_max_num_ref_frames; 119 uint32_t enc_num_default_active_ref_l0; 120 uint32_t enc_num_default_active_ref_l1; 121 uint32_t enc_slice_mode; 122 uint32_t enc_max_slice_size; 123 }; 124 125 struct rvce_task_info { 126 uint32_t offset_of_next_task_info; 127 uint32_t task_operation; 128 uint32_t reference_picture_dependency; 129 uint32_t collocate_flag_dependency; 130 uint32_t feedback_index; 131 uint32_t video_bitstream_ring_index; 132 }; 133 134 struct rvce_feedback_buf_pkg { 135 uint32_t feedback_ring_address_hi; 136 uint32_t feedback_ring_address_lo; 137 uint32_t feedback_ring_size; 138 }; 139 140 struct rvce_rdo { 141 uint32_t enc_disable_tbe_pred_i_frame; 142 uint32_t enc_disable_tbe_pred_p_frame; 143 uint32_t use_fme_interpol_y; 144 uint32_t use_fme_interpol_uv; 145 uint32_t use_fme_intrapol_y; 146 uint32_t use_fme_intrapol_uv; 147 uint32_t use_fme_interpol_y_1; 148 uint32_t use_fme_interpol_uv_1; 149 uint32_t use_fme_intrapol_y_1; 150 uint32_t use_fme_intrapol_uv_1; 151 uint32_t enc_16x16_cost_adj; 152 uint32_t enc_skip_cost_adj; 153 uint32_t enc_force_16x16_skip; 154 uint32_t enc_disable_threshold_calc_a; 155 uint32_t enc_luma_coeff_cost; 156 uint32_t enc_luma_mb_coeff_cost; 157 uint32_t enc_chroma_coeff_cost; 158 }; 159 160 struct rvce_enc_operation { 161 uint32_t insert_headers; 162 uint32_t picture_structure; 163 uint32_t allowed_max_bitstream_size; 164 uint32_t force_refresh_map; 165 uint32_t insert_aud; 166 uint32_t end_of_sequence; 167 uint32_t end_of_stream; 168 uint32_t input_picture_luma_address_hi; 169 uint32_t input_picture_luma_address_lo; 170 uint32_t input_picture_chroma_address_hi; 171 uint32_t input_picture_chroma_address_lo; 172 uint32_t enc_input_frame_y_pitch; 173 uint32_t enc_input_pic_luma_pitch; 174 uint32_t enc_input_pic_chroma_pitch; 175 ; 176 union { 177 struct { 178 uint8_t enc_input_pic_addr_mode; 179 uint8_t enc_input_pic_swizzle_mode; 180 uint8_t enc_disable_two_pipe_mode; 181 uint8_t enc_disable_mb_offloading; 182 }; 183 uint32_t enc_input_pic_addr_array_disable2pipe_disablemboffload; 184 }; 185 uint32_t enc_input_pic_tile_config; 186 uint32_t enc_pic_type; 187 uint32_t enc_idr_flag; 188 uint32_t enc_idr_pic_id; 189 uint32_t enc_mgs_key_pic; 190 uint32_t enc_reference_flag; 191 uint32_t enc_temporal_layer_index; 192 uint32_t num_ref_idx_active_override_flag; 193 uint32_t num_ref_idx_l0_active_minus1; 194 uint32_t num_ref_idx_l1_active_minus1; 195 uint32_t enc_ref_list_modification_op[4]; 196 uint32_t enc_ref_list_modification_num[4]; 197 uint32_t enc_decoded_picture_marking_op[4]; 198 uint32_t enc_decoded_picture_marking_num[4]; 199 uint32_t enc_decoded_picture_marking_idx[4]; 200 uint32_t enc_decoded_ref_base_picture_marking_op[4]; 201 uint32_t enc_decoded_ref_base_picture_marking_num[4]; 202 uint32_t l0_dpb_idx; 203 uint32_t l0_picture_structure; 204 uint32_t l0_enc_pic_type; 205 uint32_t l0_frame_number; 206 uint32_t l0_picture_order_count; 207 uint32_t l0_luma_offset; 208 uint32_t l0_chroma_offset; 209 uint32_t l1_dpb_idx; 210 uint32_t l1_picture_structure; 211 uint32_t l1_enc_pic_type; 212 uint32_t l1_frame_number; 213 uint32_t l1_picture_order_count; 214 uint32_t l1_luma_offset; 215 uint32_t l1_chroma_offset; 216 uint32_t cur_dpb_idx; 217 uint32_t enc_reconstructed_luma_offset; 218 uint32_t enc_reconstructed_chroma_offset; 219 ; 220 uint32_t enc_coloc_buffer_offset; 221 uint32_t enc_reconstructed_ref_base_picture_luma_offset; 222 uint32_t enc_reconstructed_ref_base_picture_chroma_offset; 223 uint32_t enc_reference_ref_base_picture_luma_offset; 224 uint32_t enc_reference_ref_base_picture_chroma_offset; 225 uint32_t picture_count; 226 uint32_t frame_number; 227 uint32_t picture_order_count; 228 uint32_t num_i_pic_remain_in_rcgop; 229 uint32_t num_p_pic_remain_in_rcgop; 230 uint32_t num_b_pic_remain_in_rcgop; 231 uint32_t num_ir_pic_remain_in_rcgop; 232 uint32_t enable_intra_refresh; 233 uint32_t aq_variance_en; 234 uint32_t aq_block_size; 235 uint32_t aq_mb_variance_sel; 236 uint32_t aq_frame_variance_sel; 237 uint32_t aq_param_a; 238 uint32_t aq_param_b; 239 uint32_t aq_param_c; 240 uint32_t aq_param_d; 241 uint32_t aq_param_e; 242 uint32_t context_in_sfb; 243 }; 244 245 struct rvce_enc_create { 246 uint32_t enc_use_circular_buffer; 247 uint32_t enc_profile; 248 uint32_t enc_level; 249 uint32_t enc_pic_struct_restriction; 250 uint32_t enc_image_width; 251 uint32_t enc_image_height; 252 uint32_t enc_ref_pic_luma_pitch; 253 uint32_t enc_ref_pic_chroma_pitch; 254 uint32_t enc_ref_y_height_in_qw; 255 uint32_t enc_ref_pic_addr_array_enc_pic_struct_restriction_disable_rdo; 256 uint32_t enc_pre_encode_context_buffer_offset; 257 uint32_t enc_pre_encode_input_luma_buffer_offset; 258 uint32_t enc_pre_encode_input_chroma_buffer_offset; 259 union { 260 struct { 261 uint8_t enc_pre_encode_mode; 262 uint8_t enc_pre_encode_chroma_flag; 263 uint8_t enc_vbaq_mode; 264 uint8_t enc_scene_change_sensitivity; 265 }; 266 uint32_t enc_pre_encode_mode_chromaflag_vbaqmode_scenechangesensitivity; 267 }; 268 }; 269 270 struct rvce_config_ext { 271 uint32_t enc_enable_perf_logging; 272 }; 273 274 struct rvce_h264_enc_pic { 275 struct rvce_rate_control rc; 276 struct rvce_motion_estimation me; 277 struct rvce_pic_control pc; 278 struct rvce_task_info ti; 279 struct rvce_feedback_buf_pkg fb; 280 struct rvce_rdo rdo; 281 struct rvce_enc_operation eo; 282 struct rvce_enc_create ec; 283 struct rvce_config_ext ce; 284 285 unsigned quant_i_frames; 286 unsigned quant_p_frames; 287 unsigned quant_b_frames; 288 289 enum pipe_h2645_enc_picture_type picture_type; 290 unsigned frame_num; 291 unsigned frame_num_cnt; 292 unsigned p_remain; 293 unsigned i_remain; 294 unsigned idr_pic_id; 295 unsigned pic_order_cnt; 296 unsigned addrmode_arraymode_disrdo_distwoinstants; 297 298 bool not_referenced; 299 bool is_idr; 300 }; 301 302 /* VCE encoder representation */ 303 struct rvce_encoder { 304 struct pipe_video_codec base; 305 306 /* version specific packets */ 307 void (*session)(struct rvce_encoder *enc); 308 void (*create)(struct rvce_encoder *enc); 309 void (*feedback)(struct rvce_encoder *enc); 310 void (*rate_control)(struct rvce_encoder *enc); 311 void (*config_extension)(struct rvce_encoder *enc); 312 void (*pic_control)(struct rvce_encoder *enc); 313 void (*motion_estimation)(struct rvce_encoder *enc); 314 void (*rdo)(struct rvce_encoder *enc); 315 void (*config)(struct rvce_encoder *enc); 316 void (*encode)(struct rvce_encoder *enc); 317 void (*destroy)(struct rvce_encoder *enc); 318 void (*task_info)(struct rvce_encoder *enc, uint32_t op, uint32_t fb_idx); 319 void (*si_get_pic_param)(struct rvce_encoder *enc, struct pipe_h264_enc_picture_desc *pic); 320 321 unsigned stream_handle; 322 323 struct pipe_screen *screen; 324 struct radeon_winsys *ws; 325 struct radeon_cmdbuf cs; 326 327 rvce_get_buffer get_buffer; 328 329 struct pb_buffer_lean *handle; 330 struct radeon_surf *luma; 331 struct radeon_surf *chroma; 332 333 struct pb_buffer_lean *bs_handle; 334 unsigned bs_size; 335 unsigned bs_offset; 336 337 unsigned dpb_slots; 338 339 struct rvid_buffer *fb; 340 struct rvid_buffer dpb; 341 struct pipe_h264_enc_picture_desc pic; 342 struct rvce_h264_enc_pic enc_pic; 343 344 bool use_vm; 345 bool dual_pipe; 346 }; 347 348 struct rvce_output_unit_segment { 349 bool is_slice; 350 unsigned size; 351 unsigned offset; 352 }; 353 354 struct rvce_feedback_data { 355 unsigned num_segments; 356 struct rvce_output_unit_segment segments[]; 357 }; 358 359 unsigned int si_vce_write_sps(struct rvce_encoder *enc, uint8_t nal_byte, uint8_t *out); 360 unsigned int si_vce_write_pps(struct rvce_encoder *enc, uint8_t nal_byte, uint8_t *out); 361 362 /* CPB handling functions */ 363 void si_vce_frame_offset(struct rvce_encoder *enc, unsigned slot, signed *luma_offset, 364 signed *chroma_offset); 365 366 struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context, 367 const struct pipe_video_codec *templat, 368 struct radeon_winsys *ws, 369 rvce_get_buffer get_buffer); 370 371 bool si_vce_is_fw_version_supported(struct si_screen *sscreen); 372 373 void si_vce_add_buffer(struct rvce_encoder *enc, struct pb_buffer_lean *buf, unsigned usage, 374 enum radeon_bo_domain domain, signed offset); 375 376 /* init vce fw 52 specific callbacks */ 377 void si_vce_52_init(struct rvce_encoder *enc); 378 379 #endif 380